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Searched refs:phy_set_bits_mmd (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/net/phy/
H A Dadin1100.c102 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL, in adin_config_aneg()
111 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN); in adin_config_aneg()
120 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, in adin_config_aneg()
168 return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL, in adin_set_loopback()
180 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN); in adin_soft_reset()
H A Dnxp-c45-tja11xx.c831 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_or_falling()
843 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
852 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
1215 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_start_op()
1222 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1247 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_config_intr()
1315 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_cable_test_start()
1317 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test, in nxp_c45_cable_test_start()
1383 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_link_change_notify()
1414 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_LINK_DROP_COUNTER, in nxp_c45_counters_enable()
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H A Dmediatek-ge-soc.c339 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, in cal_cycle()
559 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, in tx_vcm_cal_sw()
563 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, in tx_vcm_cal_sw()
574 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
585 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
596 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
607 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
893 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in mt798x_phy_eee()
921 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, in mt798x_phy_eee()
930 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, in mt798x_phy_eee()
H A Dphy-c45.c70 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_suspend()
345 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_restart_aneg()
1171 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_fast_retrain()
1176 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, in genphy_c45_fast_retrain()
1182 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain()
1343 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
H A Dmarvell10g.c319 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_down()
342 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_up()
623 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype()
676 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_set_mactype()
1290 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1319 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
H A Dmxl-gpy.c696 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
703 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
710 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
723 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
H A Ddp83td510.c67 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
H A Dmarvell-88x2222.c72 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, in mv2222_tx_disable()
102 int ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL, in mv2222_enable_aneg()
H A Ddp83822.c409 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, in dp83822_config_init()
470 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, in dp83822_config_init()
H A Dadin.c727 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_soft_reset()
848 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN, in adin_cable_test_start()
H A Ddp83867.c483 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, in dp83867_config_port_mirroring()
901 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, in dp83867_config_init()
H A Ddp83tc811.c381 phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, in dp83811_resume()
H A Dmicrel.c4271 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin)); in lan8841_ptp_perout_on()
4275 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin)); in lan8841_ptp_perout_on()
4279 return phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin)); in lan8841_ptp_perout_on()
4359 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1, in lan8841_ptp_enable_event()
4362 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2, in lan8841_ptp_enable_event()
4517 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin)); in lan8841_ptp_extts_on()
H A Ddp83869.c500 return phy_set_bits_mmd(phydev, DP83869_DEVADDR, in dp83869_config_port_mirroring()
H A Daquantia_main.c694 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, in aqr107_suspend()
H A Dphy.c1566 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, in phy_init_eee()
/openbmc/linux/include/linux/
H A Dphy.h1480 static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad, in phy_set_bits_mmd() function