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Searched refs:mmIH_RB_WPTR_ADDR_HI (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_1_0_d.h234 #define mmIH_RB_WPTR_ADDR_HI 0x0F84 macro
H A Dosssys_4_0_1_offset.h130 #define mmIH_RB_WPTR_ADDR_HI macro
H A Dosssys_4_0_offset.h130 #define mmIH_RB_WPTR_ADDR_HI macro
H A Dosssys_5_0_0_offset.h130 #define mmIH_RB_WPTR_ADDR_HI macro
H A Dosssys_4_2_0_offset.h132 #define mmIH_RB_WPTR_ADDR_HI macro
H A Doss_2_4_d.h47 #define mmIH_RB_WPTR_ADDR_HI 0xe34 macro
H A Doss_3_0_1_d.h47 #define mmIH_RB_WPTR_ADDR_HI 0xe34 macro
H A Doss_3_0_d.h47 #define mmIH_RB_WPTR_ADDR_HI 0xe34 macro
H A Doss_2_0_d.h47 #define mmIH_RB_WPTR_ADDR_HI 0xf84 macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dcik_ih.c137 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in cik_ih_irq_init()
H A Diceland_ih.c139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in iceland_ih_irq_init()
H A Dcz_ih.c139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in cz_ih_irq_init()
H A Dtonga_ih.c139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in tonga_ih_irq_init()
H A Dvega10_ih.c60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); in vega10_ih_init_register_offset()
H A Dvega20_ih.c68 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); in vega20_ih_init_register_offset()
H A Dnavi10_ih.c62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); in navi10_ih_init_register_offset()