13d220cc3SHawking Zhang /* 23d220cc3SHawking Zhang * Copyright (C) 2019 Advanced Micro Devices, Inc. 33d220cc3SHawking Zhang * 43d220cc3SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 53d220cc3SHawking Zhang * copy of this software and associated documentation files (the "Software"), 63d220cc3SHawking Zhang * to deal in the Software without restriction, including without limitation 73d220cc3SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 83d220cc3SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 93d220cc3SHawking Zhang * Software is furnished to do so, subject to the following conditions: 103d220cc3SHawking Zhang * 113d220cc3SHawking Zhang * The above copyright notice and this permission notice shall be included 123d220cc3SHawking Zhang * in all copies or substantial portions of the Software. 133d220cc3SHawking Zhang * 143d220cc3SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 153d220cc3SHawking Zhang * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 163d220cc3SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 173d220cc3SHawking Zhang * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 183d220cc3SHawking Zhang * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 193d220cc3SHawking Zhang * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 203d220cc3SHawking Zhang */ 213d220cc3SHawking Zhang #ifndef _osssys_5_0_0_OFFSET_HEADER 223d220cc3SHawking Zhang #define _osssys_5_0_0_OFFSET_HEADER 233d220cc3SHawking Zhang 243d220cc3SHawking Zhang 253d220cc3SHawking Zhang 263d220cc3SHawking Zhang // addressBlock: osssys_osssysdec 273d220cc3SHawking Zhang // base address: 0x4280 283d220cc3SHawking Zhang #define mmIH_VMID_0_LUT 0x0000 293d220cc3SHawking Zhang #define mmIH_VMID_0_LUT_BASE_IDX 0 303d220cc3SHawking Zhang #define mmIH_VMID_1_LUT 0x0001 313d220cc3SHawking Zhang #define mmIH_VMID_1_LUT_BASE_IDX 0 323d220cc3SHawking Zhang #define mmIH_VMID_2_LUT 0x0002 333d220cc3SHawking Zhang #define mmIH_VMID_2_LUT_BASE_IDX 0 343d220cc3SHawking Zhang #define mmIH_VMID_3_LUT 0x0003 353d220cc3SHawking Zhang #define mmIH_VMID_3_LUT_BASE_IDX 0 363d220cc3SHawking Zhang #define mmIH_VMID_4_LUT 0x0004 373d220cc3SHawking Zhang #define mmIH_VMID_4_LUT_BASE_IDX 0 383d220cc3SHawking Zhang #define mmIH_VMID_5_LUT 0x0005 393d220cc3SHawking Zhang #define mmIH_VMID_5_LUT_BASE_IDX 0 403d220cc3SHawking Zhang #define mmIH_VMID_6_LUT 0x0006 413d220cc3SHawking Zhang #define mmIH_VMID_6_LUT_BASE_IDX 0 423d220cc3SHawking Zhang #define mmIH_VMID_7_LUT 0x0007 433d220cc3SHawking Zhang #define mmIH_VMID_7_LUT_BASE_IDX 0 443d220cc3SHawking Zhang #define mmIH_VMID_8_LUT 0x0008 453d220cc3SHawking Zhang #define mmIH_VMID_8_LUT_BASE_IDX 0 463d220cc3SHawking Zhang #define mmIH_VMID_9_LUT 0x0009 473d220cc3SHawking Zhang #define mmIH_VMID_9_LUT_BASE_IDX 0 483d220cc3SHawking Zhang #define mmIH_VMID_10_LUT 0x000a 493d220cc3SHawking Zhang #define mmIH_VMID_10_LUT_BASE_IDX 0 503d220cc3SHawking Zhang #define mmIH_VMID_11_LUT 0x000b 513d220cc3SHawking Zhang #define mmIH_VMID_11_LUT_BASE_IDX 0 523d220cc3SHawking Zhang #define mmIH_VMID_12_LUT 0x000c 533d220cc3SHawking Zhang #define mmIH_VMID_12_LUT_BASE_IDX 0 543d220cc3SHawking Zhang #define mmIH_VMID_13_LUT 0x000d 553d220cc3SHawking Zhang #define mmIH_VMID_13_LUT_BASE_IDX 0 563d220cc3SHawking Zhang #define mmIH_VMID_14_LUT 0x000e 573d220cc3SHawking Zhang #define mmIH_VMID_14_LUT_BASE_IDX 0 583d220cc3SHawking Zhang #define mmIH_VMID_15_LUT 0x000f 593d220cc3SHawking Zhang #define mmIH_VMID_15_LUT_BASE_IDX 0 603d220cc3SHawking Zhang #define mmIH_VMID_0_LUT_MM 0x0010 613d220cc3SHawking Zhang #define mmIH_VMID_0_LUT_MM_BASE_IDX 0 623d220cc3SHawking Zhang #define mmIH_VMID_1_LUT_MM 0x0011 633d220cc3SHawking Zhang #define mmIH_VMID_1_LUT_MM_BASE_IDX 0 643d220cc3SHawking Zhang #define mmIH_VMID_2_LUT_MM 0x0012 653d220cc3SHawking Zhang #define mmIH_VMID_2_LUT_MM_BASE_IDX 0 663d220cc3SHawking Zhang #define mmIH_VMID_3_LUT_MM 0x0013 673d220cc3SHawking Zhang #define mmIH_VMID_3_LUT_MM_BASE_IDX 0 683d220cc3SHawking Zhang #define mmIH_VMID_4_LUT_MM 0x0014 693d220cc3SHawking Zhang #define mmIH_VMID_4_LUT_MM_BASE_IDX 0 703d220cc3SHawking Zhang #define mmIH_VMID_5_LUT_MM 0x0015 713d220cc3SHawking Zhang #define mmIH_VMID_5_LUT_MM_BASE_IDX 0 723d220cc3SHawking Zhang #define mmIH_VMID_6_LUT_MM 0x0016 733d220cc3SHawking Zhang #define mmIH_VMID_6_LUT_MM_BASE_IDX 0 743d220cc3SHawking Zhang #define mmIH_VMID_7_LUT_MM 0x0017 753d220cc3SHawking Zhang #define mmIH_VMID_7_LUT_MM_BASE_IDX 0 763d220cc3SHawking Zhang #define mmIH_VMID_8_LUT_MM 0x0018 773d220cc3SHawking Zhang #define mmIH_VMID_8_LUT_MM_BASE_IDX 0 783d220cc3SHawking Zhang #define mmIH_VMID_9_LUT_MM 0x0019 793d220cc3SHawking Zhang #define mmIH_VMID_9_LUT_MM_BASE_IDX 0 803d220cc3SHawking Zhang #define mmIH_VMID_10_LUT_MM 0x001a 813d220cc3SHawking Zhang #define mmIH_VMID_10_LUT_MM_BASE_IDX 0 823d220cc3SHawking Zhang #define mmIH_VMID_11_LUT_MM 0x001b 833d220cc3SHawking Zhang #define mmIH_VMID_11_LUT_MM_BASE_IDX 0 843d220cc3SHawking Zhang #define mmIH_VMID_12_LUT_MM 0x001c 853d220cc3SHawking Zhang #define mmIH_VMID_12_LUT_MM_BASE_IDX 0 863d220cc3SHawking Zhang #define mmIH_VMID_13_LUT_MM 0x001d 873d220cc3SHawking Zhang #define mmIH_VMID_13_LUT_MM_BASE_IDX 0 883d220cc3SHawking Zhang #define mmIH_VMID_14_LUT_MM 0x001e 893d220cc3SHawking Zhang #define mmIH_VMID_14_LUT_MM_BASE_IDX 0 903d220cc3SHawking Zhang #define mmIH_VMID_15_LUT_MM 0x001f 913d220cc3SHawking Zhang #define mmIH_VMID_15_LUT_MM_BASE_IDX 0 923d220cc3SHawking Zhang #define mmIH_COOKIE_0 0x0020 933d220cc3SHawking Zhang #define mmIH_COOKIE_0_BASE_IDX 0 943d220cc3SHawking Zhang #define mmIH_COOKIE_1 0x0021 953d220cc3SHawking Zhang #define mmIH_COOKIE_1_BASE_IDX 0 963d220cc3SHawking Zhang #define mmIH_COOKIE_2 0x0022 973d220cc3SHawking Zhang #define mmIH_COOKIE_2_BASE_IDX 0 983d220cc3SHawking Zhang #define mmIH_COOKIE_3 0x0023 993d220cc3SHawking Zhang #define mmIH_COOKIE_3_BASE_IDX 0 1003d220cc3SHawking Zhang #define mmIH_COOKIE_4 0x0024 1013d220cc3SHawking Zhang #define mmIH_COOKIE_4_BASE_IDX 0 1023d220cc3SHawking Zhang #define mmIH_COOKIE_5 0x0025 1033d220cc3SHawking Zhang #define mmIH_COOKIE_5_BASE_IDX 0 1043d220cc3SHawking Zhang #define mmIH_COOKIE_6 0x0026 1053d220cc3SHawking Zhang #define mmIH_COOKIE_6_BASE_IDX 0 1063d220cc3SHawking Zhang #define mmIH_COOKIE_7 0x0027 1073d220cc3SHawking Zhang #define mmIH_COOKIE_7_BASE_IDX 0 1083d220cc3SHawking Zhang #define mmIH_REGISTER_LAST_PART0 0x003f 1093d220cc3SHawking Zhang #define mmIH_REGISTER_LAST_PART0_BASE_IDX 0 1103d220cc3SHawking Zhang #define mmSEM_REQ_INPUT_0 0x0040 1113d220cc3SHawking Zhang #define mmSEM_REQ_INPUT_0_BASE_IDX 0 1123d220cc3SHawking Zhang #define mmSEM_REQ_INPUT_1 0x0041 1133d220cc3SHawking Zhang #define mmSEM_REQ_INPUT_1_BASE_IDX 0 1143d220cc3SHawking Zhang #define mmSEM_REQ_INPUT_2 0x0042 1153d220cc3SHawking Zhang #define mmSEM_REQ_INPUT_2_BASE_IDX 0 1163d220cc3SHawking Zhang #define mmSEM_REQ_INPUT_3 0x0043 1173d220cc3SHawking Zhang #define mmSEM_REQ_INPUT_3_BASE_IDX 0 1183d220cc3SHawking Zhang #define mmSEM_REGISTER_LAST_PART0 0x007f 1193d220cc3SHawking Zhang #define mmSEM_REGISTER_LAST_PART0_BASE_IDX 0 1203d220cc3SHawking Zhang #define mmIH_RB_CNTL 0x0080 1213d220cc3SHawking Zhang #define mmIH_RB_CNTL_BASE_IDX 0 1223d220cc3SHawking Zhang #define mmIH_RB_BASE 0x0081 1233d220cc3SHawking Zhang #define mmIH_RB_BASE_BASE_IDX 0 1243d220cc3SHawking Zhang #define mmIH_RB_BASE_HI 0x0082 1253d220cc3SHawking Zhang #define mmIH_RB_BASE_HI_BASE_IDX 0 1263d220cc3SHawking Zhang #define mmIH_RB_RPTR 0x0083 1273d220cc3SHawking Zhang #define mmIH_RB_RPTR_BASE_IDX 0 1283d220cc3SHawking Zhang #define mmIH_RB_WPTR 0x0084 1293d220cc3SHawking Zhang #define mmIH_RB_WPTR_BASE_IDX 0 1303d220cc3SHawking Zhang #define mmIH_RB_WPTR_ADDR_HI 0x0085 1313d220cc3SHawking Zhang #define mmIH_RB_WPTR_ADDR_HI_BASE_IDX 0 1323d220cc3SHawking Zhang #define mmIH_RB_WPTR_ADDR_LO 0x0086 1333d220cc3SHawking Zhang #define mmIH_RB_WPTR_ADDR_LO_BASE_IDX 0 1343d220cc3SHawking Zhang #define mmIH_DOORBELL_RPTR 0x0087 1353d220cc3SHawking Zhang #define mmIH_DOORBELL_RPTR_BASE_IDX 0 1363d220cc3SHawking Zhang #define mmIH_RB_CNTL_RING1 0x008c 1373d220cc3SHawking Zhang #define mmIH_RB_CNTL_RING1_BASE_IDX 0 1383d220cc3SHawking Zhang #define mmIH_RB_BASE_RING1 0x008d 1393d220cc3SHawking Zhang #define mmIH_RB_BASE_RING1_BASE_IDX 0 1403d220cc3SHawking Zhang #define mmIH_RB_BASE_HI_RING1 0x008e 1413d220cc3SHawking Zhang #define mmIH_RB_BASE_HI_RING1_BASE_IDX 0 1423d220cc3SHawking Zhang #define mmIH_RB_RPTR_RING1 0x008f 1433d220cc3SHawking Zhang #define mmIH_RB_RPTR_RING1_BASE_IDX 0 1443d220cc3SHawking Zhang #define mmIH_RB_WPTR_RING1 0x0090 1453d220cc3SHawking Zhang #define mmIH_RB_WPTR_RING1_BASE_IDX 0 1463d220cc3SHawking Zhang #define mmIH_DOORBELL_RPTR_RING1 0x0093 1473d220cc3SHawking Zhang #define mmIH_DOORBELL_RPTR_RING1_BASE_IDX 0 1483d220cc3SHawking Zhang #define mmIH_RB_CNTL_RING2 0x0098 1493d220cc3SHawking Zhang #define mmIH_RB_CNTL_RING2_BASE_IDX 0 1503d220cc3SHawking Zhang #define mmIH_RB_BASE_RING2 0x0099 1513d220cc3SHawking Zhang #define mmIH_RB_BASE_RING2_BASE_IDX 0 1523d220cc3SHawking Zhang #define mmIH_RB_BASE_HI_RING2 0x009a 1533d220cc3SHawking Zhang #define mmIH_RB_BASE_HI_RING2_BASE_IDX 0 1543d220cc3SHawking Zhang #define mmIH_RB_RPTR_RING2 0x009b 1553d220cc3SHawking Zhang #define mmIH_RB_RPTR_RING2_BASE_IDX 0 1563d220cc3SHawking Zhang #define mmIH_RB_WPTR_RING2 0x009c 1573d220cc3SHawking Zhang #define mmIH_RB_WPTR_RING2_BASE_IDX 0 1583d220cc3SHawking Zhang #define mmIH_DOORBELL_RPTR_RING2 0x009f 1593d220cc3SHawking Zhang #define mmIH_DOORBELL_RPTR_RING2_BASE_IDX 0 1603d220cc3SHawking Zhang #define mmIH_VERSION 0x00a5 1613d220cc3SHawking Zhang #define mmIH_VERSION_BASE_IDX 0 1623d220cc3SHawking Zhang #define mmIH_CNTL 0x00c0 1633d220cc3SHawking Zhang #define mmIH_CNTL_BASE_IDX 0 1643d220cc3SHawking Zhang #define mmIH_CNTL2 0x00c1 1653d220cc3SHawking Zhang #define mmIH_CNTL2_BASE_IDX 0 1663d220cc3SHawking Zhang #define mmIH_STATUS 0x00c2 1673d220cc3SHawking Zhang #define mmIH_STATUS_BASE_IDX 0 1683d220cc3SHawking Zhang #define mmIH_PERFMON_CNTL 0x00c3 1693d220cc3SHawking Zhang #define mmIH_PERFMON_CNTL_BASE_IDX 0 1703d220cc3SHawking Zhang #define mmIH_PERFCOUNTER0_RESULT 0x00c4 1713d220cc3SHawking Zhang #define mmIH_PERFCOUNTER0_RESULT_BASE_IDX 0 1723d220cc3SHawking Zhang #define mmIH_PERFCOUNTER1_RESULT 0x00c5 1733d220cc3SHawking Zhang #define mmIH_PERFCOUNTER1_RESULT_BASE_IDX 0 1743d220cc3SHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7 1753d220cc3SHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0 1763d220cc3SHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8 1773d220cc3SHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0 1783d220cc3SHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9 1793d220cc3SHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0 1803d220cc3SHawking Zhang #define mmIH_DSM_MATCH_FIELD_CONTROL 0x00ca 1813d220cc3SHawking Zhang #define mmIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0 1823d220cc3SHawking Zhang #define mmIH_DSM_MATCH_DATA_CONTROL 0x00cb 1833d220cc3SHawking Zhang #define mmIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0 1843d220cc3SHawking Zhang #define mmIH_DSM_MATCH_FCN_ID 0x00cc 1853d220cc3SHawking Zhang #define mmIH_DSM_MATCH_FCN_ID_BASE_IDX 0 1863d220cc3SHawking Zhang #define mmIH_LIMIT_INT_RATE_CNTL 0x00cd 1873d220cc3SHawking Zhang #define mmIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0 1883d220cc3SHawking Zhang #define mmIH_VF_RB_STATUS 0x00ce 1893d220cc3SHawking Zhang #define mmIH_VF_RB_STATUS_BASE_IDX 0 1903d220cc3SHawking Zhang #define mmIH_VF_RB_STATUS2 0x00cf 1913d220cc3SHawking Zhang #define mmIH_VF_RB_STATUS2_BASE_IDX 0 1923d220cc3SHawking Zhang #define mmIH_VF_RB1_STATUS 0x00d0 1933d220cc3SHawking Zhang #define mmIH_VF_RB1_STATUS_BASE_IDX 0 1943d220cc3SHawking Zhang #define mmIH_VF_RB1_STATUS2 0x00d1 1953d220cc3SHawking Zhang #define mmIH_VF_RB1_STATUS2_BASE_IDX 0 1963d220cc3SHawking Zhang #define mmIH_VF_RB2_STATUS 0x00d2 1973d220cc3SHawking Zhang #define mmIH_VF_RB2_STATUS_BASE_IDX 0 1983d220cc3SHawking Zhang #define mmIH_VF_RB2_STATUS2 0x00d3 1993d220cc3SHawking Zhang #define mmIH_VF_RB2_STATUS2_BASE_IDX 0 2003d220cc3SHawking Zhang #define mmIH_INT_FLOOD_CNTL 0x00d5 2013d220cc3SHawking Zhang #define mmIH_INT_FLOOD_CNTL_BASE_IDX 0 2023d220cc3SHawking Zhang #define mmIH_RB0_INT_FLOOD_STATUS 0x00d6 2033d220cc3SHawking Zhang #define mmIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0 2043d220cc3SHawking Zhang #define mmIH_RB1_INT_FLOOD_STATUS 0x00d7 2053d220cc3SHawking Zhang #define mmIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0 2063d220cc3SHawking Zhang #define mmIH_RB2_INT_FLOOD_STATUS 0x00d8 2073d220cc3SHawking Zhang #define mmIH_RB2_INT_FLOOD_STATUS_BASE_IDX 0 2083d220cc3SHawking Zhang #define mmIH_INT_FLOOD_STATUS 0x00d9 2093d220cc3SHawking Zhang #define mmIH_INT_FLOOD_STATUS_BASE_IDX 0 2103d220cc3SHawking Zhang #define mmIH_STORM_CLIENT_LIST_CNTL 0x00da 2113d220cc3SHawking Zhang #define mmIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0 2123d220cc3SHawking Zhang #define mmIH_CLK_CTRL 0x00db 2133d220cc3SHawking Zhang #define mmIH_CLK_CTRL_BASE_IDX 0 2143d220cc3SHawking Zhang #define mmIH_INT_FLAGS 0x00dc 2153d220cc3SHawking Zhang #define mmIH_INT_FLAGS_BASE_IDX 0 2163d220cc3SHawking Zhang #define mmIH_LAST_INT_INFO0 0x00dd 2173d220cc3SHawking Zhang #define mmIH_LAST_INT_INFO0_BASE_IDX 0 2183d220cc3SHawking Zhang #define mmIH_LAST_INT_INFO1 0x00de 2193d220cc3SHawking Zhang #define mmIH_LAST_INT_INFO1_BASE_IDX 0 2203d220cc3SHawking Zhang #define mmIH_LAST_INT_INFO2 0x00df 2213d220cc3SHawking Zhang #define mmIH_LAST_INT_INFO2_BASE_IDX 0 2223d220cc3SHawking Zhang #define mmIH_SCRATCH 0x00e0 2233d220cc3SHawking Zhang #define mmIH_SCRATCH_BASE_IDX 0 2243d220cc3SHawking Zhang #define mmIH_CLIENT_CREDIT_ERROR 0x00e1 2253d220cc3SHawking Zhang #define mmIH_CLIENT_CREDIT_ERROR_BASE_IDX 0 2263d220cc3SHawking Zhang #define mmIH_GPU_IOV_VIOLATION_LOG 0x00e2 2273d220cc3SHawking Zhang #define mmIH_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 2283d220cc3SHawking Zhang #define mmIH_GPU_IOV_VIOLATION_LOG2 0x00e3 2293d220cc3SHawking Zhang #define mmIH_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0 2303d220cc3SHawking Zhang #define mmIH_COOKIE_REC_VIOLATION_LOG 0x00e4 2313d220cc3SHawking Zhang #define mmIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0 2323d220cc3SHawking Zhang #define mmIH_CREDIT_STATUS 0x00e5 2333d220cc3SHawking Zhang #define mmIH_CREDIT_STATUS_BASE_IDX 0 2343d220cc3SHawking Zhang #define mmIH_MMHUB_ERROR 0x00e6 2353d220cc3SHawking Zhang #define mmIH_MMHUB_ERROR_BASE_IDX 0 2363d220cc3SHawking Zhang #define mmIH_MEM_POWER_CTRL 0x00e9 2373d220cc3SHawking Zhang #define mmIH_MEM_POWER_CTRL_BASE_IDX 0 2383d220cc3SHawking Zhang #define mmIH_VF_RB_STATUS3 0x00ea 2393d220cc3SHawking Zhang #define mmIH_VF_RB_STATUS3_BASE_IDX 0 2403d220cc3SHawking Zhang #define mmIH_VF_RB_STATUS4 0x00eb 2413d220cc3SHawking Zhang #define mmIH_VF_RB_STATUS4_BASE_IDX 0 2423d220cc3SHawking Zhang #define mmIH_VF_RB1_STATUS3 0x00ec 2433d220cc3SHawking Zhang #define mmIH_VF_RB1_STATUS3_BASE_IDX 0 2443d220cc3SHawking Zhang #define mmIH_VF_RB2_STATUS3 0x00ee 2453d220cc3SHawking Zhang #define mmIH_VF_RB2_STATUS3_BASE_IDX 0 2463d220cc3SHawking Zhang #define mmIH_REGISTER_LAST_PART2 0x00ff 2473d220cc3SHawking Zhang #define mmIH_REGISTER_LAST_PART2_BASE_IDX 0 2483d220cc3SHawking Zhang #define mmSEM_CLK_CTRL 0x0100 2493d220cc3SHawking Zhang #define mmSEM_CLK_CTRL_BASE_IDX 0 2503d220cc3SHawking Zhang #define mmSEM_UTC_CREDIT 0x0101 2513d220cc3SHawking Zhang #define mmSEM_UTC_CREDIT_BASE_IDX 0 2523d220cc3SHawking Zhang #define mmSEM_UTC_CONFIG 0x0102 2533d220cc3SHawking Zhang #define mmSEM_UTC_CONFIG_BASE_IDX 0 2543d220cc3SHawking Zhang #define mmSEM_UTCL2_TRAN_EN_LUT 0x0103 2553d220cc3SHawking Zhang #define mmSEM_UTCL2_TRAN_EN_LUT_BASE_IDX 0 2563d220cc3SHawking Zhang #define mmSEM_MCIF_CONFIG 0x0104 2573d220cc3SHawking Zhang #define mmSEM_MCIF_CONFIG_BASE_IDX 0 2583d220cc3SHawking Zhang #define mmSEM_PERFMON_CNTL 0x0105 2593d220cc3SHawking Zhang #define mmSEM_PERFMON_CNTL_BASE_IDX 0 2603d220cc3SHawking Zhang #define mmSEM_PERFCOUNTER0_RESULT 0x0106 2613d220cc3SHawking Zhang #define mmSEM_PERFCOUNTER0_RESULT_BASE_IDX 0 2623d220cc3SHawking Zhang #define mmSEM_PERFCOUNTER1_RESULT 0x0107 2633d220cc3SHawking Zhang #define mmSEM_PERFCOUNTER1_RESULT_BASE_IDX 0 2643d220cc3SHawking Zhang #define mmSEM_STATUS 0x0108 2653d220cc3SHawking Zhang #define mmSEM_STATUS_BASE_IDX 0 2663d220cc3SHawking Zhang #define mmSEM_MAILBOX_CLIENTCONFIG 0x0109 2673d220cc3SHawking Zhang #define mmSEM_MAILBOX_CLIENTCONFIG_BASE_IDX 0 2683d220cc3SHawking Zhang #define mmSEM_MAILBOX 0x010a 2693d220cc3SHawking Zhang #define mmSEM_MAILBOX_BASE_IDX 0 2703d220cc3SHawking Zhang #define mmSEM_MAILBOX_CONTROL 0x010b 2713d220cc3SHawking Zhang #define mmSEM_MAILBOX_CONTROL_BASE_IDX 0 2723d220cc3SHawking Zhang #define mmSEM_CHICKEN_BITS 0x010c 2733d220cc3SHawking Zhang #define mmSEM_CHICKEN_BITS_BASE_IDX 0 2743d220cc3SHawking Zhang #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0x010d 2753d220cc3SHawking Zhang #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_BASE_IDX 0 2763d220cc3SHawking Zhang #define mmSEM_GPU_IOV_VIOLATION_LOG 0x010e 2773d220cc3SHawking Zhang #define mmSEM_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 2783d220cc3SHawking Zhang #define mmSEM_OUTSTANDING_THRESHOLD 0x010f 2793d220cc3SHawking Zhang #define mmSEM_OUTSTANDING_THRESHOLD_BASE_IDX 0 2803d220cc3SHawking Zhang #define mmSEM_MEM_POWER_CTRL 0x0110 2813d220cc3SHawking Zhang #define mmSEM_MEM_POWER_CTRL_BASE_IDX 0 2823d220cc3SHawking Zhang #define mmSEM_GPU_IOV_VIOLATION_LOG2 0x0111 2833d220cc3SHawking Zhang #define mmSEM_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0 2843d220cc3SHawking Zhang #define mmSEM_REGISTER_LAST_PART2 0x017f 2853d220cc3SHawking Zhang #define mmSEM_REGISTER_LAST_PART2_BASE_IDX 0 2863d220cc3SHawking Zhang #define mmIH_ACTIVE_FCN_ID 0x0180 2873d220cc3SHawking Zhang #define mmIH_ACTIVE_FCN_ID_BASE_IDX 0 2883d220cc3SHawking Zhang #define mmIH_VIRT_RESET_REQ 0x0181 2893d220cc3SHawking Zhang #define mmIH_VIRT_RESET_REQ_BASE_IDX 0 2903d220cc3SHawking Zhang #define mmIH_CLIENT_CFG 0x0184 2913d220cc3SHawking Zhang #define mmIH_CLIENT_CFG_BASE_IDX 0 2923d220cc3SHawking Zhang #define mmIH_CLIENT_CFG_INDEX 0x0188 2933d220cc3SHawking Zhang #define mmIH_CLIENT_CFG_INDEX_BASE_IDX 0 2943d220cc3SHawking Zhang #define mmIH_CLIENT_CFG_DATA 0x0189 2953d220cc3SHawking Zhang #define mmIH_CLIENT_CFG_DATA_BASE_IDX 0 2963d220cc3SHawking Zhang #define mmIH_CID_REMAP_INDEX 0x018a 2973d220cc3SHawking Zhang #define mmIH_CID_REMAP_INDEX_BASE_IDX 0 2983d220cc3SHawking Zhang #define mmIH_CID_REMAP_DATA 0x018b 2993d220cc3SHawking Zhang #define mmIH_CID_REMAP_DATA_BASE_IDX 0 3003d220cc3SHawking Zhang #define mmIH_CHICKEN 0x018c 3013d220cc3SHawking Zhang #define mmIH_CHICKEN_BASE_IDX 0 3023d220cc3SHawking Zhang #define mmIH_MMHUB_CNTL 0x018d 3033d220cc3SHawking Zhang #define mmIH_MMHUB_CNTL_BASE_IDX 0 3043d220cc3SHawking Zhang #define mmIH_INT_DROP_CNTL 0x018e 3053d220cc3SHawking Zhang #define mmIH_INT_DROP_CNTL_BASE_IDX 0 3063d220cc3SHawking Zhang #define mmIH_INT_DROP_MATCH_VALUE0 0x018f 3073d220cc3SHawking Zhang #define mmIH_INT_DROP_MATCH_VALUE0_BASE_IDX 0 3083d220cc3SHawking Zhang #define mmIH_INT_DROP_MATCH_VALUE1 0x0190 3093d220cc3SHawking Zhang #define mmIH_INT_DROP_MATCH_VALUE1_BASE_IDX 0 3103d220cc3SHawking Zhang #define mmIH_INT_DROP_MATCH_MASK0 0x0191 3113d220cc3SHawking Zhang #define mmIH_INT_DROP_MATCH_MASK0_BASE_IDX 0 3123d220cc3SHawking Zhang #define mmIH_INT_DROP_MATCH_MASK1 0x0192 3133d220cc3SHawking Zhang #define mmIH_INT_DROP_MATCH_MASK1_BASE_IDX 0 3143d220cc3SHawking Zhang #define mmIH_REGISTER_LAST_PART1 0x019f 3153d220cc3SHawking Zhang #define mmIH_REGISTER_LAST_PART1_BASE_IDX 0 3163d220cc3SHawking Zhang #define mmSEM_ACTIVE_FCN_ID 0x01a0 3173d220cc3SHawking Zhang #define mmSEM_ACTIVE_FCN_ID_BASE_IDX 0 3183d220cc3SHawking Zhang #define mmSEM_VIRT_RESET_REQ 0x01a1 3193d220cc3SHawking Zhang #define mmSEM_VIRT_RESET_REQ_BASE_IDX 0 3203d220cc3SHawking Zhang #define mmSEM_RESP_SDMA0 0x01a4 3213d220cc3SHawking Zhang #define mmSEM_RESP_SDMA0_BASE_IDX 0 3223d220cc3SHawking Zhang #define mmSEM_RESP_SDMA1 0x01a5 3233d220cc3SHawking Zhang #define mmSEM_RESP_SDMA1_BASE_IDX 0 3243d220cc3SHawking Zhang #define mmSEM_RESP_UVD 0x01a6 3253d220cc3SHawking Zhang #define mmSEM_RESP_UVD_BASE_IDX 0 3263d220cc3SHawking Zhang #define mmSEM_RESP_VCE_0 0x01a7 3273d220cc3SHawking Zhang #define mmSEM_RESP_VCE_0_BASE_IDX 0 3283d220cc3SHawking Zhang #define mmSEM_RESP_ACP 0x01a8 3293d220cc3SHawking Zhang #define mmSEM_RESP_ACP_BASE_IDX 0 3303d220cc3SHawking Zhang #define mmSEM_RESP_ISP 0x01a9 3313d220cc3SHawking Zhang #define mmSEM_RESP_ISP_BASE_IDX 0 3323d220cc3SHawking Zhang #define mmSEM_RESP_VCE_1 0x01aa 3333d220cc3SHawking Zhang #define mmSEM_RESP_VCE_1_BASE_IDX 0 3343d220cc3SHawking Zhang #define mmSEM_RESP_VP8 0x01ab 3353d220cc3SHawking Zhang #define mmSEM_RESP_VP8_BASE_IDX 0 3363d220cc3SHawking Zhang #define mmSEM_RESP_GC 0x01ac 3373d220cc3SHawking Zhang #define mmSEM_RESP_GC_BASE_IDX 0 3383d220cc3SHawking Zhang #define mmSEM_CID_REMAP_INDEX 0x01b0 3393d220cc3SHawking Zhang #define mmSEM_CID_REMAP_INDEX_BASE_IDX 0 3403d220cc3SHawking Zhang #define mmSEM_CID_REMAP_DATA 0x01b1 3413d220cc3SHawking Zhang #define mmSEM_CID_REMAP_DATA_BASE_IDX 0 3423d220cc3SHawking Zhang #define mmSEM_ATOMIC_OP_LUT 0x01b2 3433d220cc3SHawking Zhang #define mmSEM_ATOMIC_OP_LUT_BASE_IDX 0 3443d220cc3SHawking Zhang #define mmSEM_EDC_CONFIG 0x01b3 3453d220cc3SHawking Zhang #define mmSEM_EDC_CONFIG_BASE_IDX 0 3463d220cc3SHawking Zhang #define mmSEM_CHICKEN_BITS2 0x01b4 3473d220cc3SHawking Zhang #define mmSEM_CHICKEN_BITS2_BASE_IDX 0 3483d220cc3SHawking Zhang #define mmSEM_MMHUB_CNTL 0x01b5 3493d220cc3SHawking Zhang #define mmSEM_MMHUB_CNTL_BASE_IDX 0 3503d220cc3SHawking Zhang #define mmSEM_REGISTER_LAST_PART1 0x01bf 3513d220cc3SHawking Zhang #define mmSEM_REGISTER_LAST_PART1_BASE_IDX 0 3523d220cc3SHawking Zhang 3533d220cc3SHawking Zhang #endif 354