18af7454eSFeifei Xu /* 28af7454eSFeifei Xu * Copyright (C) 2017 Advanced Micro Devices, Inc. 38af7454eSFeifei Xu * 48af7454eSFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 58af7454eSFeifei Xu * copy of this software and associated documentation files (the "Software"), 68af7454eSFeifei Xu * to deal in the Software without restriction, including without limitation 78af7454eSFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 88af7454eSFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 98af7454eSFeifei Xu * Software is furnished to do so, subject to the following conditions: 108af7454eSFeifei Xu * 118af7454eSFeifei Xu * The above copyright notice and this permission notice shall be included 128af7454eSFeifei Xu * in all copies or substantial portions of the Software. 138af7454eSFeifei Xu * 148af7454eSFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 158af7454eSFeifei Xu * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 168af7454eSFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 178af7454eSFeifei Xu * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 188af7454eSFeifei Xu * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 198af7454eSFeifei Xu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 208af7454eSFeifei Xu */ 218af7454eSFeifei Xu #ifndef _osssys_4_0_OFFSET_HEADER 228af7454eSFeifei Xu #define _osssys_4_0_OFFSET_HEADER 238af7454eSFeifei Xu 248af7454eSFeifei Xu 258af7454eSFeifei Xu 268af7454eSFeifei Xu // addressBlock: osssys_osssysdec 278af7454eSFeifei Xu // base address: 0x4280 288af7454eSFeifei Xu #define mmIH_VMID_0_LUT 0x0000 298af7454eSFeifei Xu #define mmIH_VMID_0_LUT_BASE_IDX 0 308af7454eSFeifei Xu #define mmIH_VMID_1_LUT 0x0001 318af7454eSFeifei Xu #define mmIH_VMID_1_LUT_BASE_IDX 0 328af7454eSFeifei Xu #define mmIH_VMID_2_LUT 0x0002 338af7454eSFeifei Xu #define mmIH_VMID_2_LUT_BASE_IDX 0 348af7454eSFeifei Xu #define mmIH_VMID_3_LUT 0x0003 358af7454eSFeifei Xu #define mmIH_VMID_3_LUT_BASE_IDX 0 368af7454eSFeifei Xu #define mmIH_VMID_4_LUT 0x0004 378af7454eSFeifei Xu #define mmIH_VMID_4_LUT_BASE_IDX 0 388af7454eSFeifei Xu #define mmIH_VMID_5_LUT 0x0005 398af7454eSFeifei Xu #define mmIH_VMID_5_LUT_BASE_IDX 0 408af7454eSFeifei Xu #define mmIH_VMID_6_LUT 0x0006 418af7454eSFeifei Xu #define mmIH_VMID_6_LUT_BASE_IDX 0 428af7454eSFeifei Xu #define mmIH_VMID_7_LUT 0x0007 438af7454eSFeifei Xu #define mmIH_VMID_7_LUT_BASE_IDX 0 448af7454eSFeifei Xu #define mmIH_VMID_8_LUT 0x0008 458af7454eSFeifei Xu #define mmIH_VMID_8_LUT_BASE_IDX 0 468af7454eSFeifei Xu #define mmIH_VMID_9_LUT 0x0009 478af7454eSFeifei Xu #define mmIH_VMID_9_LUT_BASE_IDX 0 488af7454eSFeifei Xu #define mmIH_VMID_10_LUT 0x000a 498af7454eSFeifei Xu #define mmIH_VMID_10_LUT_BASE_IDX 0 508af7454eSFeifei Xu #define mmIH_VMID_11_LUT 0x000b 518af7454eSFeifei Xu #define mmIH_VMID_11_LUT_BASE_IDX 0 528af7454eSFeifei Xu #define mmIH_VMID_12_LUT 0x000c 538af7454eSFeifei Xu #define mmIH_VMID_12_LUT_BASE_IDX 0 548af7454eSFeifei Xu #define mmIH_VMID_13_LUT 0x000d 558af7454eSFeifei Xu #define mmIH_VMID_13_LUT_BASE_IDX 0 568af7454eSFeifei Xu #define mmIH_VMID_14_LUT 0x000e 578af7454eSFeifei Xu #define mmIH_VMID_14_LUT_BASE_IDX 0 588af7454eSFeifei Xu #define mmIH_VMID_15_LUT 0x000f 598af7454eSFeifei Xu #define mmIH_VMID_15_LUT_BASE_IDX 0 608af7454eSFeifei Xu #define mmIH_VMID_0_LUT_MM 0x0010 618af7454eSFeifei Xu #define mmIH_VMID_0_LUT_MM_BASE_IDX 0 628af7454eSFeifei Xu #define mmIH_VMID_1_LUT_MM 0x0011 638af7454eSFeifei Xu #define mmIH_VMID_1_LUT_MM_BASE_IDX 0 648af7454eSFeifei Xu #define mmIH_VMID_2_LUT_MM 0x0012 658af7454eSFeifei Xu #define mmIH_VMID_2_LUT_MM_BASE_IDX 0 668af7454eSFeifei Xu #define mmIH_VMID_3_LUT_MM 0x0013 678af7454eSFeifei Xu #define mmIH_VMID_3_LUT_MM_BASE_IDX 0 688af7454eSFeifei Xu #define mmIH_VMID_4_LUT_MM 0x0014 698af7454eSFeifei Xu #define mmIH_VMID_4_LUT_MM_BASE_IDX 0 708af7454eSFeifei Xu #define mmIH_VMID_5_LUT_MM 0x0015 718af7454eSFeifei Xu #define mmIH_VMID_5_LUT_MM_BASE_IDX 0 728af7454eSFeifei Xu #define mmIH_VMID_6_LUT_MM 0x0016 738af7454eSFeifei Xu #define mmIH_VMID_6_LUT_MM_BASE_IDX 0 748af7454eSFeifei Xu #define mmIH_VMID_7_LUT_MM 0x0017 758af7454eSFeifei Xu #define mmIH_VMID_7_LUT_MM_BASE_IDX 0 768af7454eSFeifei Xu #define mmIH_VMID_8_LUT_MM 0x0018 778af7454eSFeifei Xu #define mmIH_VMID_8_LUT_MM_BASE_IDX 0 788af7454eSFeifei Xu #define mmIH_VMID_9_LUT_MM 0x0019 798af7454eSFeifei Xu #define mmIH_VMID_9_LUT_MM_BASE_IDX 0 808af7454eSFeifei Xu #define mmIH_VMID_10_LUT_MM 0x001a 818af7454eSFeifei Xu #define mmIH_VMID_10_LUT_MM_BASE_IDX 0 828af7454eSFeifei Xu #define mmIH_VMID_11_LUT_MM 0x001b 838af7454eSFeifei Xu #define mmIH_VMID_11_LUT_MM_BASE_IDX 0 848af7454eSFeifei Xu #define mmIH_VMID_12_LUT_MM 0x001c 858af7454eSFeifei Xu #define mmIH_VMID_12_LUT_MM_BASE_IDX 0 868af7454eSFeifei Xu #define mmIH_VMID_13_LUT_MM 0x001d 878af7454eSFeifei Xu #define mmIH_VMID_13_LUT_MM_BASE_IDX 0 888af7454eSFeifei Xu #define mmIH_VMID_14_LUT_MM 0x001e 898af7454eSFeifei Xu #define mmIH_VMID_14_LUT_MM_BASE_IDX 0 908af7454eSFeifei Xu #define mmIH_VMID_15_LUT_MM 0x001f 918af7454eSFeifei Xu #define mmIH_VMID_15_LUT_MM_BASE_IDX 0 928af7454eSFeifei Xu #define mmIH_COOKIE_0 0x0020 938af7454eSFeifei Xu #define mmIH_COOKIE_0_BASE_IDX 0 948af7454eSFeifei Xu #define mmIH_COOKIE_1 0x0021 958af7454eSFeifei Xu #define mmIH_COOKIE_1_BASE_IDX 0 968af7454eSFeifei Xu #define mmIH_COOKIE_2 0x0022 978af7454eSFeifei Xu #define mmIH_COOKIE_2_BASE_IDX 0 988af7454eSFeifei Xu #define mmIH_COOKIE_3 0x0023 998af7454eSFeifei Xu #define mmIH_COOKIE_3_BASE_IDX 0 1008af7454eSFeifei Xu #define mmIH_COOKIE_4 0x0024 1018af7454eSFeifei Xu #define mmIH_COOKIE_4_BASE_IDX 0 1028af7454eSFeifei Xu #define mmIH_COOKIE_5 0x0025 1038af7454eSFeifei Xu #define mmIH_COOKIE_5_BASE_IDX 0 1048af7454eSFeifei Xu #define mmIH_COOKIE_6 0x0026 1058af7454eSFeifei Xu #define mmIH_COOKIE_6_BASE_IDX 0 1068af7454eSFeifei Xu #define mmIH_COOKIE_7 0x0027 1078af7454eSFeifei Xu #define mmIH_COOKIE_7_BASE_IDX 0 1088af7454eSFeifei Xu #define mmIH_REGISTER_LAST_PART0 0x003f 1098af7454eSFeifei Xu #define mmIH_REGISTER_LAST_PART0_BASE_IDX 0 1108af7454eSFeifei Xu #define mmSEM_REQ_INPUT_0 0x0040 1118af7454eSFeifei Xu #define mmSEM_REQ_INPUT_0_BASE_IDX 0 1128af7454eSFeifei Xu #define mmSEM_REQ_INPUT_1 0x0041 1138af7454eSFeifei Xu #define mmSEM_REQ_INPUT_1_BASE_IDX 0 1148af7454eSFeifei Xu #define mmSEM_REQ_INPUT_2 0x0042 1158af7454eSFeifei Xu #define mmSEM_REQ_INPUT_2_BASE_IDX 0 1168af7454eSFeifei Xu #define mmSEM_REQ_INPUT_3 0x0043 1178af7454eSFeifei Xu #define mmSEM_REQ_INPUT_3_BASE_IDX 0 1188af7454eSFeifei Xu #define mmSEM_REGISTER_LAST_PART0 0x007f 1198af7454eSFeifei Xu #define mmSEM_REGISTER_LAST_PART0_BASE_IDX 0 1208af7454eSFeifei Xu #define mmIH_RB_CNTL 0x0080 1218af7454eSFeifei Xu #define mmIH_RB_CNTL_BASE_IDX 0 1228af7454eSFeifei Xu #define mmIH_RB_BASE 0x0081 1238af7454eSFeifei Xu #define mmIH_RB_BASE_BASE_IDX 0 1248af7454eSFeifei Xu #define mmIH_RB_BASE_HI 0x0082 1258af7454eSFeifei Xu #define mmIH_RB_BASE_HI_BASE_IDX 0 1268af7454eSFeifei Xu #define mmIH_RB_RPTR 0x0083 1278af7454eSFeifei Xu #define mmIH_RB_RPTR_BASE_IDX 0 1288af7454eSFeifei Xu #define mmIH_RB_WPTR 0x0084 1298af7454eSFeifei Xu #define mmIH_RB_WPTR_BASE_IDX 0 1308af7454eSFeifei Xu #define mmIH_RB_WPTR_ADDR_HI 0x0085 1318af7454eSFeifei Xu #define mmIH_RB_WPTR_ADDR_HI_BASE_IDX 0 1328af7454eSFeifei Xu #define mmIH_RB_WPTR_ADDR_LO 0x0086 1338af7454eSFeifei Xu #define mmIH_RB_WPTR_ADDR_LO_BASE_IDX 0 1348af7454eSFeifei Xu #define mmIH_DOORBELL_RPTR 0x0087 1358af7454eSFeifei Xu #define mmIH_DOORBELL_RPTR_BASE_IDX 0 1368af7454eSFeifei Xu #define mmIH_RB_CNTL_RING1 0x0088 1378af7454eSFeifei Xu #define mmIH_RB_CNTL_RING1_BASE_IDX 0 1388af7454eSFeifei Xu #define mmIH_RB_BASE_RING1 0x0089 1398af7454eSFeifei Xu #define mmIH_RB_BASE_RING1_BASE_IDX 0 1408af7454eSFeifei Xu #define mmIH_RB_BASE_HI_RING1 0x008a 1418af7454eSFeifei Xu #define mmIH_RB_BASE_HI_RING1_BASE_IDX 0 1428af7454eSFeifei Xu #define mmIH_RB_RPTR_RING1 0x008b 1438af7454eSFeifei Xu #define mmIH_RB_RPTR_RING1_BASE_IDX 0 1448af7454eSFeifei Xu #define mmIH_RB_WPTR_RING1 0x008c 1458af7454eSFeifei Xu #define mmIH_RB_WPTR_RING1_BASE_IDX 0 1468af7454eSFeifei Xu #define mmIH_DOORBELL_RPTR_RING1 0x008f 1478af7454eSFeifei Xu #define mmIH_DOORBELL_RPTR_RING1_BASE_IDX 0 1488af7454eSFeifei Xu #define mmIH_RB_CNTL_RING2 0x0090 1498af7454eSFeifei Xu #define mmIH_RB_CNTL_RING2_BASE_IDX 0 1508af7454eSFeifei Xu #define mmIH_RB_BASE_RING2 0x0091 1518af7454eSFeifei Xu #define mmIH_RB_BASE_RING2_BASE_IDX 0 1528af7454eSFeifei Xu #define mmIH_RB_BASE_HI_RING2 0x0092 1538af7454eSFeifei Xu #define mmIH_RB_BASE_HI_RING2_BASE_IDX 0 1548af7454eSFeifei Xu #define mmIH_RB_RPTR_RING2 0x0093 1558af7454eSFeifei Xu #define mmIH_RB_RPTR_RING2_BASE_IDX 0 1568af7454eSFeifei Xu #define mmIH_RB_WPTR_RING2 0x0094 1578af7454eSFeifei Xu #define mmIH_RB_WPTR_RING2_BASE_IDX 0 1588af7454eSFeifei Xu #define mmIH_DOORBELL_RPTR_RING2 0x0097 1598af7454eSFeifei Xu #define mmIH_DOORBELL_RPTR_RING2_BASE_IDX 0 1608af7454eSFeifei Xu #define mmIH_VERSION 0x0098 1618af7454eSFeifei Xu #define mmIH_VERSION_BASE_IDX 0 1628af7454eSFeifei Xu #define mmIH_CNTL 0x00c0 1638af7454eSFeifei Xu #define mmIH_CNTL_BASE_IDX 0 1648af7454eSFeifei Xu #define mmIH_CNTL2 0x00c1 1658af7454eSFeifei Xu #define mmIH_CNTL2_BASE_IDX 0 1668af7454eSFeifei Xu #define mmIH_STATUS 0x00c2 1678af7454eSFeifei Xu #define mmIH_STATUS_BASE_IDX 0 1688af7454eSFeifei Xu #define mmIH_PERFMON_CNTL 0x00c3 1698af7454eSFeifei Xu #define mmIH_PERFMON_CNTL_BASE_IDX 0 1708af7454eSFeifei Xu #define mmIH_PERFCOUNTER0_RESULT 0x00c4 1718af7454eSFeifei Xu #define mmIH_PERFCOUNTER0_RESULT_BASE_IDX 0 1728af7454eSFeifei Xu #define mmIH_PERFCOUNTER1_RESULT 0x00c5 1738af7454eSFeifei Xu #define mmIH_PERFCOUNTER1_RESULT_BASE_IDX 0 1748af7454eSFeifei Xu #define mmIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7 1758af7454eSFeifei Xu #define mmIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0 1768af7454eSFeifei Xu #define mmIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8 1778af7454eSFeifei Xu #define mmIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0 1788af7454eSFeifei Xu #define mmIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9 1798af7454eSFeifei Xu #define mmIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0 1808af7454eSFeifei Xu #define mmIH_DSM_MATCH_FIELD_CONTROL 0x00ca 1818af7454eSFeifei Xu #define mmIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0 1828af7454eSFeifei Xu #define mmIH_DSM_MATCH_DATA_CONTROL 0x00cb 1838af7454eSFeifei Xu #define mmIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0 1848af7454eSFeifei Xu #define mmIH_DSM_MATCH_FCN_ID 0x00cc 1858af7454eSFeifei Xu #define mmIH_DSM_MATCH_FCN_ID_BASE_IDX 0 1868af7454eSFeifei Xu #define mmIH_LIMIT_INT_RATE_CNTL 0x00cd 1878af7454eSFeifei Xu #define mmIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0 1888af7454eSFeifei Xu #define mmIH_VF_RB_STATUS 0x00ce 1898af7454eSFeifei Xu #define mmIH_VF_RB_STATUS_BASE_IDX 0 1908af7454eSFeifei Xu #define mmIH_VF_RB_STATUS2 0x00cf 1918af7454eSFeifei Xu #define mmIH_VF_RB_STATUS2_BASE_IDX 0 1928af7454eSFeifei Xu #define mmIH_VF_RB1_STATUS 0x00d0 1938af7454eSFeifei Xu #define mmIH_VF_RB1_STATUS_BASE_IDX 0 1948af7454eSFeifei Xu #define mmIH_VF_RB1_STATUS2 0x00d1 1958af7454eSFeifei Xu #define mmIH_VF_RB1_STATUS2_BASE_IDX 0 1968af7454eSFeifei Xu #define mmIH_VF_RB2_STATUS 0x00d2 1978af7454eSFeifei Xu #define mmIH_VF_RB2_STATUS_BASE_IDX 0 1988af7454eSFeifei Xu #define mmIH_VF_RB2_STATUS2 0x00d3 1998af7454eSFeifei Xu #define mmIH_VF_RB2_STATUS2_BASE_IDX 0 2008af7454eSFeifei Xu #define mmIH_INT_FLOOD_CNTL 0x00d5 2018af7454eSFeifei Xu #define mmIH_INT_FLOOD_CNTL_BASE_IDX 0 2028af7454eSFeifei Xu #define mmIH_RB0_INT_FLOOD_STATUS 0x00d6 2038af7454eSFeifei Xu #define mmIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0 2048af7454eSFeifei Xu #define mmIH_RB1_INT_FLOOD_STATUS 0x00d7 2058af7454eSFeifei Xu #define mmIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0 2068af7454eSFeifei Xu #define mmIH_RB2_INT_FLOOD_STATUS 0x00d8 2078af7454eSFeifei Xu #define mmIH_RB2_INT_FLOOD_STATUS_BASE_IDX 0 2088af7454eSFeifei Xu #define mmIH_INT_FLOOD_STATUS 0x00d9 2098af7454eSFeifei Xu #define mmIH_INT_FLOOD_STATUS_BASE_IDX 0 2108af7454eSFeifei Xu #define mmIH_STORM_CLIENT_LIST_CNTL 0x00da 2118af7454eSFeifei Xu #define mmIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0 2128af7454eSFeifei Xu #define mmIH_CLK_CTRL 0x00db 2138af7454eSFeifei Xu #define mmIH_CLK_CTRL_BASE_IDX 0 2148af7454eSFeifei Xu #define mmIH_INT_FLAGS 0x00dc 2158af7454eSFeifei Xu #define mmIH_INT_FLAGS_BASE_IDX 0 2168af7454eSFeifei Xu #define mmIH_LAST_INT_INFO0 0x00dd 2178af7454eSFeifei Xu #define mmIH_LAST_INT_INFO0_BASE_IDX 0 2188af7454eSFeifei Xu #define mmIH_LAST_INT_INFO1 0x00de 2198af7454eSFeifei Xu #define mmIH_LAST_INT_INFO1_BASE_IDX 0 2208af7454eSFeifei Xu #define mmIH_LAST_INT_INFO2 0x00df 2218af7454eSFeifei Xu #define mmIH_LAST_INT_INFO2_BASE_IDX 0 2228af7454eSFeifei Xu #define mmIH_SCRATCH 0x00e0 2238af7454eSFeifei Xu #define mmIH_SCRATCH_BASE_IDX 0 2248af7454eSFeifei Xu #define mmIH_CLIENT_CREDIT_ERROR 0x00e1 2258af7454eSFeifei Xu #define mmIH_CLIENT_CREDIT_ERROR_BASE_IDX 0 2268af7454eSFeifei Xu #define mmIH_GPU_IOV_VIOLATION_LOG 0x00e2 2278af7454eSFeifei Xu #define mmIH_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 2288af7454eSFeifei Xu #define mmIH_COOKIE_REC_VIOLATION_LOG 0x00e3 2298af7454eSFeifei Xu #define mmIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0 2308af7454eSFeifei Xu #define mmIH_CREDIT_STATUS 0x00e4 2318af7454eSFeifei Xu #define mmIH_CREDIT_STATUS_BASE_IDX 0 2328af7454eSFeifei Xu #define mmIH_MMHUB_ERROR 0x00e5 2338af7454eSFeifei Xu #define mmIH_MMHUB_ERROR_BASE_IDX 0 2348af7454eSFeifei Xu #define mmIH_REGISTER_LAST_PART2 0x00ff 2358af7454eSFeifei Xu #define mmIH_REGISTER_LAST_PART2_BASE_IDX 0 2368af7454eSFeifei Xu #define mmSEM_CLK_CTRL 0x0100 2378af7454eSFeifei Xu #define mmSEM_CLK_CTRL_BASE_IDX 0 2388af7454eSFeifei Xu #define mmSEM_UTC_CREDIT 0x0101 2398af7454eSFeifei Xu #define mmSEM_UTC_CREDIT_BASE_IDX 0 2408af7454eSFeifei Xu #define mmSEM_UTC_CONFIG 0x0102 2418af7454eSFeifei Xu #define mmSEM_UTC_CONFIG_BASE_IDX 0 2428af7454eSFeifei Xu #define mmSEM_UTCL2_TRAN_EN_LUT 0x0103 2438af7454eSFeifei Xu #define mmSEM_UTCL2_TRAN_EN_LUT_BASE_IDX 0 2448af7454eSFeifei Xu #define mmSEM_MCIF_CONFIG 0x0104 2458af7454eSFeifei Xu #define mmSEM_MCIF_CONFIG_BASE_IDX 0 2468af7454eSFeifei Xu #define mmSEM_PERFMON_CNTL 0x0105 2478af7454eSFeifei Xu #define mmSEM_PERFMON_CNTL_BASE_IDX 0 2488af7454eSFeifei Xu #define mmSEM_PERFCOUNTER0_RESULT 0x0106 2498af7454eSFeifei Xu #define mmSEM_PERFCOUNTER0_RESULT_BASE_IDX 0 2508af7454eSFeifei Xu #define mmSEM_PERFCOUNTER1_RESULT 0x0107 2518af7454eSFeifei Xu #define mmSEM_PERFCOUNTER1_RESULT_BASE_IDX 0 2528af7454eSFeifei Xu #define mmSEM_STATUS 0x0108 2538af7454eSFeifei Xu #define mmSEM_STATUS_BASE_IDX 0 2548af7454eSFeifei Xu #define mmSEM_MAILBOX_CLIENTCONFIG 0x0109 2558af7454eSFeifei Xu #define mmSEM_MAILBOX_CLIENTCONFIG_BASE_IDX 0 2568af7454eSFeifei Xu #define mmSEM_MAILBOX 0x010a 2578af7454eSFeifei Xu #define mmSEM_MAILBOX_BASE_IDX 0 2588af7454eSFeifei Xu #define mmSEM_MAILBOX_CONTROL 0x010b 2598af7454eSFeifei Xu #define mmSEM_MAILBOX_CONTROL_BASE_IDX 0 2608af7454eSFeifei Xu #define mmSEM_CHICKEN_BITS 0x010c 2618af7454eSFeifei Xu #define mmSEM_CHICKEN_BITS_BASE_IDX 0 2628af7454eSFeifei Xu #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0x010d 2638af7454eSFeifei Xu #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_BASE_IDX 0 2648af7454eSFeifei Xu #define mmSEM_GPU_IOV_VIOLATION_LOG 0x010e 2658af7454eSFeifei Xu #define mmSEM_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 2668af7454eSFeifei Xu #define mmSEM_OUTSTANDING_THRESHOLD 0x010f 2678af7454eSFeifei Xu #define mmSEM_OUTSTANDING_THRESHOLD_BASE_IDX 0 2688af7454eSFeifei Xu #define mmSEM_REGISTER_LAST_PART2 0x017f 2698af7454eSFeifei Xu #define mmSEM_REGISTER_LAST_PART2_BASE_IDX 0 2708af7454eSFeifei Xu #define mmIH_ACTIVE_FCN_ID 0x0180 2718af7454eSFeifei Xu #define mmIH_ACTIVE_FCN_ID_BASE_IDX 0 2728af7454eSFeifei Xu #define mmIH_VIRT_RESET_REQ 0x0181 2738af7454eSFeifei Xu #define mmIH_VIRT_RESET_REQ_BASE_IDX 0 2748af7454eSFeifei Xu #define mmIH_CLIENT_CFG 0x0184 2758af7454eSFeifei Xu #define mmIH_CLIENT_CFG_BASE_IDX 0 2768af7454eSFeifei Xu #define mmIH_CLIENT_CFG_INDEX 0x0188 2778af7454eSFeifei Xu #define mmIH_CLIENT_CFG_INDEX_BASE_IDX 0 2788af7454eSFeifei Xu #define mmIH_CLIENT_CFG_DATA 0x0189 2798af7454eSFeifei Xu #define mmIH_CLIENT_CFG_DATA_BASE_IDX 0 2808af7454eSFeifei Xu #define mmIH_CID_REMAP_INDEX 0x018a 2818af7454eSFeifei Xu #define mmIH_CID_REMAP_INDEX_BASE_IDX 0 2828af7454eSFeifei Xu #define mmIH_CID_REMAP_DATA 0x018b 2838af7454eSFeifei Xu #define mmIH_CID_REMAP_DATA_BASE_IDX 0 2848af7454eSFeifei Xu #define mmIH_CHICKEN 0x018c 2858af7454eSFeifei Xu #define mmIH_CHICKEN_BASE_IDX 0 2868af7454eSFeifei Xu #define mmIH_MMHUB_CNTL 0x018d 2878af7454eSFeifei Xu #define mmIH_MMHUB_CNTL_BASE_IDX 0 2888af7454eSFeifei Xu #define mmIH_REGISTER_LAST_PART1 0x019f 2898af7454eSFeifei Xu #define mmIH_REGISTER_LAST_PART1_BASE_IDX 0 2908af7454eSFeifei Xu #define mmSEM_ACTIVE_FCN_ID 0x01a0 2918af7454eSFeifei Xu #define mmSEM_ACTIVE_FCN_ID_BASE_IDX 0 2928af7454eSFeifei Xu #define mmSEM_VIRT_RESET_REQ 0x01a1 2938af7454eSFeifei Xu #define mmSEM_VIRT_RESET_REQ_BASE_IDX 0 2948af7454eSFeifei Xu #define mmSEM_RESP_SDMA0 0x01a4 2958af7454eSFeifei Xu #define mmSEM_RESP_SDMA0_BASE_IDX 0 2968af7454eSFeifei Xu #define mmSEM_RESP_SDMA1 0x01a5 2978af7454eSFeifei Xu #define mmSEM_RESP_SDMA1_BASE_IDX 0 2988af7454eSFeifei Xu #define mmSEM_RESP_UVD 0x01a6 2998af7454eSFeifei Xu #define mmSEM_RESP_UVD_BASE_IDX 0 3008af7454eSFeifei Xu #define mmSEM_RESP_VCE_0 0x01a7 3018af7454eSFeifei Xu #define mmSEM_RESP_VCE_0_BASE_IDX 0 3028af7454eSFeifei Xu #define mmSEM_RESP_ACP 0x01a8 3038af7454eSFeifei Xu #define mmSEM_RESP_ACP_BASE_IDX 0 3048af7454eSFeifei Xu #define mmSEM_RESP_ISP 0x01a9 3058af7454eSFeifei Xu #define mmSEM_RESP_ISP_BASE_IDX 0 3068af7454eSFeifei Xu #define mmSEM_RESP_VCE_1 0x01aa 3078af7454eSFeifei Xu #define mmSEM_RESP_VCE_1_BASE_IDX 0 3088af7454eSFeifei Xu #define mmSEM_RESP_VP8 0x01ab 3098af7454eSFeifei Xu #define mmSEM_RESP_VP8_BASE_IDX 0 3108af7454eSFeifei Xu #define mmSEM_RESP_GC 0x01ac 3118af7454eSFeifei Xu #define mmSEM_RESP_GC_BASE_IDX 0 3128af7454eSFeifei Xu #define mmSEM_CID_REMAP_INDEX 0x01b0 3138af7454eSFeifei Xu #define mmSEM_CID_REMAP_INDEX_BASE_IDX 0 3148af7454eSFeifei Xu #define mmSEM_CID_REMAP_DATA 0x01b1 3158af7454eSFeifei Xu #define mmSEM_CID_REMAP_DATA_BASE_IDX 0 3168af7454eSFeifei Xu #define mmSEM_ATOMIC_OP_LUT 0x01b2 3178af7454eSFeifei Xu #define mmSEM_ATOMIC_OP_LUT_BASE_IDX 0 3188af7454eSFeifei Xu #define mmSEM_EDC_CONFIG 0x01b3 3198af7454eSFeifei Xu #define mmSEM_EDC_CONFIG_BASE_IDX 0 3208af7454eSFeifei Xu #define mmSEM_CHICKEN_BITS2 0x01b4 3218af7454eSFeifei Xu #define mmSEM_CHICKEN_BITS2_BASE_IDX 0 3228af7454eSFeifei Xu #define mmSEM_MMHUB_CNTL 0x01b5 3238af7454eSFeifei Xu #define mmSEM_MMHUB_CNTL_BASE_IDX 0 3248af7454eSFeifei Xu #define mmSEM_REGISTER_LAST_PART1 0x01bf 3258af7454eSFeifei Xu #define mmSEM_REGISTER_LAST_PART1_BASE_IDX 0 3268af7454eSFeifei Xu 3278af7454eSFeifei Xu #endif 328