1502173acSHawking Zhang /* 2502173acSHawking Zhang * Copyright 2020 Advanced Micro Devices, Inc. 3502173acSHawking Zhang * 4502173acSHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5502173acSHawking Zhang * copy of this software and associated documentation files (the "Software"), 6502173acSHawking Zhang * to deal in the Software without restriction, including without limitation 7502173acSHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8502173acSHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9502173acSHawking Zhang * Software is furnished to do so, subject to the following conditions: 10502173acSHawking Zhang * 11502173acSHawking Zhang * The above copyright notice and this permission notice shall be included in 12502173acSHawking Zhang * all copies or substantial portions of the Software. 13502173acSHawking Zhang * 14502173acSHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15502173acSHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16502173acSHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17502173acSHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18502173acSHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19502173acSHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20502173acSHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21502173acSHawking Zhang * 22502173acSHawking Zhang */ 23502173acSHawking Zhang #ifndef _osssys_4_2_0_OFFSET_HEADER 24502173acSHawking Zhang #define _osssys_4_2_0_OFFSET_HEADER 25502173acSHawking Zhang 26502173acSHawking Zhang 27502173acSHawking Zhang 28502173acSHawking Zhang // addressBlock: osssys_osssysdec 29502173acSHawking Zhang // base address: 0x4280 30502173acSHawking Zhang #define mmIH_VMID_0_LUT 0x0000 31502173acSHawking Zhang #define mmIH_VMID_0_LUT_BASE_IDX 0 32502173acSHawking Zhang #define mmIH_VMID_1_LUT 0x0001 33502173acSHawking Zhang #define mmIH_VMID_1_LUT_BASE_IDX 0 34502173acSHawking Zhang #define mmIH_VMID_2_LUT 0x0002 35502173acSHawking Zhang #define mmIH_VMID_2_LUT_BASE_IDX 0 36502173acSHawking Zhang #define mmIH_VMID_3_LUT 0x0003 37502173acSHawking Zhang #define mmIH_VMID_3_LUT_BASE_IDX 0 38502173acSHawking Zhang #define mmIH_VMID_4_LUT 0x0004 39502173acSHawking Zhang #define mmIH_VMID_4_LUT_BASE_IDX 0 40502173acSHawking Zhang #define mmIH_VMID_5_LUT 0x0005 41502173acSHawking Zhang #define mmIH_VMID_5_LUT_BASE_IDX 0 42502173acSHawking Zhang #define mmIH_VMID_6_LUT 0x0006 43502173acSHawking Zhang #define mmIH_VMID_6_LUT_BASE_IDX 0 44502173acSHawking Zhang #define mmIH_VMID_7_LUT 0x0007 45502173acSHawking Zhang #define mmIH_VMID_7_LUT_BASE_IDX 0 46502173acSHawking Zhang #define mmIH_VMID_8_LUT 0x0008 47502173acSHawking Zhang #define mmIH_VMID_8_LUT_BASE_IDX 0 48502173acSHawking Zhang #define mmIH_VMID_9_LUT 0x0009 49502173acSHawking Zhang #define mmIH_VMID_9_LUT_BASE_IDX 0 50502173acSHawking Zhang #define mmIH_VMID_10_LUT 0x000a 51502173acSHawking Zhang #define mmIH_VMID_10_LUT_BASE_IDX 0 52502173acSHawking Zhang #define mmIH_VMID_11_LUT 0x000b 53502173acSHawking Zhang #define mmIH_VMID_11_LUT_BASE_IDX 0 54502173acSHawking Zhang #define mmIH_VMID_12_LUT 0x000c 55502173acSHawking Zhang #define mmIH_VMID_12_LUT_BASE_IDX 0 56502173acSHawking Zhang #define mmIH_VMID_13_LUT 0x000d 57502173acSHawking Zhang #define mmIH_VMID_13_LUT_BASE_IDX 0 58502173acSHawking Zhang #define mmIH_VMID_14_LUT 0x000e 59502173acSHawking Zhang #define mmIH_VMID_14_LUT_BASE_IDX 0 60502173acSHawking Zhang #define mmIH_VMID_15_LUT 0x000f 61502173acSHawking Zhang #define mmIH_VMID_15_LUT_BASE_IDX 0 62502173acSHawking Zhang #define mmIH_VMID_0_LUT_MM 0x0010 63502173acSHawking Zhang #define mmIH_VMID_0_LUT_MM_BASE_IDX 0 64502173acSHawking Zhang #define mmIH_VMID_1_LUT_MM 0x0011 65502173acSHawking Zhang #define mmIH_VMID_1_LUT_MM_BASE_IDX 0 66502173acSHawking Zhang #define mmIH_VMID_2_LUT_MM 0x0012 67502173acSHawking Zhang #define mmIH_VMID_2_LUT_MM_BASE_IDX 0 68502173acSHawking Zhang #define mmIH_VMID_3_LUT_MM 0x0013 69502173acSHawking Zhang #define mmIH_VMID_3_LUT_MM_BASE_IDX 0 70502173acSHawking Zhang #define mmIH_VMID_4_LUT_MM 0x0014 71502173acSHawking Zhang #define mmIH_VMID_4_LUT_MM_BASE_IDX 0 72502173acSHawking Zhang #define mmIH_VMID_5_LUT_MM 0x0015 73502173acSHawking Zhang #define mmIH_VMID_5_LUT_MM_BASE_IDX 0 74502173acSHawking Zhang #define mmIH_VMID_6_LUT_MM 0x0016 75502173acSHawking Zhang #define mmIH_VMID_6_LUT_MM_BASE_IDX 0 76502173acSHawking Zhang #define mmIH_VMID_7_LUT_MM 0x0017 77502173acSHawking Zhang #define mmIH_VMID_7_LUT_MM_BASE_IDX 0 78502173acSHawking Zhang #define mmIH_VMID_8_LUT_MM 0x0018 79502173acSHawking Zhang #define mmIH_VMID_8_LUT_MM_BASE_IDX 0 80502173acSHawking Zhang #define mmIH_VMID_9_LUT_MM 0x0019 81502173acSHawking Zhang #define mmIH_VMID_9_LUT_MM_BASE_IDX 0 82502173acSHawking Zhang #define mmIH_VMID_10_LUT_MM 0x001a 83502173acSHawking Zhang #define mmIH_VMID_10_LUT_MM_BASE_IDX 0 84502173acSHawking Zhang #define mmIH_VMID_11_LUT_MM 0x001b 85502173acSHawking Zhang #define mmIH_VMID_11_LUT_MM_BASE_IDX 0 86502173acSHawking Zhang #define mmIH_VMID_12_LUT_MM 0x001c 87502173acSHawking Zhang #define mmIH_VMID_12_LUT_MM_BASE_IDX 0 88502173acSHawking Zhang #define mmIH_VMID_13_LUT_MM 0x001d 89502173acSHawking Zhang #define mmIH_VMID_13_LUT_MM_BASE_IDX 0 90502173acSHawking Zhang #define mmIH_VMID_14_LUT_MM 0x001e 91502173acSHawking Zhang #define mmIH_VMID_14_LUT_MM_BASE_IDX 0 92502173acSHawking Zhang #define mmIH_VMID_15_LUT_MM 0x001f 93502173acSHawking Zhang #define mmIH_VMID_15_LUT_MM_BASE_IDX 0 94502173acSHawking Zhang #define mmIH_COOKIE_0 0x0020 95502173acSHawking Zhang #define mmIH_COOKIE_0_BASE_IDX 0 96502173acSHawking Zhang #define mmIH_COOKIE_1 0x0021 97502173acSHawking Zhang #define mmIH_COOKIE_1_BASE_IDX 0 98502173acSHawking Zhang #define mmIH_COOKIE_2 0x0022 99502173acSHawking Zhang #define mmIH_COOKIE_2_BASE_IDX 0 100502173acSHawking Zhang #define mmIH_COOKIE_3 0x0023 101502173acSHawking Zhang #define mmIH_COOKIE_3_BASE_IDX 0 102502173acSHawking Zhang #define mmIH_COOKIE_4 0x0024 103502173acSHawking Zhang #define mmIH_COOKIE_4_BASE_IDX 0 104502173acSHawking Zhang #define mmIH_COOKIE_5 0x0025 105502173acSHawking Zhang #define mmIH_COOKIE_5_BASE_IDX 0 106502173acSHawking Zhang #define mmIH_COOKIE_6 0x0026 107502173acSHawking Zhang #define mmIH_COOKIE_6_BASE_IDX 0 108502173acSHawking Zhang #define mmIH_COOKIE_7 0x0027 109502173acSHawking Zhang #define mmIH_COOKIE_7_BASE_IDX 0 110502173acSHawking Zhang #define mmIH_REGISTER_LAST_PART0 0x003f 111502173acSHawking Zhang #define mmIH_REGISTER_LAST_PART0_BASE_IDX 0 112502173acSHawking Zhang #define mmSEM_REQ_INPUT_0 0x0040 113502173acSHawking Zhang #define mmSEM_REQ_INPUT_0_BASE_IDX 0 114502173acSHawking Zhang #define mmSEM_REQ_INPUT_1 0x0041 115502173acSHawking Zhang #define mmSEM_REQ_INPUT_1_BASE_IDX 0 116502173acSHawking Zhang #define mmSEM_REQ_INPUT_2 0x0042 117502173acSHawking Zhang #define mmSEM_REQ_INPUT_2_BASE_IDX 0 118502173acSHawking Zhang #define mmSEM_REQ_INPUT_3 0x0043 119502173acSHawking Zhang #define mmSEM_REQ_INPUT_3_BASE_IDX 0 120502173acSHawking Zhang #define mmSEM_REGISTER_LAST_PART0 0x007f 121502173acSHawking Zhang #define mmSEM_REGISTER_LAST_PART0_BASE_IDX 0 122502173acSHawking Zhang #define mmIH_RB_CNTL 0x0080 123502173acSHawking Zhang #define mmIH_RB_CNTL_BASE_IDX 0 124502173acSHawking Zhang #define mmIH_RB_BASE 0x0081 125502173acSHawking Zhang #define mmIH_RB_BASE_BASE_IDX 0 126502173acSHawking Zhang #define mmIH_RB_BASE_HI 0x0082 127502173acSHawking Zhang #define mmIH_RB_BASE_HI_BASE_IDX 0 128502173acSHawking Zhang #define mmIH_RB_RPTR 0x0083 129502173acSHawking Zhang #define mmIH_RB_RPTR_BASE_IDX 0 130502173acSHawking Zhang #define mmIH_RB_WPTR 0x0084 131502173acSHawking Zhang #define mmIH_RB_WPTR_BASE_IDX 0 132502173acSHawking Zhang #define mmIH_RB_WPTR_ADDR_HI 0x0085 133502173acSHawking Zhang #define mmIH_RB_WPTR_ADDR_HI_BASE_IDX 0 134502173acSHawking Zhang #define mmIH_RB_WPTR_ADDR_LO 0x0086 135502173acSHawking Zhang #define mmIH_RB_WPTR_ADDR_LO_BASE_IDX 0 136502173acSHawking Zhang #define mmIH_DOORBELL_RPTR 0x0087 137502173acSHawking Zhang #define mmIH_DOORBELL_RPTR_BASE_IDX 0 138*318e431bSMukul Joshi #define mmIH_DOORBELL_RETRY_CAM 0x0088 139*318e431bSMukul Joshi #define mmIH_DOORBELL_RETRY_CAM_BASE_IDX 0 140502173acSHawking Zhang #define mmIH_RB_CNTL_RING1 0x008c 141502173acSHawking Zhang #define mmIH_RB_CNTL_RING1_BASE_IDX 0 142502173acSHawking Zhang #define mmIH_RB_BASE_RING1 0x008d 143502173acSHawking Zhang #define mmIH_RB_BASE_RING1_BASE_IDX 0 144502173acSHawking Zhang #define mmIH_RB_BASE_HI_RING1 0x008e 145502173acSHawking Zhang #define mmIH_RB_BASE_HI_RING1_BASE_IDX 0 146502173acSHawking Zhang #define mmIH_RB_RPTR_RING1 0x008f 147502173acSHawking Zhang #define mmIH_RB_RPTR_RING1_BASE_IDX 0 148502173acSHawking Zhang #define mmIH_RB_WPTR_RING1 0x0090 149502173acSHawking Zhang #define mmIH_RB_WPTR_RING1_BASE_IDX 0 150502173acSHawking Zhang #define mmIH_DOORBELL_RPTR_RING1 0x0093 151502173acSHawking Zhang #define mmIH_DOORBELL_RPTR_RING1_BASE_IDX 0 152502173acSHawking Zhang #define mmIH_RB_CNTL_RING2 0x0098 153502173acSHawking Zhang #define mmIH_RB_CNTL_RING2_BASE_IDX 0 154502173acSHawking Zhang #define mmIH_RB_BASE_RING2 0x0099 155502173acSHawking Zhang #define mmIH_RB_BASE_RING2_BASE_IDX 0 156502173acSHawking Zhang #define mmIH_RB_BASE_HI_RING2 0x009a 157502173acSHawking Zhang #define mmIH_RB_BASE_HI_RING2_BASE_IDX 0 158502173acSHawking Zhang #define mmIH_RB_RPTR_RING2 0x009b 159502173acSHawking Zhang #define mmIH_RB_RPTR_RING2_BASE_IDX 0 160502173acSHawking Zhang #define mmIH_RB_WPTR_RING2 0x009c 161502173acSHawking Zhang #define mmIH_RB_WPTR_RING2_BASE_IDX 0 162502173acSHawking Zhang #define mmIH_DOORBELL_RPTR_RING2 0x009f 163502173acSHawking Zhang #define mmIH_DOORBELL_RPTR_RING2_BASE_IDX 0 164*318e431bSMukul Joshi #define mmIH_RETRY_CAM_ACK 0x00a4 165*318e431bSMukul Joshi #define mmIH_RETRY_CAM_ACK_BASE_IDX 0 166502173acSHawking Zhang #define mmIH_VERSION 0x00a5 167502173acSHawking Zhang #define mmIH_VERSION_BASE_IDX 0 168502173acSHawking Zhang #define mmIH_CNTL 0x00c0 169502173acSHawking Zhang #define mmIH_CNTL_BASE_IDX 0 170502173acSHawking Zhang #define mmIH_CNTL2 0x00c1 171502173acSHawking Zhang #define mmIH_CNTL2_BASE_IDX 0 172502173acSHawking Zhang #define mmIH_STATUS 0x00c2 173502173acSHawking Zhang #define mmIH_STATUS_BASE_IDX 0 174502173acSHawking Zhang #define mmIH_PERFMON_CNTL 0x00c3 175502173acSHawking Zhang #define mmIH_PERFMON_CNTL_BASE_IDX 0 176502173acSHawking Zhang #define mmIH_PERFCOUNTER0_RESULT 0x00c4 177502173acSHawking Zhang #define mmIH_PERFCOUNTER0_RESULT_BASE_IDX 0 178502173acSHawking Zhang #define mmIH_PERFCOUNTER1_RESULT 0x00c5 179502173acSHawking Zhang #define mmIH_PERFCOUNTER1_RESULT_BASE_IDX 0 180502173acSHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7 181502173acSHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0 182502173acSHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8 183502173acSHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0 184502173acSHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9 185502173acSHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0 186502173acSHawking Zhang #define mmIH_DSM_MATCH_FIELD_CONTROL 0x00ca 187502173acSHawking Zhang #define mmIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0 188502173acSHawking Zhang #define mmIH_DSM_MATCH_DATA_CONTROL 0x00cb 189502173acSHawking Zhang #define mmIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0 190502173acSHawking Zhang #define mmIH_DSM_MATCH_FCN_ID 0x00cc 191502173acSHawking Zhang #define mmIH_DSM_MATCH_FCN_ID_BASE_IDX 0 192502173acSHawking Zhang #define mmIH_LIMIT_INT_RATE_CNTL 0x00cd 193502173acSHawking Zhang #define mmIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0 194502173acSHawking Zhang #define mmIH_VF_RB_STATUS 0x00ce 195502173acSHawking Zhang #define mmIH_VF_RB_STATUS_BASE_IDX 0 196502173acSHawking Zhang #define mmIH_VF_RB_STATUS2 0x00cf 197502173acSHawking Zhang #define mmIH_VF_RB_STATUS2_BASE_IDX 0 198502173acSHawking Zhang #define mmIH_VF_RB1_STATUS 0x00d0 199502173acSHawking Zhang #define mmIH_VF_RB1_STATUS_BASE_IDX 0 200502173acSHawking Zhang #define mmIH_VF_RB1_STATUS2 0x00d1 201502173acSHawking Zhang #define mmIH_VF_RB1_STATUS2_BASE_IDX 0 202502173acSHawking Zhang #define mmIH_VF_RB2_STATUS 0x00d2 203502173acSHawking Zhang #define mmIH_VF_RB2_STATUS_BASE_IDX 0 204502173acSHawking Zhang #define mmIH_VF_RB2_STATUS2 0x00d3 205502173acSHawking Zhang #define mmIH_VF_RB2_STATUS2_BASE_IDX 0 206502173acSHawking Zhang #define mmIH_INT_FLOOD_CNTL 0x00d5 207502173acSHawking Zhang #define mmIH_INT_FLOOD_CNTL_BASE_IDX 0 208502173acSHawking Zhang #define mmIH_RB0_INT_FLOOD_STATUS 0x00d6 209502173acSHawking Zhang #define mmIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0 210502173acSHawking Zhang #define mmIH_RB1_INT_FLOOD_STATUS 0x00d7 211502173acSHawking Zhang #define mmIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0 212502173acSHawking Zhang #define mmIH_RB2_INT_FLOOD_STATUS 0x00d8 213502173acSHawking Zhang #define mmIH_RB2_INT_FLOOD_STATUS_BASE_IDX 0 214502173acSHawking Zhang #define mmIH_INT_FLOOD_STATUS 0x00d9 215502173acSHawking Zhang #define mmIH_INT_FLOOD_STATUS_BASE_IDX 0 216502173acSHawking Zhang #define mmIH_STORM_CLIENT_LIST_CNTL 0x00da 217502173acSHawking Zhang #define mmIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0 218502173acSHawking Zhang #define mmIH_CLK_CTRL 0x00db 219502173acSHawking Zhang #define mmIH_CLK_CTRL_BASE_IDX 0 220502173acSHawking Zhang #define mmIH_INT_FLAGS 0x00dc 221502173acSHawking Zhang #define mmIH_INT_FLAGS_BASE_IDX 0 222502173acSHawking Zhang #define mmIH_LAST_INT_INFO0 0x00dd 223502173acSHawking Zhang #define mmIH_LAST_INT_INFO0_BASE_IDX 0 224502173acSHawking Zhang #define mmIH_LAST_INT_INFO1 0x00de 225502173acSHawking Zhang #define mmIH_LAST_INT_INFO1_BASE_IDX 0 226502173acSHawking Zhang #define mmIH_LAST_INT_INFO2 0x00df 227502173acSHawking Zhang #define mmIH_LAST_INT_INFO2_BASE_IDX 0 228502173acSHawking Zhang #define mmIH_SCRATCH 0x00e0 229502173acSHawking Zhang #define mmIH_SCRATCH_BASE_IDX 0 230502173acSHawking Zhang #define mmIH_CLIENT_CREDIT_ERROR 0x00e1 231502173acSHawking Zhang #define mmIH_CLIENT_CREDIT_ERROR_BASE_IDX 0 232502173acSHawking Zhang #define mmIH_GPU_IOV_VIOLATION_LOG 0x00e2 233502173acSHawking Zhang #define mmIH_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 234502173acSHawking Zhang #define mmIH_COOKIE_REC_VIOLATION_LOG 0x00e3 235502173acSHawking Zhang #define mmIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0 236502173acSHawking Zhang #define mmIH_CREDIT_STATUS 0x00e4 237502173acSHawking Zhang #define mmIH_CREDIT_STATUS_BASE_IDX 0 238502173acSHawking Zhang #define mmIH_MMHUB_ERROR 0x00e5 239502173acSHawking Zhang #define mmIH_MMHUB_ERROR_BASE_IDX 0 240502173acSHawking Zhang #define mmIH_MEM_POWER_CTRL 0x00e8 241502173acSHawking Zhang #define mmIH_MEM_POWER_CTRL_BASE_IDX 0 242*318e431bSMukul Joshi #define mmIH_RETRY_INT_CAM_CNTL 0x00e9 243*318e431bSMukul Joshi #define mmIH_RETRY_INT_CAM_CNTL_BASE_IDX 0 244502173acSHawking Zhang #define mmIH_REGISTER_LAST_PART2 0x00ff 245502173acSHawking Zhang #define mmIH_REGISTER_LAST_PART2_BASE_IDX 0 246502173acSHawking Zhang #define mmSEM_CLK_CTRL 0x0100 247502173acSHawking Zhang #define mmSEM_CLK_CTRL_BASE_IDX 0 248502173acSHawking Zhang #define mmSEM_UTC_CREDIT 0x0101 249502173acSHawking Zhang #define mmSEM_UTC_CREDIT_BASE_IDX 0 250502173acSHawking Zhang #define mmSEM_UTC_CONFIG 0x0102 251502173acSHawking Zhang #define mmSEM_UTC_CONFIG_BASE_IDX 0 252502173acSHawking Zhang #define mmSEM_UTCL2_TRAN_EN_LUT 0x0103 253502173acSHawking Zhang #define mmSEM_UTCL2_TRAN_EN_LUT_BASE_IDX 0 254502173acSHawking Zhang #define mmSEM_MCIF_CONFIG 0x0104 255502173acSHawking Zhang #define mmSEM_MCIF_CONFIG_BASE_IDX 0 256502173acSHawking Zhang #define mmSEM_PERFMON_CNTL 0x0105 257502173acSHawking Zhang #define mmSEM_PERFMON_CNTL_BASE_IDX 0 258502173acSHawking Zhang #define mmSEM_PERFCOUNTER0_RESULT 0x0106 259502173acSHawking Zhang #define mmSEM_PERFCOUNTER0_RESULT_BASE_IDX 0 260502173acSHawking Zhang #define mmSEM_PERFCOUNTER1_RESULT 0x0107 261502173acSHawking Zhang #define mmSEM_PERFCOUNTER1_RESULT_BASE_IDX 0 262502173acSHawking Zhang #define mmSEM_STATUS 0x0108 263502173acSHawking Zhang #define mmSEM_STATUS_BASE_IDX 0 264502173acSHawking Zhang #define mmSEM_MAILBOX_CLIENTCONFIG 0x0109 265502173acSHawking Zhang #define mmSEM_MAILBOX_CLIENTCONFIG_BASE_IDX 0 266502173acSHawking Zhang #define mmSEM_MAILBOX 0x010a 267502173acSHawking Zhang #define mmSEM_MAILBOX_BASE_IDX 0 268502173acSHawking Zhang #define mmSEM_MAILBOX_CONTROL 0x010b 269502173acSHawking Zhang #define mmSEM_MAILBOX_CONTROL_BASE_IDX 0 270502173acSHawking Zhang #define mmSEM_CHICKEN_BITS 0x010c 271502173acSHawking Zhang #define mmSEM_CHICKEN_BITS_BASE_IDX 0 272502173acSHawking Zhang #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0x010d 273502173acSHawking Zhang #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_BASE_IDX 0 274502173acSHawking Zhang #define mmSEM_GPU_IOV_VIOLATION_LOG 0x010e 275502173acSHawking Zhang #define mmSEM_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 276502173acSHawking Zhang #define mmSEM_OUTSTANDING_THRESHOLD 0x010f 277502173acSHawking Zhang #define mmSEM_OUTSTANDING_THRESHOLD_BASE_IDX 0 278502173acSHawking Zhang #define mmSEM_MEM_POWER_CTRL 0x0110 279502173acSHawking Zhang #define mmSEM_MEM_POWER_CTRL_BASE_IDX 0 280502173acSHawking Zhang #define mmSEM_REGISTER_LAST_PART2 0x017f 281502173acSHawking Zhang #define mmSEM_REGISTER_LAST_PART2_BASE_IDX 0 282502173acSHawking Zhang #define mmIH_ACTIVE_FCN_ID 0x0180 283502173acSHawking Zhang #define mmIH_ACTIVE_FCN_ID_BASE_IDX 0 284502173acSHawking Zhang #define mmIH_VIRT_RESET_REQ 0x0181 285502173acSHawking Zhang #define mmIH_VIRT_RESET_REQ_BASE_IDX 0 286502173acSHawking Zhang #define mmIH_CLIENT_CFG 0x0184 287502173acSHawking Zhang #define mmIH_CLIENT_CFG_BASE_IDX 0 288502173acSHawking Zhang #define mmIH_CLIENT_CFG_INDEX 0x0188 289502173acSHawking Zhang #define mmIH_CLIENT_CFG_INDEX_BASE_IDX 0 290502173acSHawking Zhang #define mmIH_CLIENT_CFG_DATA 0x0189 291502173acSHawking Zhang #define mmIH_CLIENT_CFG_DATA_BASE_IDX 0 292502173acSHawking Zhang #define mmIH_CID_REMAP_INDEX 0x018a 293502173acSHawking Zhang #define mmIH_CID_REMAP_INDEX_BASE_IDX 0 294502173acSHawking Zhang #define mmIH_CID_REMAP_DATA 0x018b 295502173acSHawking Zhang #define mmIH_CID_REMAP_DATA_BASE_IDX 0 296502173acSHawking Zhang #define mmIH_CHICKEN 0x018c 297502173acSHawking Zhang #define mmIH_CHICKEN_BASE_IDX 0 298502173acSHawking Zhang #define mmIH_MMHUB_CNTL 0x018d 299502173acSHawking Zhang #define mmIH_MMHUB_CNTL_BASE_IDX 0 300502173acSHawking Zhang #define mmIH_INT_DROP_CNTL 0x018e 301502173acSHawking Zhang #define mmIH_INT_DROP_CNTL_BASE_IDX 0 302502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_VALUE0 0x018f 303502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_VALUE0_BASE_IDX 0 304502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_VALUE1 0x0190 305502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_VALUE1_BASE_IDX 0 306502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_MASK0 0x0191 307502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_MASK0_BASE_IDX 0 308502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_MASK1 0x0192 309502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_MASK1_BASE_IDX 0 310502173acSHawking Zhang #define mmIH_REGISTER_LAST_PART1 0x019f 311502173acSHawking Zhang #define mmIH_REGISTER_LAST_PART1_BASE_IDX 0 312502173acSHawking Zhang #define mmSEM_ACTIVE_FCN_ID 0x01a0 313502173acSHawking Zhang #define mmSEM_ACTIVE_FCN_ID_BASE_IDX 0 314502173acSHawking Zhang #define mmSEM_VIRT_RESET_REQ 0x01a1 315502173acSHawking Zhang #define mmSEM_VIRT_RESET_REQ_BASE_IDX 0 316502173acSHawking Zhang #define mmSEM_RESP_SDMA0 0x01a4 317502173acSHawking Zhang #define mmSEM_RESP_SDMA0_BASE_IDX 0 318502173acSHawking Zhang #define mmSEM_RESP_SDMA1 0x01a5 319502173acSHawking Zhang #define mmSEM_RESP_SDMA1_BASE_IDX 0 320502173acSHawking Zhang #define mmSEM_RESP_UVD 0x01a6 321502173acSHawking Zhang #define mmSEM_RESP_UVD_BASE_IDX 0 322502173acSHawking Zhang #define mmSEM_RESP_VCE_0 0x01a7 323502173acSHawking Zhang #define mmSEM_RESP_VCE_0_BASE_IDX 0 324502173acSHawking Zhang #define mmSEM_RESP_ACP 0x01a8 325502173acSHawking Zhang #define mmSEM_RESP_ACP_BASE_IDX 0 326502173acSHawking Zhang #define mmSEM_RESP_ISP 0x01a9 327502173acSHawking Zhang #define mmSEM_RESP_ISP_BASE_IDX 0 328502173acSHawking Zhang #define mmSEM_RESP_VCE_1 0x01aa 329502173acSHawking Zhang #define mmSEM_RESP_VCE_1_BASE_IDX 0 330502173acSHawking Zhang #define mmSEM_RESP_VP8 0x01ab 331502173acSHawking Zhang #define mmSEM_RESP_VP8_BASE_IDX 0 332502173acSHawking Zhang #define mmSEM_RESP_GC 0x01ac 333502173acSHawking Zhang #define mmSEM_RESP_GC_BASE_IDX 0 334502173acSHawking Zhang #define mmSEM_RESP_UVD_1 0x01ad 335502173acSHawking Zhang #define mmSEM_RESP_UVD_1_BASE_IDX 0 336502173acSHawking Zhang #define mmSEM_CID_REMAP_INDEX 0x01b0 337502173acSHawking Zhang #define mmSEM_CID_REMAP_INDEX_BASE_IDX 0 338502173acSHawking Zhang #define mmSEM_CID_REMAP_DATA 0x01b1 339502173acSHawking Zhang #define mmSEM_CID_REMAP_DATA_BASE_IDX 0 340502173acSHawking Zhang #define mmSEM_ATOMIC_OP_LUT 0x01b2 341502173acSHawking Zhang #define mmSEM_ATOMIC_OP_LUT_BASE_IDX 0 342502173acSHawking Zhang #define mmSEM_EDC_CONFIG 0x01b3 343502173acSHawking Zhang #define mmSEM_EDC_CONFIG_BASE_IDX 0 344502173acSHawking Zhang #define mmSEM_CHICKEN_BITS2 0x01b4 345502173acSHawking Zhang #define mmSEM_CHICKEN_BITS2_BASE_IDX 0 346502173acSHawking Zhang #define mmSEM_MMHUB_CNTL 0x01b5 347502173acSHawking Zhang #define mmSEM_MMHUB_CNTL_BASE_IDX 0 348502173acSHawking Zhang #define mmSEM_REGISTER_LAST_PART1 0x01bf 349502173acSHawking Zhang #define mmSEM_REGISTER_LAST_PART1_BASE_IDX 0 350502173acSHawking Zhang 351502173acSHawking Zhang #endif 352