1133f9794SFeifei Xu /* 2133f9794SFeifei Xu * Copyright (C) 2017 Advanced Micro Devices, Inc. 3133f9794SFeifei Xu * 4133f9794SFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 5133f9794SFeifei Xu * copy of this software and associated documentation files (the "Software"), 6133f9794SFeifei Xu * to deal in the Software without restriction, including without limitation 7133f9794SFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8133f9794SFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 9133f9794SFeifei Xu * Software is furnished to do so, subject to the following conditions: 10133f9794SFeifei Xu * 11133f9794SFeifei Xu * The above copyright notice and this permission notice shall be included 12133f9794SFeifei Xu * in all copies or substantial portions of the Software. 13133f9794SFeifei Xu * 14133f9794SFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15133f9794SFeifei Xu * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16133f9794SFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17133f9794SFeifei Xu * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18133f9794SFeifei Xu * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19133f9794SFeifei Xu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20133f9794SFeifei Xu */ 21133f9794SFeifei Xu #ifndef _osssys_4_0_1_OFFSET_HEADER 22133f9794SFeifei Xu #define _osssys_4_0_1_OFFSET_HEADER 23133f9794SFeifei Xu 24133f9794SFeifei Xu 25133f9794SFeifei Xu 26133f9794SFeifei Xu // addressBlock: osssys_osssysdec 27133f9794SFeifei Xu // base address: 0x4280 28133f9794SFeifei Xu #define mmIH_VMID_0_LUT 0x0000 29133f9794SFeifei Xu #define mmIH_VMID_0_LUT_BASE_IDX 0 30133f9794SFeifei Xu #define mmIH_VMID_1_LUT 0x0001 31133f9794SFeifei Xu #define mmIH_VMID_1_LUT_BASE_IDX 0 32133f9794SFeifei Xu #define mmIH_VMID_2_LUT 0x0002 33133f9794SFeifei Xu #define mmIH_VMID_2_LUT_BASE_IDX 0 34133f9794SFeifei Xu #define mmIH_VMID_3_LUT 0x0003 35133f9794SFeifei Xu #define mmIH_VMID_3_LUT_BASE_IDX 0 36133f9794SFeifei Xu #define mmIH_VMID_4_LUT 0x0004 37133f9794SFeifei Xu #define mmIH_VMID_4_LUT_BASE_IDX 0 38133f9794SFeifei Xu #define mmIH_VMID_5_LUT 0x0005 39133f9794SFeifei Xu #define mmIH_VMID_5_LUT_BASE_IDX 0 40133f9794SFeifei Xu #define mmIH_VMID_6_LUT 0x0006 41133f9794SFeifei Xu #define mmIH_VMID_6_LUT_BASE_IDX 0 42133f9794SFeifei Xu #define mmIH_VMID_7_LUT 0x0007 43133f9794SFeifei Xu #define mmIH_VMID_7_LUT_BASE_IDX 0 44133f9794SFeifei Xu #define mmIH_VMID_8_LUT 0x0008 45133f9794SFeifei Xu #define mmIH_VMID_8_LUT_BASE_IDX 0 46133f9794SFeifei Xu #define mmIH_VMID_9_LUT 0x0009 47133f9794SFeifei Xu #define mmIH_VMID_9_LUT_BASE_IDX 0 48133f9794SFeifei Xu #define mmIH_VMID_10_LUT 0x000a 49133f9794SFeifei Xu #define mmIH_VMID_10_LUT_BASE_IDX 0 50133f9794SFeifei Xu #define mmIH_VMID_11_LUT 0x000b 51133f9794SFeifei Xu #define mmIH_VMID_11_LUT_BASE_IDX 0 52133f9794SFeifei Xu #define mmIH_VMID_12_LUT 0x000c 53133f9794SFeifei Xu #define mmIH_VMID_12_LUT_BASE_IDX 0 54133f9794SFeifei Xu #define mmIH_VMID_13_LUT 0x000d 55133f9794SFeifei Xu #define mmIH_VMID_13_LUT_BASE_IDX 0 56133f9794SFeifei Xu #define mmIH_VMID_14_LUT 0x000e 57133f9794SFeifei Xu #define mmIH_VMID_14_LUT_BASE_IDX 0 58133f9794SFeifei Xu #define mmIH_VMID_15_LUT 0x000f 59133f9794SFeifei Xu #define mmIH_VMID_15_LUT_BASE_IDX 0 60133f9794SFeifei Xu #define mmIH_VMID_0_LUT_MM 0x0010 61133f9794SFeifei Xu #define mmIH_VMID_0_LUT_MM_BASE_IDX 0 62133f9794SFeifei Xu #define mmIH_VMID_1_LUT_MM 0x0011 63133f9794SFeifei Xu #define mmIH_VMID_1_LUT_MM_BASE_IDX 0 64133f9794SFeifei Xu #define mmIH_VMID_2_LUT_MM 0x0012 65133f9794SFeifei Xu #define mmIH_VMID_2_LUT_MM_BASE_IDX 0 66133f9794SFeifei Xu #define mmIH_VMID_3_LUT_MM 0x0013 67133f9794SFeifei Xu #define mmIH_VMID_3_LUT_MM_BASE_IDX 0 68133f9794SFeifei Xu #define mmIH_VMID_4_LUT_MM 0x0014 69133f9794SFeifei Xu #define mmIH_VMID_4_LUT_MM_BASE_IDX 0 70133f9794SFeifei Xu #define mmIH_VMID_5_LUT_MM 0x0015 71133f9794SFeifei Xu #define mmIH_VMID_5_LUT_MM_BASE_IDX 0 72133f9794SFeifei Xu #define mmIH_VMID_6_LUT_MM 0x0016 73133f9794SFeifei Xu #define mmIH_VMID_6_LUT_MM_BASE_IDX 0 74133f9794SFeifei Xu #define mmIH_VMID_7_LUT_MM 0x0017 75133f9794SFeifei Xu #define mmIH_VMID_7_LUT_MM_BASE_IDX 0 76133f9794SFeifei Xu #define mmIH_VMID_8_LUT_MM 0x0018 77133f9794SFeifei Xu #define mmIH_VMID_8_LUT_MM_BASE_IDX 0 78133f9794SFeifei Xu #define mmIH_VMID_9_LUT_MM 0x0019 79133f9794SFeifei Xu #define mmIH_VMID_9_LUT_MM_BASE_IDX 0 80133f9794SFeifei Xu #define mmIH_VMID_10_LUT_MM 0x001a 81133f9794SFeifei Xu #define mmIH_VMID_10_LUT_MM_BASE_IDX 0 82133f9794SFeifei Xu #define mmIH_VMID_11_LUT_MM 0x001b 83133f9794SFeifei Xu #define mmIH_VMID_11_LUT_MM_BASE_IDX 0 84133f9794SFeifei Xu #define mmIH_VMID_12_LUT_MM 0x001c 85133f9794SFeifei Xu #define mmIH_VMID_12_LUT_MM_BASE_IDX 0 86133f9794SFeifei Xu #define mmIH_VMID_13_LUT_MM 0x001d 87133f9794SFeifei Xu #define mmIH_VMID_13_LUT_MM_BASE_IDX 0 88133f9794SFeifei Xu #define mmIH_VMID_14_LUT_MM 0x001e 89133f9794SFeifei Xu #define mmIH_VMID_14_LUT_MM_BASE_IDX 0 90133f9794SFeifei Xu #define mmIH_VMID_15_LUT_MM 0x001f 91133f9794SFeifei Xu #define mmIH_VMID_15_LUT_MM_BASE_IDX 0 92133f9794SFeifei Xu #define mmIH_COOKIE_0 0x0020 93133f9794SFeifei Xu #define mmIH_COOKIE_0_BASE_IDX 0 94133f9794SFeifei Xu #define mmIH_COOKIE_1 0x0021 95133f9794SFeifei Xu #define mmIH_COOKIE_1_BASE_IDX 0 96133f9794SFeifei Xu #define mmIH_COOKIE_2 0x0022 97133f9794SFeifei Xu #define mmIH_COOKIE_2_BASE_IDX 0 98133f9794SFeifei Xu #define mmIH_COOKIE_3 0x0023 99133f9794SFeifei Xu #define mmIH_COOKIE_3_BASE_IDX 0 100133f9794SFeifei Xu #define mmIH_COOKIE_4 0x0024 101133f9794SFeifei Xu #define mmIH_COOKIE_4_BASE_IDX 0 102133f9794SFeifei Xu #define mmIH_COOKIE_5 0x0025 103133f9794SFeifei Xu #define mmIH_COOKIE_5_BASE_IDX 0 104133f9794SFeifei Xu #define mmIH_COOKIE_6 0x0026 105133f9794SFeifei Xu #define mmIH_COOKIE_6_BASE_IDX 0 106133f9794SFeifei Xu #define mmIH_COOKIE_7 0x0027 107133f9794SFeifei Xu #define mmIH_COOKIE_7_BASE_IDX 0 108133f9794SFeifei Xu #define mmIH_REGISTER_LAST_PART0 0x003f 109133f9794SFeifei Xu #define mmIH_REGISTER_LAST_PART0_BASE_IDX 0 110133f9794SFeifei Xu #define mmSEM_REQ_INPUT_0 0x0040 111133f9794SFeifei Xu #define mmSEM_REQ_INPUT_0_BASE_IDX 0 112133f9794SFeifei Xu #define mmSEM_REQ_INPUT_1 0x0041 113133f9794SFeifei Xu #define mmSEM_REQ_INPUT_1_BASE_IDX 0 114133f9794SFeifei Xu #define mmSEM_REQ_INPUT_2 0x0042 115133f9794SFeifei Xu #define mmSEM_REQ_INPUT_2_BASE_IDX 0 116133f9794SFeifei Xu #define mmSEM_REQ_INPUT_3 0x0043 117133f9794SFeifei Xu #define mmSEM_REQ_INPUT_3_BASE_IDX 0 118133f9794SFeifei Xu #define mmSEM_REGISTER_LAST_PART0 0x007f 119133f9794SFeifei Xu #define mmSEM_REGISTER_LAST_PART0_BASE_IDX 0 120133f9794SFeifei Xu #define mmIH_RB_CNTL 0x0080 121133f9794SFeifei Xu #define mmIH_RB_CNTL_BASE_IDX 0 122133f9794SFeifei Xu #define mmIH_RB_BASE 0x0081 123133f9794SFeifei Xu #define mmIH_RB_BASE_BASE_IDX 0 124133f9794SFeifei Xu #define mmIH_RB_BASE_HI 0x0082 125133f9794SFeifei Xu #define mmIH_RB_BASE_HI_BASE_IDX 0 126133f9794SFeifei Xu #define mmIH_RB_RPTR 0x0083 127133f9794SFeifei Xu #define mmIH_RB_RPTR_BASE_IDX 0 128133f9794SFeifei Xu #define mmIH_RB_WPTR 0x0084 129133f9794SFeifei Xu #define mmIH_RB_WPTR_BASE_IDX 0 130133f9794SFeifei Xu #define mmIH_RB_WPTR_ADDR_HI 0x0085 131133f9794SFeifei Xu #define mmIH_RB_WPTR_ADDR_HI_BASE_IDX 0 132133f9794SFeifei Xu #define mmIH_RB_WPTR_ADDR_LO 0x0086 133133f9794SFeifei Xu #define mmIH_RB_WPTR_ADDR_LO_BASE_IDX 0 134133f9794SFeifei Xu #define mmIH_DOORBELL_RPTR 0x0087 135133f9794SFeifei Xu #define mmIH_DOORBELL_RPTR_BASE_IDX 0 136133f9794SFeifei Xu #define mmIH_RB_CNTL_RING1 0x0088 137133f9794SFeifei Xu #define mmIH_RB_CNTL_RING1_BASE_IDX 0 138133f9794SFeifei Xu #define mmIH_RB_BASE_RING1 0x0089 139133f9794SFeifei Xu #define mmIH_RB_BASE_RING1_BASE_IDX 0 140133f9794SFeifei Xu #define mmIH_RB_BASE_HI_RING1 0x008a 141133f9794SFeifei Xu #define mmIH_RB_BASE_HI_RING1_BASE_IDX 0 142133f9794SFeifei Xu #define mmIH_RB_RPTR_RING1 0x008b 143133f9794SFeifei Xu #define mmIH_RB_RPTR_RING1_BASE_IDX 0 144133f9794SFeifei Xu #define mmIH_RB_WPTR_RING1 0x008c 145133f9794SFeifei Xu #define mmIH_RB_WPTR_RING1_BASE_IDX 0 146133f9794SFeifei Xu #define mmIH_DOORBELL_RPTR_RING1 0x008f 147133f9794SFeifei Xu #define mmIH_DOORBELL_RPTR_RING1_BASE_IDX 0 148133f9794SFeifei Xu #define mmIH_RB_CNTL_RING2 0x0090 149133f9794SFeifei Xu #define mmIH_RB_CNTL_RING2_BASE_IDX 0 150133f9794SFeifei Xu #define mmIH_RB_BASE_RING2 0x0091 151133f9794SFeifei Xu #define mmIH_RB_BASE_RING2_BASE_IDX 0 152133f9794SFeifei Xu #define mmIH_RB_BASE_HI_RING2 0x0092 153133f9794SFeifei Xu #define mmIH_RB_BASE_HI_RING2_BASE_IDX 0 154133f9794SFeifei Xu #define mmIH_RB_RPTR_RING2 0x0093 155133f9794SFeifei Xu #define mmIH_RB_RPTR_RING2_BASE_IDX 0 156133f9794SFeifei Xu #define mmIH_RB_WPTR_RING2 0x0094 157133f9794SFeifei Xu #define mmIH_RB_WPTR_RING2_BASE_IDX 0 158133f9794SFeifei Xu #define mmIH_DOORBELL_RPTR_RING2 0x0097 159133f9794SFeifei Xu #define mmIH_DOORBELL_RPTR_RING2_BASE_IDX 0 160133f9794SFeifei Xu #define mmIH_VERSION 0x0098 161133f9794SFeifei Xu #define mmIH_VERSION_BASE_IDX 0 162133f9794SFeifei Xu #define mmIH_CNTL 0x00c0 163133f9794SFeifei Xu #define mmIH_CNTL_BASE_IDX 0 164133f9794SFeifei Xu #define mmIH_CNTL2 0x00c1 165133f9794SFeifei Xu #define mmIH_CNTL2_BASE_IDX 0 166133f9794SFeifei Xu #define mmIH_STATUS 0x00c2 167133f9794SFeifei Xu #define mmIH_STATUS_BASE_IDX 0 168133f9794SFeifei Xu #define mmIH_PERFMON_CNTL 0x00c3 169133f9794SFeifei Xu #define mmIH_PERFMON_CNTL_BASE_IDX 0 170133f9794SFeifei Xu #define mmIH_PERFCOUNTER0_RESULT 0x00c4 171133f9794SFeifei Xu #define mmIH_PERFCOUNTER0_RESULT_BASE_IDX 0 172133f9794SFeifei Xu #define mmIH_PERFCOUNTER1_RESULT 0x00c5 173133f9794SFeifei Xu #define mmIH_PERFCOUNTER1_RESULT_BASE_IDX 0 174133f9794SFeifei Xu #define mmIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7 175133f9794SFeifei Xu #define mmIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0 176133f9794SFeifei Xu #define mmIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8 177133f9794SFeifei Xu #define mmIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0 178133f9794SFeifei Xu #define mmIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9 179133f9794SFeifei Xu #define mmIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0 180133f9794SFeifei Xu #define mmIH_DSM_MATCH_FIELD_CONTROL 0x00ca 181133f9794SFeifei Xu #define mmIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0 182133f9794SFeifei Xu #define mmIH_DSM_MATCH_DATA_CONTROL 0x00cb 183133f9794SFeifei Xu #define mmIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0 184133f9794SFeifei Xu #define mmIH_DSM_MATCH_FCN_ID 0x00cc 185133f9794SFeifei Xu #define mmIH_DSM_MATCH_FCN_ID_BASE_IDX 0 186133f9794SFeifei Xu #define mmIH_LIMIT_INT_RATE_CNTL 0x00cd 187133f9794SFeifei Xu #define mmIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0 188133f9794SFeifei Xu #define mmIH_VF_RB_STATUS 0x00ce 189133f9794SFeifei Xu #define mmIH_VF_RB_STATUS_BASE_IDX 0 190133f9794SFeifei Xu #define mmIH_VF_RB_STATUS2 0x00cf 191133f9794SFeifei Xu #define mmIH_VF_RB_STATUS2_BASE_IDX 0 192133f9794SFeifei Xu #define mmIH_VF_RB1_STATUS 0x00d0 193133f9794SFeifei Xu #define mmIH_VF_RB1_STATUS_BASE_IDX 0 194133f9794SFeifei Xu #define mmIH_VF_RB1_STATUS2 0x00d1 195133f9794SFeifei Xu #define mmIH_VF_RB1_STATUS2_BASE_IDX 0 196133f9794SFeifei Xu #define mmIH_VF_RB2_STATUS 0x00d2 197133f9794SFeifei Xu #define mmIH_VF_RB2_STATUS_BASE_IDX 0 198133f9794SFeifei Xu #define mmIH_VF_RB2_STATUS2 0x00d3 199133f9794SFeifei Xu #define mmIH_VF_RB2_STATUS2_BASE_IDX 0 200133f9794SFeifei Xu #define mmIH_INT_FLOOD_CNTL 0x00d5 201133f9794SFeifei Xu #define mmIH_INT_FLOOD_CNTL_BASE_IDX 0 202133f9794SFeifei Xu #define mmIH_RB0_INT_FLOOD_STATUS 0x00d6 203133f9794SFeifei Xu #define mmIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0 204133f9794SFeifei Xu #define mmIH_RB1_INT_FLOOD_STATUS 0x00d7 205133f9794SFeifei Xu #define mmIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0 206133f9794SFeifei Xu #define mmIH_RB2_INT_FLOOD_STATUS 0x00d8 207133f9794SFeifei Xu #define mmIH_RB2_INT_FLOOD_STATUS_BASE_IDX 0 208133f9794SFeifei Xu #define mmIH_INT_FLOOD_STATUS 0x00d9 209133f9794SFeifei Xu #define mmIH_INT_FLOOD_STATUS_BASE_IDX 0 210133f9794SFeifei Xu #define mmIH_STORM_CLIENT_LIST_CNTL 0x00da 211133f9794SFeifei Xu #define mmIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0 212133f9794SFeifei Xu #define mmIH_CLK_CTRL 0x00db 213133f9794SFeifei Xu #define mmIH_CLK_CTRL_BASE_IDX 0 214133f9794SFeifei Xu #define mmIH_INT_FLAGS 0x00dc 215133f9794SFeifei Xu #define mmIH_INT_FLAGS_BASE_IDX 0 216133f9794SFeifei Xu #define mmIH_LAST_INT_INFO0 0x00dd 217133f9794SFeifei Xu #define mmIH_LAST_INT_INFO0_BASE_IDX 0 218133f9794SFeifei Xu #define mmIH_LAST_INT_INFO1 0x00de 219133f9794SFeifei Xu #define mmIH_LAST_INT_INFO1_BASE_IDX 0 220133f9794SFeifei Xu #define mmIH_LAST_INT_INFO2 0x00df 221133f9794SFeifei Xu #define mmIH_LAST_INT_INFO2_BASE_IDX 0 222133f9794SFeifei Xu #define mmIH_SCRATCH 0x00e0 223133f9794SFeifei Xu #define mmIH_SCRATCH_BASE_IDX 0 224133f9794SFeifei Xu #define mmIH_CLIENT_CREDIT_ERROR 0x00e1 225133f9794SFeifei Xu #define mmIH_CLIENT_CREDIT_ERROR_BASE_IDX 0 226133f9794SFeifei Xu #define mmIH_GPU_IOV_VIOLATION_LOG 0x00e2 227133f9794SFeifei Xu #define mmIH_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 228133f9794SFeifei Xu #define mmIH_COOKIE_REC_VIOLATION_LOG 0x00e3 229133f9794SFeifei Xu #define mmIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0 230133f9794SFeifei Xu #define mmIH_CREDIT_STATUS 0x00e4 231133f9794SFeifei Xu #define mmIH_CREDIT_STATUS_BASE_IDX 0 232133f9794SFeifei Xu #define mmIH_MMHUB_ERROR 0x00e5 233133f9794SFeifei Xu #define mmIH_MMHUB_ERROR_BASE_IDX 0 234133f9794SFeifei Xu #define mmIH_REGISTER_LAST_PART2 0x00ff 235133f9794SFeifei Xu #define mmIH_REGISTER_LAST_PART2_BASE_IDX 0 236133f9794SFeifei Xu #define mmSEM_CLK_CTRL 0x0100 237133f9794SFeifei Xu #define mmSEM_CLK_CTRL_BASE_IDX 0 238133f9794SFeifei Xu #define mmSEM_UTC_CREDIT 0x0101 239133f9794SFeifei Xu #define mmSEM_UTC_CREDIT_BASE_IDX 0 240133f9794SFeifei Xu #define mmSEM_UTC_CONFIG 0x0102 241133f9794SFeifei Xu #define mmSEM_UTC_CONFIG_BASE_IDX 0 242133f9794SFeifei Xu #define mmSEM_UTCL2_TRAN_EN_LUT 0x0103 243133f9794SFeifei Xu #define mmSEM_UTCL2_TRAN_EN_LUT_BASE_IDX 0 244133f9794SFeifei Xu #define mmSEM_MCIF_CONFIG 0x0104 245133f9794SFeifei Xu #define mmSEM_MCIF_CONFIG_BASE_IDX 0 246133f9794SFeifei Xu #define mmSEM_PERFMON_CNTL 0x0105 247133f9794SFeifei Xu #define mmSEM_PERFMON_CNTL_BASE_IDX 0 248133f9794SFeifei Xu #define mmSEM_PERFCOUNTER0_RESULT 0x0106 249133f9794SFeifei Xu #define mmSEM_PERFCOUNTER0_RESULT_BASE_IDX 0 250133f9794SFeifei Xu #define mmSEM_PERFCOUNTER1_RESULT 0x0107 251133f9794SFeifei Xu #define mmSEM_PERFCOUNTER1_RESULT_BASE_IDX 0 252133f9794SFeifei Xu #define mmSEM_STATUS 0x0108 253133f9794SFeifei Xu #define mmSEM_STATUS_BASE_IDX 0 254133f9794SFeifei Xu #define mmSEM_MAILBOX_CLIENTCONFIG 0x0109 255133f9794SFeifei Xu #define mmSEM_MAILBOX_CLIENTCONFIG_BASE_IDX 0 256133f9794SFeifei Xu #define mmSEM_MAILBOX 0x010a 257133f9794SFeifei Xu #define mmSEM_MAILBOX_BASE_IDX 0 258133f9794SFeifei Xu #define mmSEM_MAILBOX_CONTROL 0x010b 259133f9794SFeifei Xu #define mmSEM_MAILBOX_CONTROL_BASE_IDX 0 260133f9794SFeifei Xu #define mmSEM_CHICKEN_BITS 0x010c 261133f9794SFeifei Xu #define mmSEM_CHICKEN_BITS_BASE_IDX 0 262133f9794SFeifei Xu #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0x010d 263133f9794SFeifei Xu #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_BASE_IDX 0 264133f9794SFeifei Xu #define mmSEM_GPU_IOV_VIOLATION_LOG 0x010e 265133f9794SFeifei Xu #define mmSEM_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 266133f9794SFeifei Xu #define mmSEM_OUTSTANDING_THRESHOLD 0x010f 267133f9794SFeifei Xu #define mmSEM_OUTSTANDING_THRESHOLD_BASE_IDX 0 268133f9794SFeifei Xu #define mmSEM_REGISTER_LAST_PART2 0x017f 269133f9794SFeifei Xu #define mmSEM_REGISTER_LAST_PART2_BASE_IDX 0 270133f9794SFeifei Xu #define mmIH_ACTIVE_FCN_ID 0x0180 271133f9794SFeifei Xu #define mmIH_ACTIVE_FCN_ID_BASE_IDX 0 272133f9794SFeifei Xu #define mmIH_VIRT_RESET_REQ 0x0181 273133f9794SFeifei Xu #define mmIH_VIRT_RESET_REQ_BASE_IDX 0 274133f9794SFeifei Xu #define mmIH_CLIENT_CFG 0x0184 275133f9794SFeifei Xu #define mmIH_CLIENT_CFG_BASE_IDX 0 276133f9794SFeifei Xu #define mmIH_CLIENT_CFG_INDEX 0x0188 277133f9794SFeifei Xu #define mmIH_CLIENT_CFG_INDEX_BASE_IDX 0 278133f9794SFeifei Xu #define mmIH_CLIENT_CFG_DATA 0x0189 279133f9794SFeifei Xu #define mmIH_CLIENT_CFG_DATA_BASE_IDX 0 280133f9794SFeifei Xu #define mmIH_CID_REMAP_INDEX 0x018a 281133f9794SFeifei Xu #define mmIH_CID_REMAP_INDEX_BASE_IDX 0 282133f9794SFeifei Xu #define mmIH_CID_REMAP_DATA 0x018b 283133f9794SFeifei Xu #define mmIH_CID_REMAP_DATA_BASE_IDX 0 284133f9794SFeifei Xu #define mmIH_CHICKEN 0x018c 285133f9794SFeifei Xu #define mmIH_CHICKEN_BASE_IDX 0 286133f9794SFeifei Xu #define mmIH_MMHUB_CNTL 0x018d 287133f9794SFeifei Xu #define mmIH_MMHUB_CNTL_BASE_IDX 0 288133f9794SFeifei Xu #define mmIH_INT_DROP_CNTL 0x018e 289133f9794SFeifei Xu #define mmIH_INT_DROP_CNTL_BASE_IDX 0 290133f9794SFeifei Xu #define mmIH_INT_DROP_MATCH_VALUE0 0x018f 291133f9794SFeifei Xu #define mmIH_INT_DROP_MATCH_VALUE0_BASE_IDX 0 292133f9794SFeifei Xu #define mmIH_INT_DROP_MATCH_VALUE1 0x0190 293133f9794SFeifei Xu #define mmIH_INT_DROP_MATCH_VALUE1_BASE_IDX 0 294133f9794SFeifei Xu #define mmIH_INT_DROP_MATCH_MASK0 0x0191 295133f9794SFeifei Xu #define mmIH_INT_DROP_MATCH_MASK0_BASE_IDX 0 296133f9794SFeifei Xu #define mmIH_INT_DROP_MATCH_MASK1 0x0192 297133f9794SFeifei Xu #define mmIH_INT_DROP_MATCH_MASK1_BASE_IDX 0 298133f9794SFeifei Xu #define mmIH_REGISTER_LAST_PART1 0x019f 299133f9794SFeifei Xu #define mmIH_REGISTER_LAST_PART1_BASE_IDX 0 300133f9794SFeifei Xu #define mmSEM_ACTIVE_FCN_ID 0x01a0 301133f9794SFeifei Xu #define mmSEM_ACTIVE_FCN_ID_BASE_IDX 0 302133f9794SFeifei Xu #define mmSEM_VIRT_RESET_REQ 0x01a1 303133f9794SFeifei Xu #define mmSEM_VIRT_RESET_REQ_BASE_IDX 0 304133f9794SFeifei Xu #define mmSEM_RESP_SDMA0 0x01a4 305133f9794SFeifei Xu #define mmSEM_RESP_SDMA0_BASE_IDX 0 306133f9794SFeifei Xu #define mmSEM_RESP_SDMA1 0x01a5 307133f9794SFeifei Xu #define mmSEM_RESP_SDMA1_BASE_IDX 0 308133f9794SFeifei Xu #define mmSEM_RESP_UVD 0x01a6 309133f9794SFeifei Xu #define mmSEM_RESP_UVD_BASE_IDX 0 310133f9794SFeifei Xu #define mmSEM_RESP_VCE_0 0x01a7 311133f9794SFeifei Xu #define mmSEM_RESP_VCE_0_BASE_IDX 0 312133f9794SFeifei Xu #define mmSEM_RESP_ACP 0x01a8 313133f9794SFeifei Xu #define mmSEM_RESP_ACP_BASE_IDX 0 314133f9794SFeifei Xu #define mmSEM_RESP_ISP 0x01a9 315133f9794SFeifei Xu #define mmSEM_RESP_ISP_BASE_IDX 0 316133f9794SFeifei Xu #define mmSEM_RESP_VCE_1 0x01aa 317133f9794SFeifei Xu #define mmSEM_RESP_VCE_1_BASE_IDX 0 318133f9794SFeifei Xu #define mmSEM_RESP_VP8 0x01ab 319133f9794SFeifei Xu #define mmSEM_RESP_VP8_BASE_IDX 0 320133f9794SFeifei Xu #define mmSEM_RESP_GC 0x01ac 321133f9794SFeifei Xu #define mmSEM_RESP_GC_BASE_IDX 0 322133f9794SFeifei Xu #define mmSEM_CID_REMAP_INDEX 0x01b0 323133f9794SFeifei Xu #define mmSEM_CID_REMAP_INDEX_BASE_IDX 0 324133f9794SFeifei Xu #define mmSEM_CID_REMAP_DATA 0x01b1 325133f9794SFeifei Xu #define mmSEM_CID_REMAP_DATA_BASE_IDX 0 326133f9794SFeifei Xu #define mmSEM_ATOMIC_OP_LUT 0x01b2 327133f9794SFeifei Xu #define mmSEM_ATOMIC_OP_LUT_BASE_IDX 0 328133f9794SFeifei Xu #define mmSEM_EDC_CONFIG 0x01b3 329133f9794SFeifei Xu #define mmSEM_EDC_CONFIG_BASE_IDX 0 330133f9794SFeifei Xu #define mmSEM_CHICKEN_BITS2 0x01b4 331133f9794SFeifei Xu #define mmSEM_CHICKEN_BITS2_BASE_IDX 0 332133f9794SFeifei Xu #define mmSEM_MMHUB_CNTL 0x01b5 333133f9794SFeifei Xu #define mmSEM_MMHUB_CNTL_BASE_IDX 0 334133f9794SFeifei Xu #define mmSEM_REGISTER_LAST_PART1 0x01bf 335133f9794SFeifei Xu #define mmSEM_REGISTER_LAST_PART1_BASE_IDX 0 336133f9794SFeifei Xu 337133f9794SFeifei Xu #endif 338