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Searched refs:mmIH_RB_RPTR (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dcik_ih.c89 WREG32(mmIH_RB_RPTR, 0); in cik_ih_disable_interrupts()
142 WREG32(mmIH_RB_RPTR, 0); in cik_ih_irq_init()
283 WREG32(mmIH_RB_RPTR, ih->rptr); in cik_ih_set_rptr()
H A Diceland_ih.c89 WREG32(mmIH_RB_RPTR, 0); in iceland_ih_disable_interrupts()
144 WREG32(mmIH_RB_RPTR, 0); in iceland_ih_irq_init()
273 WREG32(mmIH_RB_RPTR, ih->rptr); in iceland_ih_set_rptr()
H A Dcz_ih.c89 WREG32(mmIH_RB_RPTR, 0); in cz_ih_disable_interrupts()
144 WREG32(mmIH_RB_RPTR, 0); in cz_ih_irq_init()
274 WREG32(mmIH_RB_RPTR, ih->rptr); in cz_ih_set_rptr()
H A Dtonga_ih.c85 WREG32(mmIH_RB_RPTR, 0); in tonga_ih_disable_interrupts()
142 WREG32(mmIH_RB_RPTR, 0); in tonga_ih_irq_init()
282 WREG32(mmIH_RB_RPTR, ih->rptr); in tonga_ih_set_rptr()
H A Dvega10_ih.c57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega10_ih_init_register_offset()
H A Dvega20_ih.c65 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega20_ih_init_register_offset()
H A Dnavi10_ih.c59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in navi10_ih_init_register_offset()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_1_0_d.h232 #define mmIH_RB_RPTR 0x0F82 macro
H A Dosssys_4_0_1_offset.h126 #define mmIH_RB_RPTR … macro
H A Dosssys_4_0_offset.h126 #define mmIH_RB_RPTR … macro
H A Dosssys_5_0_0_offset.h126 #define mmIH_RB_RPTR … macro
H A Dosssys_4_2_0_offset.h128 #define mmIH_RB_RPTR … macro
H A Doss_2_4_d.h45 #define mmIH_RB_RPTR 0xe32 macro
H A Doss_3_0_1_d.h45 #define mmIH_RB_RPTR 0xe32 macro
H A Doss_3_0_d.h45 #define mmIH_RB_RPTR 0xe32 macro
H A Doss_2_0_d.h45 #define mmIH_RB_RPTR 0xf82 macro