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Searched refs:ccm (Results 1 – 25 of 196) sorted by relevance

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/openbmc/linux/drivers/clk/imx/
H A Dclk-imx25.c42 #define ccm(x) (ccm_base + (x)) macro
86 clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2); in __mx25_clocks_init()
87 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
108 clk[cko] = imx_clk_gate("cko", "cko_div", ccm(CCM_MCR), 30); in __mx25_clocks_init()
141 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); in __mx25_clocks_init()
143 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); in __mx25_clocks_init()
144 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); in __mx25_clocks_init()
148 clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23); in __mx25_clocks_init()
229 void __iomem *ccm; in mx25_clocks_init_dt() local
231 ccm = of_iomap(np, 0); in mx25_clocks_init_dt()
[all …]
H A Dclk-imx1.c28 static void __iomem *ccm __initdata;
29 #define CCM_CSCR (ccm + 0x0000)
30 #define CCM_MPCTL0 (ccm + 0x0004)
31 #define CCM_SPCTL0 (ccm + 0x000c)
32 #define CCM_PCDR (ccm + 0x0020)
33 #define SCM_GCCR (ccm + 0x0810)
37 ccm = of_iomap(np, 0); in mx1_clocks_init_dt()
38 BUG_ON(!ccm); in mx1_clocks_init_dt()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun9i.c23 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
42 &ccm->ahb0_cfg); in clock_init_safe()
45 &ccm->ahb1_cfg); in clock_init_safe()
48 &ccm->ahb2_cfg); in clock_init_safe()
51 &ccm->apb0_cfg); in clock_init_safe()
55 &ccm->gtbus_cfg); in clock_init_safe()
58 &ccm->cci400_cfg); in clock_init_safe()
75 setbits_le32(&ccm->apb1_gate, in clock_init_uart()
98 &ccm->pll1_c0_cfg); in clock_set_pll1()
124 &ccm->pll2_c1_cfg); in clock_set_pll2()
[all …]
H A Dclock_sun8i_a83t.c21 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
27 writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg); in clock_init_safe()
31 writel(0x0, &ccm->cci400_cfg); in clock_init_safe()
53 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
60 &ccm->apb2_div); in clock_init_uart()
63 setbits_le32(&ccm->apb2_gate, in clock_init_uart()
68 setbits_le32(&ccm->apb2_reset_cfg, in clock_init_uart()
85 &ccm->cpu_axi_cfg); in clock_set_pll1()
90 &ccm->pll1_c0_cfg); in clock_set_pll1()
95 &ccm->pll1_c1_cfg); in clock_set_pll1()
[all …]
H A Dclock_sun6i.c21 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
66 struct sunxi_ccm_reg * const ccm = in clock_init_sec() local
71 setbits_le32(&ccm->ccu_sec_switch, in clock_init_sec()
85 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
92 &ccm->apb2_div); in clock_init_uart()
95 setbits_le32(&ccm->apb2_gate, in clock_init_uart()
129 &ccm->cpu_axi_cfg); in clock_set_pll1()
144 &ccm->cpu_axi_cfg); in clock_set_pll1()
166 &ccm->pll3_cfg); in clock_set_pll3()
178 &ccm->pll3_cfg); in clock_set_pll3_factors()
[all …]
H A Dclock_sun50i_h6.c9 struct sunxi_ccm_reg *const ccm = in clock_init_safe() local
34 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
41 &ccm->apb2_cfg); in clock_init_uart()
44 setbits_le32(&ccm->uart_gate_reset, in clock_init_uart()
48 setbits_le32(&ccm->uart_gate_reset, in clock_init_uart()
55 struct sunxi_ccm_reg * const ccm = in clock_set_pll1() local
63 val = readl(&ccm->cpu_axi_cfg); in clock_set_pll1()
66 writel(val, &ccm->cpu_axi_cfg); in clock_set_pll1()
74 val = readl(&ccm->cpu_axi_cfg); in clock_set_pll1()
77 writel(val, &ccm->cpu_axi_cfg); in clock_set_pll1()
[all …]
H A Dclock_sun4i.c21 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
29 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
36 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
50 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
57 &ccm->apb1_clk_div_cfg); in clock_init_uart()
60 setbits_le32(&ccm->apb1_gate, in clock_init_uart()
66 struct sunxi_ccm_reg *const ccm = in clock_twi_onoff() local
71 setbits_le32(&ccm->apb1_gate, in clock_twi_onoff()
74 clrbits_le32(&ccm->apb1_gate, in clock_twi_onoff()
158 &ccm->cpu_ahb_apb0_cfg); in clock_set_pll1()
[all …]
/openbmc/linux/drivers/net/ethernet/netronome/nfp/
H A Dccm.c18 used_tags = ccm->tag_alloc_next - ccm->tag_alloc_last; in nfp_ccm_all_tags_busy()
34 WARN_ON(__test_and_set_bit(ccm->tag_alloc_next, ccm->tag_allocator)); in nfp_ccm_alloc_tag()
35 return ccm->tag_alloc_next++; in nfp_ccm_alloc_tag()
42 while (!test_bit(ccm->tag_alloc_last, ccm->tag_allocator) && in nfp_ccm_free_tag()
43 ccm->tag_alloc_last != ccm->tag_alloc_next) in nfp_ccm_free_tag()
44 ccm->tag_alloc_last++; in nfp_ccm_free_tag()
55 nfp_ccm_free_tag(ccm, tag); in __nfp_ccm_reply()
70 skb = __nfp_ccm_reply(ccm, tag); in nfp_ccm_reply()
84 nfp_ccm_free_tag(ccm, tag); in nfp_ccm_reply_drop_tag()
136 tag = nfp_ccm_alloc_tag(ccm); in nfp_ccm_communicate()
[all …]
/openbmc/u-boot/arch/arm/cpu/arm1136/mx35/
H A Dgeneric.c133 struct ccm_regs *ccm = in get_mcu_main_clk() local
143 struct ccm_regs *ccm = in get_ipg_clk() local
145 u32 pdr0 = readl(&ccm->pdr0); in get_ipg_clk()
153 struct ccm_regs *ccm = in get_ipg_per_clk() local
155 u32 pdr0 = readl(&ccm->pdr0); in get_ipg_per_clk()
174 struct ccm_regs *ccm = in imx_get_uartclk() local
192 struct ccm_regs *ccm = in mxc_get_main_clock() local
195 u32 reg = readl(&ccm->pdr0); in mxc_get_main_clock()
253 struct ccm_regs *ccm = in mxc_get_peri_clock() local
401 struct ccm_regs *ccm = in get_reset_cause() local
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx25/
H A Dgeneric.c57 return imx_decode_pll(readl(&ccm->mpctl), fref); in imx_get_mpllclk()
65 return imx_decode_pll(readl(&ccm->upctl), fref); in imx_get_upllclk()
71 ulong cctl = readl(&ccm->cctl); in imx_get_armclk()
87 ulong cctl = readl(&ccm->cctl); in imx_get_ahbclk()
109 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]); in imx_get_perclk()
128 setbits_le32(&ccm->mcr, 1 << clk); in imx_set_perclk()
130 clrbits_le32(&ccm->mcr, 1 << clk); in imx_set_perclk()
183 struct ccm_regs *ccm = in get_reset_cause() local
186 u32 cause = readl(&ccm->rcsr) & 0x0f; in get_reset_cause()
227 val = readl(&ccm->cgr0); in cpu_eth_init()
[all …]
/openbmc/qemu/hw/misc/
H A Dimx6_ccm.c388 s->ccm[CCM_CCR] = 0x040116FF; in imx6_ccm_reset()
389 s->ccm[CCM_CCDR] = 0x00000000; in imx6_ccm_reset()
390 s->ccm[CCM_CSR] = 0x00000010; in imx6_ccm_reset()
391 s->ccm[CCM_CCSR] = 0x00000100; in imx6_ccm_reset()
392 s->ccm[CCM_CACRR] = 0x00000000; in imx6_ccm_reset()
393 s->ccm[CCM_CBCDR] = 0x00018D40; in imx6_ccm_reset()
405 s->ccm[CCM_CTOR] = 0x00000000; in imx6_ccm_reset()
407 s->ccm[CCM_CISR] = 0x00000000; in imx6_ccm_reset()
408 s->ccm[CCM_CIMR] = 0xFFFFFFFF; in imx6_ccm_reset()
410 s->ccm[CCM_CGPR] = 0x0000FE62; in imx6_ccm_reset()
[all …]
H A Dimx6ul_ccm.c542 s->ccm[CCM_CCR] = 0x0401167F; in imx6ul_ccm_reset()
543 s->ccm[CCM_CCDR] = 0x00000000; in imx6ul_ccm_reset()
544 s->ccm[CCM_CSR] = 0x00000010; in imx6ul_ccm_reset()
545 s->ccm[CCM_CCSR] = 0x00000100; in imx6ul_ccm_reset()
546 s->ccm[CCM_CACRR] = 0x00000000; in imx6ul_ccm_reset()
559 s->ccm[CCM_CTOR] = 0x00000000; in imx6ul_ccm_reset()
561 s->ccm[CCM_CISR] = 0x00000000; in imx6ul_ccm_reset()
562 s->ccm[CCM_CIMR] = 0xFFFFFFFF; in imx6ul_ccm_reset()
564 s->ccm[CCM_CGPR] = 0x0000FE62; in imx6ul_ccm_reset()
632 value = s->ccm[index]; in imx6ul_ccm_read()
[all …]
/openbmc/u-boot/board/aristainetos/
H A Daristainetos-v2.c442 reg = readl(&ccm->cs2cdr); in enable_lvds()
447 writel(reg, &ccm->cs2cdr); in enable_lvds()
449 reg = readl(&ccm->cscmr2); in enable_lvds()
451 writel(reg, &ccm->cscmr2); in enable_lvds()
453 reg = readl(&ccm->chsccdr); in enable_lvds()
496 reg = readl(&ccm->cs2cdr); in enable_spi_display()
501 writel(reg, &ccm->cs2cdr); in enable_spi_display()
530 reg = readl(&ccm->cs2cdr); in enable_spi_display()
535 writel(reg, &ccm->cs2cdr); in enable_spi_display()
537 reg = readl(&ccm->cscmr2); in enable_spi_display()
[all …]
/openbmc/u-boot/board/ccv/xpress/
H A Dspl.c81 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
83 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
84 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
85 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
86 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
87 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
88 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
89 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
90 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
/openbmc/u-boot/board/CarMediaLab/flea3/
H A Dflea3.c134 struct ccm_regs *ccm = in board_early_init_f() local
142 writel(CCM_CCMR_CONFIG, &ccm->ccmr); in board_early_init_f()
144 writel(CCM_MPLL_532_HZ, &ccm->mpctl); in board_early_init_f()
145 writel(CCM_PPLL_300_HZ, &ccm->ppctl); in board_early_init_f()
148 writel(0x00001000, &ccm->pdr0); in board_early_init_f()
154 writel(readl(&ccm->cgr0) | in board_early_init_f()
158 &ccm->cgr0); in board_early_init_f()
160 writel(readl(&ccm->cgr1) | in board_early_init_f()
168 &ccm->cgr1); in board_early_init_f()
171 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); in board_early_init_f()
/openbmc/u-boot/board/freescale/vf610twr/
H A Dvf610twr.c273 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
275 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
277 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
282 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
284 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
287 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
289 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
291 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
301 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, in clock_init()
303 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, in clock_init()
[all …]
/openbmc/u-boot/board/barco/platinum/
H A Dplatinum.h66 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
68 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
69 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
70 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
71 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
72 writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ in ccgr_init()
73 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
74 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
/openbmc/u-boot/board/toradex/colibri_vf/
H A Dcolibri_vf.c382 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
387 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
389 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
393 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
395 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
398 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
400 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
402 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
404 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, in clock_init()
435 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, in clock_init()
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf5445x/
H A Dspeed.c31 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_enter_limp() local
45 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); in clock_enter_limp()
49 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_enter_limp()
58 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_exit_limp() local
62 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_exit_limp()
72 ccm_t *ccm = (ccm_t *)MMAP_CCM; in setup_5441x_clocks() local
76 bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14; in setup_5441x_clocks()
104 setbits_be16(&ccm->misccr2, 0x02); in setup_5441x_clocks()
117 if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */ in setup_5441x_clocks()
131 ccm_t *ccm = (ccm_t *)MMAP_CCM; in setup_5445x_clocks() local
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/vf610/
H A Dgeneric.c26 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in enable_ocotp_clk() local
29 reg = readl(&ccm->ccgr6); in enable_ocotp_clk()
34 writel(reg, &ccm->ccgr6); in enable_ocotp_clk()
40 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in get_mcu_main_clk() local
45 ccm_ccsr = readl(&ccm->ccsr); in get_mcu_main_clk()
49 ccm_cacrr = readl(&ccm->cacrr); in get_mcu_main_clk()
107 ccm_cacrr = readl(&ccm->cacrr); in get_bus_clk()
121 ccm_cacrr = readl(&ccm->cacrr); in get_ipg_clk()
141 ccm_cscmr1 = readl(&ccm->cscmr1); in get_sdhc_clk()
145 ccm_cscdr2 = readl(&ccm->cscdr2); in get_sdhc_clk()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dlitesom.c149 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
151 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
152 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
153 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
154 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
155 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
156 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
157 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
158 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
/openbmc/u-boot/board/phytec/pcl063/
H A Dspl.c86 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
88 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
89 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
90 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
91 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
92 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
93 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
94 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
/openbmc/u-boot/board/engicam/common/
H A Dspl.c371 writel(0x00003F3F, &ccm->CCGR0); in ccgr_init()
372 writel(0x0030FC00, &ccm->CCGR1); in ccgr_init()
373 writel(0x000FC000, &ccm->CCGR2); in ccgr_init()
374 writel(0x3F300000, &ccm->CCGR3); in ccgr_init()
375 writel(0xFF00F300, &ccm->CCGR4); in ccgr_init()
376 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
377 writel(0x000003CC, &ccm->CCGR6); in ccgr_init()
379 writel(0x00c03f3f, &ccm->CCGR0); in ccgr_init()
380 writel(0xfcffff00, &ccm->CCGR1); in ccgr_init()
381 writel(0x0cffffcc, &ccm->CCGR2); in ccgr_init()
[all …]
/openbmc/u-boot/board/tbs/tbs2910/
H A Dtbs2910.c312 reg = readl(&ccm->analog_pll_video); in setup_display()
314 writel(reg, &ccm->analog_pll_video); in setup_display()
320 writel(reg, &ccm->analog_pll_video); in setup_display()
326 writel(reg, &ccm->analog_pll_video); in setup_display()
334 reg = readl(&ccm->analog_pll_video); in setup_display()
340 reg = readl(&ccm->CCGR3); in setup_display()
342 writel(reg, &ccm->CCGR3); in setup_display()
345 reg = readl(&ccm->chsccdr); in setup_display()
352 writel(reg, &ccm->chsccdr); in setup_display()
355 reg = readl(&ccm->CCGR3); in setup_display()
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf532x/
H A Dspeed.c52 ccm_t *ccm = (ccm_t *)(MMAP_CCM); in get_sys_clock() local
57 if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) { in get_sys_clock()
58 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); in get_sys_clock()
90 ccm_t *ccm = (ccm_t *)(MMAP_CCM); in clock_limp() local
100 temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF)); in clock_limp()
103 out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); in clock_limp()
105 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_limp()
113 ccm_t *ccm = (ccm_t *)(MMAP_CCM); in clock_exit_limp() local
117 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_exit_limp()
120 while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK)) in clock_exit_limp()

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