Lines Matching refs:ccm
9 struct sunxi_ccm_reg *const ccm = in clock_init_safe() local
13 writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
14 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK)) in clock_init_safe()
17 clrsetbits_le32(&ccm->cpu_axi_cfg, CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK, in clock_init_safe()
20 writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg); in clock_init_safe()
21 writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg); in clock_init_safe()
22 writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg); in clock_init_safe()
28 writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg); in clock_init_safe()
34 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
41 &ccm->apb2_cfg); in clock_init_uart()
44 setbits_le32(&ccm->uart_gate_reset, in clock_init_uart()
48 setbits_le32(&ccm->uart_gate_reset, in clock_init_uart()
55 struct sunxi_ccm_reg * const ccm = in clock_set_pll1() local
63 val = readl(&ccm->cpu_axi_cfg); in clock_set_pll1()
66 writel(val, &ccm->cpu_axi_cfg); in clock_set_pll1()
70 CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg); in clock_set_pll1()
71 while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {} in clock_set_pll1()
74 val = readl(&ccm->cpu_axi_cfg); in clock_set_pll1()
77 writel(val, &ccm->cpu_axi_cfg); in clock_set_pll1()
83 struct sunxi_ccm_reg *const ccm = in clock_get_pll6() local
86 uint32_t rval = readl(&ccm->pll6_cfg); in clock_get_pll6()