21 	struct sunxi_ccm_reg * const ccm =  in clock_init_safe()  local
26 	writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg);  in clock_init_safe()
27 	writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg);  in clock_init_safe()
28 	while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {}  in clock_init_safe()
31 	writel(0x0, &ccm->cci400_cfg);  in clock_init_safe()
33 	writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg);  in clock_init_safe()
37 	clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK,  in clock_init_safe()
39 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);  in clock_init_safe()
40 	while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {}  in clock_init_safe()
42 	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);  in clock_init_safe()
43 	writel(CCM_MBUS_RESET_RESET, &ccm->mbus_reset);  in clock_init_safe()
44 	writel(MBUS_CLK_DEFAULT, &ccm->mbus_clk_cfg);  in clock_init_safe()
53 	struct sunxi_ccm_reg *const ccm =  in clock_init_uart()  local
60 	       &ccm->apb2_div);  in clock_init_uart()
63 	setbits_le32(&ccm->apb2_gate,  in clock_init_uart()
68 	setbits_le32(&ccm->apb2_reset_cfg,  in clock_init_uart()
76 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll1()  local
85 	       &ccm->cpu_axi_cfg);  in clock_set_pll1()
90 		&ccm->pll1_c0_cfg);  in clock_set_pll1()
91 	while (!(readl(&ccm->pll_stable_status) & 0x01)) {}  in clock_set_pll1()
95 		&ccm->pll1_c1_cfg);  in clock_set_pll1()
96 	while (!(readl(&ccm->pll_stable_status) & 0x02)) {}  in clock_set_pll1()
103 	       &ccm->cpu_axi_cfg);  in clock_set_pll1()
109 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll5()  local
117 			div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg);  in clock_set_pll5()
125 	struct sunxi_ccm_reg *const ccm =  in clock_get_pll6()  local
128 	uint32_t rval = readl(&ccm->pll6_cfg);  in clock_get_pll6()