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Searched refs:XCHAL_RESET_VECTOR1_PADDR (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h319 #define XCHAL_RESET_VECTOR1_PADDR 0x00000500 macro
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h375 #define XCHAL_RESET_VECTOR1_PADDR 0xFFFF1000 macro
/openbmc/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h399 #define XCHAL_RESET_VECTOR1_PADDR 0x40000080 macro
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h340 #define XCHAL_RESET_VECTOR1_PADDR 0x00000500 macro
/openbmc/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h341 #define XCHAL_RESET_VECTOR1_PADDR 0x00000500 macro
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h391 #define XCHAL_RESET_VECTOR1_PADDR 0x00000500 macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h339 #define XCHAL_RESET_VECTOR1_PADDR 0x00000500 macro
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h390 #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h369 #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 macro
/openbmc/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h391 #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 macro
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h431 #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 macro
/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h495 #define XCHAL_RESET_VECTOR1_PADDR 0x40000400 macro
/openbmc/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h474 #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 macro
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h473 #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h473 #define XCHAL_RESET_VECTOR1_PADDR 0x40000400 macro
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h474 #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h509 #define XCHAL_RESET_VECTOR1_PADDR 0x40000400 macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h530 #define XCHAL_RESET_VECTOR1_PADDR 0x40000400 macro
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h612 #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 macro