123c2b932SScott Telford /* 223c2b932SScott Telford * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 323c2b932SScott Telford * processor CORE configuration 423c2b932SScott Telford * 523c2b932SScott Telford * See <xtensa/config/core.h>, which includes this file, for more details. 623c2b932SScott Telford */ 723c2b932SScott Telford 823c2b932SScott Telford /* Xtensa processor core configuration information. 923c2b932SScott Telford 1023c2b932SScott Telford Copyright (c) 1999-2015 Tensilica Inc. 1123c2b932SScott Telford 1223c2b932SScott Telford Permission is hereby granted, free of charge, to any person obtaining 1323c2b932SScott Telford a copy of this software and associated documentation files (the 1423c2b932SScott Telford "Software"), to deal in the Software without restriction, including 1523c2b932SScott Telford without limitation the rights to use, copy, modify, merge, publish, 1623c2b932SScott Telford distribute, sublicense, and/or sell copies of the Software, and to 1723c2b932SScott Telford permit persons to whom the Software is furnished to do so, subject to 1823c2b932SScott Telford the following conditions: 1923c2b932SScott Telford 2023c2b932SScott Telford The above copyright notice and this permission notice shall be included 2123c2b932SScott Telford in all copies or substantial portions of the Software. 2223c2b932SScott Telford 2323c2b932SScott Telford THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 2423c2b932SScott Telford EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 2523c2b932SScott Telford MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 2623c2b932SScott Telford IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 2723c2b932SScott Telford CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 2823c2b932SScott Telford TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 2923c2b932SScott Telford SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 3023c2b932SScott Telford 3123c2b932SScott Telford #ifndef _XTENSA_CORE_CONFIGURATION_H 3223c2b932SScott Telford #define _XTENSA_CORE_CONFIGURATION_H 3323c2b932SScott Telford 3423c2b932SScott Telford 3523c2b932SScott Telford /**************************************************************************** 3623c2b932SScott Telford Parameters Useful for Any Code, USER or PRIVILEGED 3723c2b932SScott Telford ****************************************************************************/ 3823c2b932SScott Telford 3923c2b932SScott Telford /* 4023c2b932SScott Telford * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is 4123c2b932SScott Telford * configured, and a value of 0 otherwise. These macros are always defined. 4223c2b932SScott Telford */ 4323c2b932SScott Telford 4423c2b932SScott Telford 4523c2b932SScott Telford /*---------------------------------------------------------------------- 4623c2b932SScott Telford ISA 4723c2b932SScott Telford ----------------------------------------------------------------------*/ 4823c2b932SScott Telford 4923c2b932SScott Telford #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 5023c2b932SScott Telford #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ 5123c2b932SScott Telford #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ 5223c2b932SScott Telford #define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ 5323c2b932SScott Telford #define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ 5423c2b932SScott Telford #define XCHAL_HAVE_DEBUG 1 /* debug option */ 5523c2b932SScott Telford #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 5623c2b932SScott Telford #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 5723c2b932SScott Telford #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ 5823c2b932SScott Telford #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ 5923c2b932SScott Telford #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ 6023c2b932SScott Telford #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ 6123c2b932SScott Telford #define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ 6223c2b932SScott Telford #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ 6323c2b932SScott Telford #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ 6423c2b932SScott Telford #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ 6523c2b932SScott Telford #define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ 6623c2b932SScott Telford #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ 6723c2b932SScott Telford #define XCHAL_HAVE_L32R 1 /* L32R instruction */ 6823c2b932SScott Telford #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ 6923c2b932SScott Telford #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ 7023c2b932SScott Telford #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ 7123c2b932SScott Telford #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ 7223c2b932SScott Telford #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ 7323c2b932SScott Telford #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ 7423c2b932SScott Telford #define XCHAL_HAVE_ABS 1 /* ABS instruction */ 7523c2b932SScott Telford /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ 7623c2b932SScott Telford /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ 7723c2b932SScott Telford #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ 7823c2b932SScott Telford #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ 7923c2b932SScott Telford #define XCHAL_HAVE_SPECULATION 0 /* speculation */ 8023c2b932SScott Telford #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ 8123c2b932SScott Telford #define XCHAL_NUM_CONTEXTS 1 /* */ 8223c2b932SScott Telford #define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ 8323c2b932SScott Telford #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ 8423c2b932SScott Telford #define XCHAL_HAVE_PRID 1 /* processor ID register */ 8523c2b932SScott Telford #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ 8623c2b932SScott Telford #define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ 8723c2b932SScott Telford #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ 8823c2b932SScott Telford #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ 8923c2b932SScott Telford #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ 9023c2b932SScott Telford #define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ 9123c2b932SScott Telford #define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ 9223c2b932SScott Telford #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ 9323c2b932SScott Telford #define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ 9423c2b932SScott Telford #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ 9523c2b932SScott Telford #define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ 9623c2b932SScott Telford #define XCHAL_HAVE_MAC16 1 /* MAC16 package */ 9723c2b932SScott Telford 9823c2b932SScott Telford #define XCHAL_HAVE_FUSION 0 /* Fusion*/ 9923c2b932SScott Telford #define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ 10023c2b932SScott Telford #define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ 10123c2b932SScott Telford #define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ 10223c2b932SScott Telford #define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ 10323c2b932SScott Telford #define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ 10423c2b932SScott Telford #define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ 10523c2b932SScott Telford #define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ 10623c2b932SScott Telford #define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ 10723c2b932SScott Telford #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ 10823c2b932SScott Telford #define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ 10923c2b932SScott Telford #define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ 11023c2b932SScott Telford #define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ 11123c2b932SScott Telford #define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ 11223c2b932SScott Telford #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ 11323c2b932SScott Telford #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ 11423c2b932SScott Telford #define XCHAL_HAVE_HIFI_MINI 0 11523c2b932SScott Telford 11623c2b932SScott Telford 11723c2b932SScott Telford #define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ 11823c2b932SScott Telford #define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ 11923c2b932SScott Telford #define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ 12023c2b932SScott Telford #define XCHAL_HAVE_FP 0 /* single prec floating point */ 12123c2b932SScott Telford #define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ 12223c2b932SScott Telford #define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ 12323c2b932SScott Telford #define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ 12423c2b932SScott Telford #define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ 12523c2b932SScott Telford #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ 12623c2b932SScott Telford #define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ 12723c2b932SScott Telford #define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ 12823c2b932SScott Telford #define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ 12923c2b932SScott Telford #define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ 13023c2b932SScott Telford #define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ 13123c2b932SScott Telford #define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ 13223c2b932SScott Telford 13323c2b932SScott Telford #define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ 13423c2b932SScott Telford #define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ 13523c2b932SScott Telford #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ 13623c2b932SScott Telford #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ 13723c2b932SScott Telford #define XCHAL_HAVE_PDX4 0 /* PDX4 */ 13823c2b932SScott Telford #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ 13923c2b932SScott Telford #define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ 14023c2b932SScott Telford #define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ 14123c2b932SScott Telford #define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ 14223c2b932SScott Telford #define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ 14323c2b932SScott Telford #define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ 14423c2b932SScott Telford #define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ 14523c2b932SScott Telford #define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ 14623c2b932SScott Telford #define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ 14723c2b932SScott Telford #define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ 14823c2b932SScott Telford #define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ 14923c2b932SScott Telford #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ 15023c2b932SScott Telford #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ 15123c2b932SScott Telford #define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ 15223c2b932SScott Telford #define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ 15323c2b932SScott Telford #define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ 15423c2b932SScott Telford 15523c2b932SScott Telford 15623c2b932SScott Telford /*---------------------------------------------------------------------- 15723c2b932SScott Telford MISC 15823c2b932SScott Telford ----------------------------------------------------------------------*/ 15923c2b932SScott Telford 16023c2b932SScott Telford #define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ 16123c2b932SScott Telford #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ 16223c2b932SScott Telford #define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ 16323c2b932SScott Telford #define XCHAL_DATA_WIDTH 16 /* data width in bytes */ 16423c2b932SScott Telford #define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay 16523c2b932SScott Telford (1 = 5-stage, 2 = 7-stage) */ 16623c2b932SScott Telford #define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */ 16723c2b932SScott Telford #define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct. unit clock gating */ 16823c2b932SScott Telford /* In T1050, applies to selected core load and store instructions (see ISA): */ 16923c2b932SScott Telford #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ 17023c2b932SScott Telford #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ 17123c2b932SScott Telford #define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ 17223c2b932SScott Telford #define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ 17323c2b932SScott Telford 17423c2b932SScott Telford #define XCHAL_SW_VERSION 1100002 /* sw version of this header */ 17523c2b932SScott Telford 17623c2b932SScott Telford #define XCHAL_CORE_ID "xt_lnx" /* alphanum core name 17723c2b932SScott Telford (CoreID) set in the Xtensa 17823c2b932SScott Telford Processor Generator */ 17923c2b932SScott Telford 18023c2b932SScott Telford #define XCHAL_BUILD_UNIQUE_ID 0x00057D54 /* 22-bit sw build ID */ 18123c2b932SScott Telford 18223c2b932SScott Telford /* 18323c2b932SScott Telford * These definitions describe the hardware targeted by this software. 18423c2b932SScott Telford */ 18523c2b932SScott Telford #define XCHAL_HW_CONFIGID0 0xC1B3FFFE /* ConfigID hi 32 bits*/ 18623c2b932SScott Telford #define XCHAL_HW_CONFIGID1 0x1C857D54 /* ConfigID lo 32 bits*/ 18723c2b932SScott Telford #define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */ 18823c2b932SScott Telford #define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ 18923c2b932SScott Telford #define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */ 19023c2b932SScott Telford #define XCHAL_HW_VERSION 260002 /* major*100+minor */ 19123c2b932SScott Telford #define XCHAL_HW_REL_LX6 1 19223c2b932SScott Telford #define XCHAL_HW_REL_LX6_0 1 19323c2b932SScott Telford #define XCHAL_HW_REL_LX6_0_2 1 19423c2b932SScott Telford #define XCHAL_HW_CONFIGID_RELIABLE 1 19523c2b932SScott Telford /* If software targets a *range* of hardware versions, these are the bounds: */ 19623c2b932SScott Telford #define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ 19723c2b932SScott Telford #define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */ 19823c2b932SScott Telford #define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */ 19923c2b932SScott Telford #define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ 20023c2b932SScott Telford #define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */ 20123c2b932SScott Telford #define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */ 20223c2b932SScott Telford 20323c2b932SScott Telford 20423c2b932SScott Telford /*---------------------------------------------------------------------- 20523c2b932SScott Telford CACHE 20623c2b932SScott Telford ----------------------------------------------------------------------*/ 20723c2b932SScott Telford 20823c2b932SScott Telford #define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ 20923c2b932SScott Telford #define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ 21023c2b932SScott Telford #define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */ 21123c2b932SScott Telford #define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */ 21223c2b932SScott Telford 21323c2b932SScott Telford #define XCHAL_ICACHE_SIZE 65536 /* I-cache size in bytes or 0 */ 21423c2b932SScott Telford #define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */ 21523c2b932SScott Telford 21623c2b932SScott Telford #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ 21723c2b932SScott Telford #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ 21823c2b932SScott Telford 21923c2b932SScott Telford #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ 22023c2b932SScott Telford #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ 22123c2b932SScott Telford #define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ 22223c2b932SScott Telford #define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ 22323c2b932SScott Telford #define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ 22423c2b932SScott Telford #define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ 22523c2b932SScott Telford #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ 22623c2b932SScott Telford #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ 22723c2b932SScott Telford #define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ 22823c2b932SScott Telford #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ 22923c2b932SScott Telford 23023c2b932SScott Telford 23123c2b932SScott Telford 23223c2b932SScott Telford 23323c2b932SScott Telford /**************************************************************************** 23423c2b932SScott Telford Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 23523c2b932SScott Telford ****************************************************************************/ 23623c2b932SScott Telford 23723c2b932SScott Telford 23823c2b932SScott Telford #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 23923c2b932SScott Telford 24023c2b932SScott Telford /*---------------------------------------------------------------------- 24123c2b932SScott Telford CACHE 24223c2b932SScott Telford ----------------------------------------------------------------------*/ 24323c2b932SScott Telford 24423c2b932SScott Telford #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ 24523c2b932SScott Telford 24623c2b932SScott Telford /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ 24723c2b932SScott Telford 24823c2b932SScott Telford /* Number of cache sets in log2(lines per way): */ 24923c2b932SScott Telford #define XCHAL_ICACHE_SETWIDTH 8 25023c2b932SScott Telford #define XCHAL_DCACHE_SETWIDTH 6 25123c2b932SScott Telford 25223c2b932SScott Telford /* Cache set associativity (number of ways): */ 25323c2b932SScott Telford #define XCHAL_ICACHE_WAYS 4 25423c2b932SScott Telford #define XCHAL_DCACHE_WAYS 4 25523c2b932SScott Telford 25623c2b932SScott Telford /* Cache features: */ 25723c2b932SScott Telford #define XCHAL_ICACHE_LINE_LOCKABLE 1 25823c2b932SScott Telford #define XCHAL_DCACHE_LINE_LOCKABLE 1 25923c2b932SScott Telford #define XCHAL_ICACHE_ECC_PARITY 0 26023c2b932SScott Telford #define XCHAL_DCACHE_ECC_PARITY 0 26123c2b932SScott Telford 26223c2b932SScott Telford /* Cache access size in bytes (affects operation of SICW instruction): */ 26323c2b932SScott Telford #define XCHAL_ICACHE_ACCESS_SIZE 16 26423c2b932SScott Telford #define XCHAL_DCACHE_ACCESS_SIZE 16 26523c2b932SScott Telford 26623c2b932SScott Telford #define XCHAL_DCACHE_BANKS 1 /* number of banks */ 26723c2b932SScott Telford 26823c2b932SScott Telford /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ 26923c2b932SScott Telford #define XCHAL_CA_BITS 4 27023c2b932SScott Telford 27123c2b932SScott Telford /* Whether MEMCTL register has anything useful */ 27223c2b932SScott Telford #define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \ 27323c2b932SScott Telford XCHAL_DCACHE_IS_COHERENT || \ 27423c2b932SScott Telford XCHAL_HAVE_ICACHE_DYN_WAYS || \ 27523c2b932SScott Telford XCHAL_HAVE_DCACHE_DYN_WAYS) && \ 27623c2b932SScott Telford (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0)) 27723c2b932SScott Telford 27823c2b932SScott Telford 27923c2b932SScott Telford /*---------------------------------------------------------------------- 28023c2b932SScott Telford INTERNAL I/D RAM/ROMs and XLMI 28123c2b932SScott Telford ----------------------------------------------------------------------*/ 28223c2b932SScott Telford 28323c2b932SScott Telford #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ 28423c2b932SScott Telford #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ 28523c2b932SScott Telford #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ 28623c2b932SScott Telford #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ 28723c2b932SScott Telford #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ 28823c2b932SScott Telford #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ 28923c2b932SScott Telford 29023c2b932SScott Telford #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ 29123c2b932SScott Telford 29223c2b932SScott Telford 29323c2b932SScott Telford /*---------------------------------------------------------------------- 29423c2b932SScott Telford INTERRUPTS and TIMERS 29523c2b932SScott Telford ----------------------------------------------------------------------*/ 29623c2b932SScott Telford 29723c2b932SScott Telford #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ 29823c2b932SScott Telford #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ 29923c2b932SScott Telford #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ 30023c2b932SScott Telford #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ 30123c2b932SScott Telford #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ 30223c2b932SScott Telford #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ 30323c2b932SScott Telford #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ 30423c2b932SScott Telford #define XCHAL_NUM_EXTINTERRUPTS 16 /* num of external interrupts */ 30523c2b932SScott Telford #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels 30623c2b932SScott Telford (not including level zero) */ 30723c2b932SScott Telford #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ 30823c2b932SScott Telford /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ 30923c2b932SScott Telford 31023c2b932SScott Telford /* Masks of interrupts at each interrupt level: */ 31123c2b932SScott Telford #define XCHAL_INTLEVEL1_MASK 0x001F00BF 31223c2b932SScott Telford #define XCHAL_INTLEVEL2_MASK 0x00001140 31323c2b932SScott Telford #define XCHAL_INTLEVEL3_MASK 0x00200E00 31423c2b932SScott Telford #define XCHAL_INTLEVEL4_MASK 0x00008000 31523c2b932SScott Telford #define XCHAL_INTLEVEL5_MASK 0x00002000 31623c2b932SScott Telford #define XCHAL_INTLEVEL6_MASK 0x00000000 31723c2b932SScott Telford #define XCHAL_INTLEVEL7_MASK 0x00004000 31823c2b932SScott Telford 31923c2b932SScott Telford /* Masks of interrupts at each range 1..n of interrupt levels: */ 32023c2b932SScott Telford #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F00BF 32123c2b932SScott Telford #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F11FF 32223c2b932SScott Telford #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F1FFF 32323c2b932SScott Telford #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF 32423c2b932SScott Telford #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF 32523c2b932SScott Telford #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF 32623c2b932SScott Telford #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF 32723c2b932SScott Telford 32823c2b932SScott Telford /* Level of each interrupt: */ 32923c2b932SScott Telford #define XCHAL_INT0_LEVEL 1 33023c2b932SScott Telford #define XCHAL_INT1_LEVEL 1 33123c2b932SScott Telford #define XCHAL_INT2_LEVEL 1 33223c2b932SScott Telford #define XCHAL_INT3_LEVEL 1 33323c2b932SScott Telford #define XCHAL_INT4_LEVEL 1 33423c2b932SScott Telford #define XCHAL_INT5_LEVEL 1 33523c2b932SScott Telford #define XCHAL_INT6_LEVEL 2 33623c2b932SScott Telford #define XCHAL_INT7_LEVEL 1 33723c2b932SScott Telford #define XCHAL_INT8_LEVEL 2 33823c2b932SScott Telford #define XCHAL_INT9_LEVEL 3 33923c2b932SScott Telford #define XCHAL_INT10_LEVEL 3 34023c2b932SScott Telford #define XCHAL_INT11_LEVEL 3 34123c2b932SScott Telford #define XCHAL_INT12_LEVEL 2 34223c2b932SScott Telford #define XCHAL_INT13_LEVEL 5 34323c2b932SScott Telford #define XCHAL_INT14_LEVEL 7 34423c2b932SScott Telford #define XCHAL_INT15_LEVEL 4 34523c2b932SScott Telford #define XCHAL_INT16_LEVEL 1 34623c2b932SScott Telford #define XCHAL_INT17_LEVEL 1 34723c2b932SScott Telford #define XCHAL_INT18_LEVEL 1 34823c2b932SScott Telford #define XCHAL_INT19_LEVEL 1 34923c2b932SScott Telford #define XCHAL_INT20_LEVEL 1 35023c2b932SScott Telford #define XCHAL_INT21_LEVEL 3 35123c2b932SScott Telford #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ 35223c2b932SScott Telford #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ 35323c2b932SScott Telford #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with 35423c2b932SScott Telford EXCSAVE/EPS/EPC_n, RFI n) */ 35523c2b932SScott Telford 35623c2b932SScott Telford /* Type of each interrupt: */ 35723c2b932SScott Telford #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 35823c2b932SScott Telford #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 35923c2b932SScott Telford #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 36023c2b932SScott Telford #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 36123c2b932SScott Telford #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 36223c2b932SScott Telford #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 36323c2b932SScott Telford #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER 36423c2b932SScott Telford #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE 36523c2b932SScott Telford #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 36623c2b932SScott Telford #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 36723c2b932SScott Telford #define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER 36823c2b932SScott Telford #define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE 36923c2b932SScott Telford #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_EDGE 37023c2b932SScott Telford #define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER 37123c2b932SScott Telford #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI 37223c2b932SScott Telford #define XCHAL_INT15_TYPE XTHAL_INTTYPE_PROFILING 37323c2b932SScott Telford #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE 37423c2b932SScott Telford #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE 37523c2b932SScott Telford #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE 37623c2b932SScott Telford #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE 37723c2b932SScott Telford #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE 37823c2b932SScott Telford #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE 37923c2b932SScott Telford 38023c2b932SScott Telford /* Masks of interrupts for each type of interrupt: */ 38123c2b932SScott Telford #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 38223c2b932SScott Telford #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 38323c2b932SScott Telford #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F1000 38423c2b932SScott Telford #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000033F 38523c2b932SScott Telford #define XCHAL_INTTYPE_MASK_TIMER 0x00002440 38623c2b932SScott Telford #define XCHAL_INTTYPE_MASK_NMI 0x00004000 38723c2b932SScott Telford #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 38823c2b932SScott Telford #define XCHAL_INTTYPE_MASK_PROFILING 0x00008000 38923c2b932SScott Telford 39023c2b932SScott Telford /* Interrupt numbers assigned to specific interrupt sources: */ 39123c2b932SScott Telford #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ 39223c2b932SScott Telford #define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ 39323c2b932SScott Telford #define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ 39423c2b932SScott Telford #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED 39523c2b932SScott Telford #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ 39623c2b932SScott Telford #define XCHAL_PROFILING_INTERRUPT 15 /* profiling interrupt */ 39723c2b932SScott Telford 39823c2b932SScott Telford /* Interrupt numbers for levels at which only one interrupt is configured: */ 39923c2b932SScott Telford #define XCHAL_INTLEVEL4_NUM 15 40023c2b932SScott Telford #define XCHAL_INTLEVEL5_NUM 13 40123c2b932SScott Telford #define XCHAL_INTLEVEL7_NUM 14 40223c2b932SScott Telford /* (There are many interrupts each at level(s) 1, 2, 3.) */ 40323c2b932SScott Telford 40423c2b932SScott Telford 40523c2b932SScott Telford /* 40623c2b932SScott Telford * External interrupt mapping. 40723c2b932SScott Telford * These macros describe how Xtensa processor interrupt numbers 40823c2b932SScott Telford * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) 40923c2b932SScott Telford * map to external BInterrupt<n> pins, for those interrupts 41023c2b932SScott Telford * configured as external (level-triggered, edge-triggered, or NMI). 41123c2b932SScott Telford * See the Xtensa processor databook for more details. 41223c2b932SScott Telford */ 41323c2b932SScott Telford 41423c2b932SScott Telford /* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ 41523c2b932SScott Telford #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ 41623c2b932SScott Telford #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ 41723c2b932SScott Telford #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ 41823c2b932SScott Telford #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ 41923c2b932SScott Telford #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ 42023c2b932SScott Telford #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ 42123c2b932SScott Telford #define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ 42223c2b932SScott Telford #define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ 42323c2b932SScott Telford #define XCHAL_EXTINT8_NUM 12 /* (intlevel 2) */ 42423c2b932SScott Telford #define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ 42523c2b932SScott Telford #define XCHAL_EXTINT10_NUM 16 /* (intlevel 1) */ 42623c2b932SScott Telford #define XCHAL_EXTINT11_NUM 17 /* (intlevel 1) */ 42723c2b932SScott Telford #define XCHAL_EXTINT12_NUM 18 /* (intlevel 1) */ 42823c2b932SScott Telford #define XCHAL_EXTINT13_NUM 19 /* (intlevel 1) */ 42923c2b932SScott Telford #define XCHAL_EXTINT14_NUM 20 /* (intlevel 1) */ 43023c2b932SScott Telford #define XCHAL_EXTINT15_NUM 21 /* (intlevel 3) */ 43123c2b932SScott Telford /* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ 43223c2b932SScott Telford #define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ 43323c2b932SScott Telford #define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ 43423c2b932SScott Telford #define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ 43523c2b932SScott Telford #define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ 43623c2b932SScott Telford #define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ 43723c2b932SScott Telford #define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ 43823c2b932SScott Telford #define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */ 43923c2b932SScott Telford #define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */ 44023c2b932SScott Telford #define XCHAL_INT12_EXTNUM 8 /* (intlevel 2) */ 44123c2b932SScott Telford #define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */ 44223c2b932SScott Telford #define XCHAL_INT16_EXTNUM 10 /* (intlevel 1) */ 44323c2b932SScott Telford #define XCHAL_INT17_EXTNUM 11 /* (intlevel 1) */ 44423c2b932SScott Telford #define XCHAL_INT18_EXTNUM 12 /* (intlevel 1) */ 44523c2b932SScott Telford #define XCHAL_INT19_EXTNUM 13 /* (intlevel 1) */ 44623c2b932SScott Telford #define XCHAL_INT20_EXTNUM 14 /* (intlevel 1) */ 44723c2b932SScott Telford #define XCHAL_INT21_EXTNUM 15 /* (intlevel 3) */ 44823c2b932SScott Telford 44923c2b932SScott Telford 45023c2b932SScott Telford /*---------------------------------------------------------------------- 45123c2b932SScott Telford EXCEPTIONS and VECTORS 45223c2b932SScott Telford ----------------------------------------------------------------------*/ 45323c2b932SScott Telford 45423c2b932SScott Telford #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture 45523c2b932SScott Telford number: 1 == XEA1 (old) 45623c2b932SScott Telford 2 == XEA2 (new) 45723c2b932SScott Telford 0 == XEAX (extern) or TX */ 45823c2b932SScott Telford #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ 45923c2b932SScott Telford #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ 46023c2b932SScott Telford #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ 46123c2b932SScott Telford #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ 46223c2b932SScott Telford #define XCHAL_HAVE_HALT 0 /* halt architecture option */ 46323c2b932SScott Telford #define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ 46423c2b932SScott Telford #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ 46523c2b932SScott Telford #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ 46623c2b932SScott Telford #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ 46723c2b932SScott Telford #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ 46823c2b932SScott Telford #define XCHAL_VECBASE_RESET_PADDR 0x00002000 46923c2b932SScott Telford #define XCHAL_RESET_VECBASE_OVERLAP 0 47023c2b932SScott Telford 47123c2b932SScott Telford #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 47223c2b932SScott Telford #define XCHAL_RESET_VECTOR0_PADDR 0xFE000000 47323c2b932SScott Telford #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 47423c2b932SScott Telford #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 47523c2b932SScott Telford #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 47623c2b932SScott Telford #define XCHAL_RESET_VECTOR_PADDR 0xFE000000 47723c2b932SScott Telford #define XCHAL_USER_VECOFS 0x00000340 47823c2b932SScott Telford #define XCHAL_USER_VECTOR_VADDR 0x00002340 47923c2b932SScott Telford #define XCHAL_USER_VECTOR_PADDR 0x00002340 48023c2b932SScott Telford #define XCHAL_KERNEL_VECOFS 0x00000300 48123c2b932SScott Telford #define XCHAL_KERNEL_VECTOR_VADDR 0x00002300 48223c2b932SScott Telford #define XCHAL_KERNEL_VECTOR_PADDR 0x00002300 48323c2b932SScott Telford #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 48423c2b932SScott Telford #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0 48523c2b932SScott Telford #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0 48623c2b932SScott Telford #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 48723c2b932SScott Telford #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 48823c2b932SScott Telford #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 48923c2b932SScott Telford #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 49023c2b932SScott Telford #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 49123c2b932SScott Telford #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 49223c2b932SScott Telford #define XCHAL_WINDOW_VECTORS_VADDR 0x00002000 49323c2b932SScott Telford #define XCHAL_WINDOW_VECTORS_PADDR 0x00002000 49423c2b932SScott Telford #define XCHAL_INTLEVEL2_VECOFS 0x00000180 49523c2b932SScott Telford #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180 49623c2b932SScott Telford #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180 49723c2b932SScott Telford #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 49823c2b932SScott Telford #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0 49923c2b932SScott Telford #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0 50023c2b932SScott Telford #define XCHAL_INTLEVEL4_VECOFS 0x00000200 50123c2b932SScott Telford #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200 50223c2b932SScott Telford #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200 50323c2b932SScott Telford #define XCHAL_INTLEVEL5_VECOFS 0x00000240 50423c2b932SScott Telford #define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240 50523c2b932SScott Telford #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240 50623c2b932SScott Telford #define XCHAL_INTLEVEL6_VECOFS 0x00000280 50723c2b932SScott Telford #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280 50823c2b932SScott Telford #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280 50923c2b932SScott Telford #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS 51023c2b932SScott Telford #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR 51123c2b932SScott Telford #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR 51223c2b932SScott Telford #define XCHAL_NMI_VECOFS 0x000002C0 51323c2b932SScott Telford #define XCHAL_NMI_VECTOR_VADDR 0x000022C0 51423c2b932SScott Telford #define XCHAL_NMI_VECTOR_PADDR 0x000022C0 51523c2b932SScott Telford #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS 51623c2b932SScott Telford #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR 51723c2b932SScott Telford #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR 51823c2b932SScott Telford 51923c2b932SScott Telford 52023c2b932SScott Telford /*---------------------------------------------------------------------- 52123c2b932SScott Telford DEBUG MODULE 52223c2b932SScott Telford ----------------------------------------------------------------------*/ 52323c2b932SScott Telford 52423c2b932SScott Telford /* Misc */ 52523c2b932SScott Telford #define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ 52623c2b932SScott Telford #define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ 52723c2b932SScott Telford #define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ 52823c2b932SScott Telford 52923c2b932SScott Telford /* On-Chip Debug (OCD) */ 53023c2b932SScott Telford #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ 53123c2b932SScott Telford #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ 53223c2b932SScott Telford #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ 53323c2b932SScott Telford #define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ 53423c2b932SScott Telford #define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ 53523c2b932SScott Telford 53623c2b932SScott Telford /* TRAX (in core) */ 53723c2b932SScott Telford #define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ 53823c2b932SScott Telford #define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */ 53923c2b932SScott Telford #define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ 54023c2b932SScott Telford #define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ 54123c2b932SScott Telford #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ 54223c2b932SScott Telford 54323c2b932SScott Telford /* Perf counters */ 54423c2b932SScott Telford #define XCHAL_NUM_PERF_COUNTERS 8 /* performance counters */ 54523c2b932SScott Telford 54623c2b932SScott Telford 54723c2b932SScott Telford /*---------------------------------------------------------------------- 54823c2b932SScott Telford MMU 54923c2b932SScott Telford ----------------------------------------------------------------------*/ 55023c2b932SScott Telford 55123c2b932SScott Telford /* See core-matmap.h header file for more details. */ 55223c2b932SScott Telford 55323c2b932SScott Telford #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ 55423c2b932SScott Telford #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ 55523c2b932SScott Telford #define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */ 55623c2b932SScott Telford #define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ 55723c2b932SScott Telford #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ 55823c2b932SScott Telford #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ 55923c2b932SScott Telford #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ 56023c2b932SScott Telford #define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table 56123c2b932SScott Telford [autorefill] and protection) 56223c2b932SScott Telford usable for an MMU-based OS */ 56323c2b932SScott Telford /* If none of the above last 4 are set, it's a custom TLB configuration. */ 56423c2b932SScott Telford #define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 56523c2b932SScott Telford #define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 56623c2b932SScott Telford 56723c2b932SScott Telford #define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ 56823c2b932SScott Telford #define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ 56923c2b932SScott Telford #define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */ 57023c2b932SScott Telford 57123c2b932SScott Telford #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 57223c2b932SScott Telford 57323c2b932SScott Telford 57423c2b932SScott Telford #endif /* _XTENSA_CORE_CONFIGURATION_H */ 57523c2b932SScott Telford 576