1*8c48e365SSimon Safar /* 2*8c48e365SSimon Safar * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 3*8c48e365SSimon Safar * processor CORE configuration 4*8c48e365SSimon Safar * 5*8c48e365SSimon Safar * See <xtensa/config/core.h>, which includes this file, for more details. 6*8c48e365SSimon Safar */ 7*8c48e365SSimon Safar 8*8c48e365SSimon Safar /* Xtensa processor core configuration information. 9*8c48e365SSimon Safar 10*8c48e365SSimon Safar Copyright (c) 1999-2010 Tensilica Inc. 11*8c48e365SSimon Safar 12*8c48e365SSimon Safar Permission is hereby granted, free of charge, to any person obtaining 13*8c48e365SSimon Safar a copy of this software and associated documentation files (the 14*8c48e365SSimon Safar "Software"), to deal in the Software without restriction, including 15*8c48e365SSimon Safar without limitation the rights to use, copy, modify, merge, publish, 16*8c48e365SSimon Safar distribute, sublicense, and/or sell copies of the Software, and to 17*8c48e365SSimon Safar permit persons to whom the Software is furnished to do so, subject to 18*8c48e365SSimon Safar the following conditions: 19*8c48e365SSimon Safar 20*8c48e365SSimon Safar The above copyright notice and this permission notice shall be included 21*8c48e365SSimon Safar in all copies or substantial portions of the Software. 22*8c48e365SSimon Safar 23*8c48e365SSimon Safar THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24*8c48e365SSimon Safar EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25*8c48e365SSimon Safar MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 26*8c48e365SSimon Safar IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 27*8c48e365SSimon Safar CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 28*8c48e365SSimon Safar TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 29*8c48e365SSimon Safar SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 30*8c48e365SSimon Safar 31*8c48e365SSimon Safar #ifndef _XTENSA_CORE_CONFIGURATION_H 32*8c48e365SSimon Safar #define _XTENSA_CORE_CONFIGURATION_H 33*8c48e365SSimon Safar 34*8c48e365SSimon Safar 35*8c48e365SSimon Safar /**************************************************************************** 36*8c48e365SSimon Safar Parameters Useful for Any Code, USER or PRIVILEGED 37*8c48e365SSimon Safar ****************************************************************************/ 38*8c48e365SSimon Safar 39*8c48e365SSimon Safar /* 40*8c48e365SSimon Safar * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is 41*8c48e365SSimon Safar * configured, and a value of 0 otherwise. These macros are always defined. 42*8c48e365SSimon Safar */ 43*8c48e365SSimon Safar 44*8c48e365SSimon Safar 45*8c48e365SSimon Safar /*---------------------------------------------------------------------- 46*8c48e365SSimon Safar ISA 47*8c48e365SSimon Safar ----------------------------------------------------------------------*/ 48*8c48e365SSimon Safar 49*8c48e365SSimon Safar #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 50*8c48e365SSimon Safar #define XCHAL_HAVE_WINDOWED 0 /* windowed registers option */ 51*8c48e365SSimon Safar #define XCHAL_NUM_AREGS 16 /* num of physical addr regs */ 52*8c48e365SSimon Safar #define XCHAL_NUM_AREGS_LOG2 4 /* log2(XCHAL_NUM_AREGS) */ 53*8c48e365SSimon Safar #define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ 54*8c48e365SSimon Safar #define XCHAL_HAVE_DEBUG 1 /* debug option */ 55*8c48e365SSimon Safar #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 56*8c48e365SSimon Safar #define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */ 57*8c48e365SSimon Safar #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ 58*8c48e365SSimon Safar #define XCHAL_HAVE_MINMAX 0 /* MIN/MAX instructions */ 59*8c48e365SSimon Safar #define XCHAL_HAVE_SEXT 0 /* SEXT instruction */ 60*8c48e365SSimon Safar #define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */ 61*8c48e365SSimon Safar #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ 62*8c48e365SSimon Safar #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ 63*8c48e365SSimon Safar #define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ 64*8c48e365SSimon Safar #define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */ 65*8c48e365SSimon Safar #define XCHAL_HAVE_L32R 1 /* L32R instruction */ 66*8c48e365SSimon Safar #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ 67*8c48e365SSimon Safar #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ 68*8c48e365SSimon Safar #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ 69*8c48e365SSimon Safar #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ 70*8c48e365SSimon Safar #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ 71*8c48e365SSimon Safar #define XCHAL_HAVE_CALL4AND12 0 /* (obsolete option) */ 72*8c48e365SSimon Safar #define XCHAL_HAVE_ABS 1 /* ABS instruction */ 73*8c48e365SSimon Safar /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ 74*8c48e365SSimon Safar /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ 75*8c48e365SSimon Safar #define XCHAL_HAVE_RELEASE_SYNC 0 /* L32AI/S32RI instructions */ 76*8c48e365SSimon Safar #define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */ 77*8c48e365SSimon Safar #define XCHAL_HAVE_SPECULATION 0 /* speculation */ 78*8c48e365SSimon Safar #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ 79*8c48e365SSimon Safar #define XCHAL_NUM_CONTEXTS 1 /* */ 80*8c48e365SSimon Safar #define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */ 81*8c48e365SSimon Safar #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ 82*8c48e365SSimon Safar #define XCHAL_HAVE_PRID 1 /* processor ID register */ 83*8c48e365SSimon Safar #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ 84*8c48e365SSimon Safar #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ 85*8c48e365SSimon Safar #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ 86*8c48e365SSimon Safar #define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */ 87*8c48e365SSimon Safar #define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ 88*8c48e365SSimon Safar #define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */ 89*8c48e365SSimon Safar #define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */ 90*8c48e365SSimon Safar #define XCHAL_HAVE_MAC16 0 /* MAC16 package */ 91*8c48e365SSimon Safar #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ 92*8c48e365SSimon Safar #define XCHAL_HAVE_FP 0 /* floating point pkg */ 93*8c48e365SSimon Safar #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ 94*8c48e365SSimon Safar #define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */ 95*8c48e365SSimon Safar #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ 96*8c48e365SSimon Safar #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ 97*8c48e365SSimon Safar #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ 98*8c48e365SSimon Safar #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ 99*8c48e365SSimon Safar #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ 100*8c48e365SSimon Safar 101*8c48e365SSimon Safar 102*8c48e365SSimon Safar /*---------------------------------------------------------------------- 103*8c48e365SSimon Safar MISC 104*8c48e365SSimon Safar ----------------------------------------------------------------------*/ 105*8c48e365SSimon Safar 106*8c48e365SSimon Safar #define XCHAL_NUM_WRITEBUFFER_ENTRIES 1 /* size of write buffer */ 107*8c48e365SSimon Safar #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ 108*8c48e365SSimon Safar #define XCHAL_DATA_WIDTH 4 /* data width in bytes */ 109*8c48e365SSimon Safar /* In T1050, applies to selected core load and store instructions (see ISA): */ 110*8c48e365SSimon Safar #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ 111*8c48e365SSimon Safar #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ 112*8c48e365SSimon Safar #define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ 113*8c48e365SSimon Safar #define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ 114*8c48e365SSimon Safar 115*8c48e365SSimon Safar #define XCHAL_SW_VERSION 800001 /* sw version of this header */ 116*8c48e365SSimon Safar 117*8c48e365SSimon Safar #define XCHAL_CORE_ID "lx106" /* alphanum core name 118*8c48e365SSimon Safar (CoreID) set in the Xtensa 119*8c48e365SSimon Safar Processor Generator */ 120*8c48e365SSimon Safar 121*8c48e365SSimon Safar #define XCHAL_BUILD_UNIQUE_ID 0x0002B6F6 /* 22-bit sw build ID */ 122*8c48e365SSimon Safar 123*8c48e365SSimon Safar /* 124*8c48e365SSimon Safar * These definitions describe the hardware targeted by this software. 125*8c48e365SSimon Safar */ 126*8c48e365SSimon Safar #define XCHAL_HW_CONFIGID0 0xC28CDAFA /* ConfigID hi 32 bits*/ 127*8c48e365SSimon Safar #define XCHAL_HW_CONFIGID1 0x1082B6F6 /* ConfigID lo 32 bits*/ 128*8c48e365SSimon Safar #define XCHAL_HW_VERSION_NAME "LX3.0.1" /* full version name */ 129*8c48e365SSimon Safar #define XCHAL_HW_VERSION_MAJOR 2300 /* major ver# of targeted hw */ 130*8c48e365SSimon Safar #define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */ 131*8c48e365SSimon Safar #define XCHAL_HW_VERSION 230001 /* major*100+minor */ 132*8c48e365SSimon Safar #define XCHAL_HW_REL_LX3 1 133*8c48e365SSimon Safar #define XCHAL_HW_REL_LX3_0 1 134*8c48e365SSimon Safar #define XCHAL_HW_REL_LX3_0_1 1 135*8c48e365SSimon Safar #define XCHAL_HW_CONFIGID_RELIABLE 1 136*8c48e365SSimon Safar /* If software targets a *range* of hardware versions, these are the bounds: */ 137*8c48e365SSimon Safar #define XCHAL_HW_MIN_VERSION_MAJOR 2300 /* major v of earliest tgt hw */ 138*8c48e365SSimon Safar #define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */ 139*8c48e365SSimon Safar #define XCHAL_HW_MIN_VERSION 230001 /* earliest targeted hw */ 140*8c48e365SSimon Safar #define XCHAL_HW_MAX_VERSION_MAJOR 2300 /* major v of latest tgt hw */ 141*8c48e365SSimon Safar #define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */ 142*8c48e365SSimon Safar #define XCHAL_HW_MAX_VERSION 230001 /* latest targeted hw */ 143*8c48e365SSimon Safar 144*8c48e365SSimon Safar 145*8c48e365SSimon Safar /*---------------------------------------------------------------------- 146*8c48e365SSimon Safar CACHE 147*8c48e365SSimon Safar ----------------------------------------------------------------------*/ 148*8c48e365SSimon Safar 149*8c48e365SSimon Safar #define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ 150*8c48e365SSimon Safar #define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ 151*8c48e365SSimon Safar #define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ 152*8c48e365SSimon Safar #define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ 153*8c48e365SSimon Safar 154*8c48e365SSimon Safar #define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ 155*8c48e365SSimon Safar #define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ 156*8c48e365SSimon Safar 157*8c48e365SSimon Safar #define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ 158*8c48e365SSimon Safar #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ 159*8c48e365SSimon Safar 160*8c48e365SSimon Safar #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ 161*8c48e365SSimon Safar 162*8c48e365SSimon Safar 163*8c48e365SSimon Safar 164*8c48e365SSimon Safar 165*8c48e365SSimon Safar /**************************************************************************** 166*8c48e365SSimon Safar Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 167*8c48e365SSimon Safar ****************************************************************************/ 168*8c48e365SSimon Safar 169*8c48e365SSimon Safar 170*8c48e365SSimon Safar #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 171*8c48e365SSimon Safar 172*8c48e365SSimon Safar /*---------------------------------------------------------------------- 173*8c48e365SSimon Safar CACHE 174*8c48e365SSimon Safar ----------------------------------------------------------------------*/ 175*8c48e365SSimon Safar 176*8c48e365SSimon Safar #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ 177*8c48e365SSimon Safar 178*8c48e365SSimon Safar /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ 179*8c48e365SSimon Safar 180*8c48e365SSimon Safar /* Number of cache sets in log2(lines per way): */ 181*8c48e365SSimon Safar #define XCHAL_ICACHE_SETWIDTH 0 182*8c48e365SSimon Safar #define XCHAL_DCACHE_SETWIDTH 0 183*8c48e365SSimon Safar 184*8c48e365SSimon Safar /* Cache set associativity (number of ways): */ 185*8c48e365SSimon Safar #define XCHAL_ICACHE_WAYS 1 186*8c48e365SSimon Safar #define XCHAL_DCACHE_WAYS 1 187*8c48e365SSimon Safar 188*8c48e365SSimon Safar /* Cache features: */ 189*8c48e365SSimon Safar #define XCHAL_ICACHE_LINE_LOCKABLE 0 190*8c48e365SSimon Safar #define XCHAL_DCACHE_LINE_LOCKABLE 0 191*8c48e365SSimon Safar #define XCHAL_ICACHE_ECC_PARITY 0 192*8c48e365SSimon Safar #define XCHAL_DCACHE_ECC_PARITY 0 193*8c48e365SSimon Safar 194*8c48e365SSimon Safar /* Cache access size in bytes (affects operation of SICW instruction): */ 195*8c48e365SSimon Safar #define XCHAL_ICACHE_ACCESS_SIZE 1 196*8c48e365SSimon Safar #define XCHAL_DCACHE_ACCESS_SIZE 1 197*8c48e365SSimon Safar 198*8c48e365SSimon Safar /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ 199*8c48e365SSimon Safar #define XCHAL_CA_BITS 4 200*8c48e365SSimon Safar 201*8c48e365SSimon Safar 202*8c48e365SSimon Safar /*---------------------------------------------------------------------- 203*8c48e365SSimon Safar INTERNAL I/D RAM/ROMs and XLMI 204*8c48e365SSimon Safar ----------------------------------------------------------------------*/ 205*8c48e365SSimon Safar 206*8c48e365SSimon Safar #define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */ 207*8c48e365SSimon Safar #define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ 208*8c48e365SSimon Safar #define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */ 209*8c48e365SSimon Safar #define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ 210*8c48e365SSimon Safar #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ 211*8c48e365SSimon Safar #define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */ 212*8c48e365SSimon Safar 213*8c48e365SSimon Safar /* Instruction ROM 0: */ 214*8c48e365SSimon Safar #define XCHAL_INSTROM0_VADDR 0x40200000 215*8c48e365SSimon Safar #define XCHAL_INSTROM0_PADDR 0x40200000 216*8c48e365SSimon Safar // #define XCHAL_INSTROM0_VADDR 0x400000 217*8c48e365SSimon Safar // #define XCHAL_INSTROM0_PADDR 0x400000 218*8c48e365SSimon Safar #define XCHAL_INSTROM0_SIZE 1048576 219*8c48e365SSimon Safar #define XCHAL_INSTROM0_ECC_PARITY 0 220*8c48e365SSimon Safar 221*8c48e365SSimon Safar /* Instruction RAM 0: */ 222*8c48e365SSimon Safar #define XCHAL_INSTRAM0_VADDR 0x40000000 223*8c48e365SSimon Safar #define XCHAL_INSTRAM0_PADDR 0x40000000 224*8c48e365SSimon Safar #define XCHAL_INSTRAM0_SIZE 1048576 225*8c48e365SSimon Safar #define XCHAL_INSTRAM0_ECC_PARITY 0 226*8c48e365SSimon Safar 227*8c48e365SSimon Safar /* Instruction RAM 1: */ 228*8c48e365SSimon Safar #define XCHAL_INSTRAM1_VADDR 0x40100000 229*8c48e365SSimon Safar #define XCHAL_INSTRAM1_PADDR 0x40100000 230*8c48e365SSimon Safar #define XCHAL_INSTRAM1_SIZE 1048576 231*8c48e365SSimon Safar #define XCHAL_INSTRAM1_ECC_PARITY 0 232*8c48e365SSimon Safar 233*8c48e365SSimon Safar /* Data ROM 0: */ 234*8c48e365SSimon Safar #define XCHAL_DATAROM0_VADDR 0x3FF40000 235*8c48e365SSimon Safar #define XCHAL_DATAROM0_PADDR 0x3FF40000 236*8c48e365SSimon Safar #define XCHAL_DATAROM0_SIZE 262144 237*8c48e365SSimon Safar #define XCHAL_DATAROM0_ECC_PARITY 0 238*8c48e365SSimon Safar 239*8c48e365SSimon Safar /* Data RAM 0: */ 240*8c48e365SSimon Safar #define XCHAL_DATARAM0_VADDR 0x3FFC0000 241*8c48e365SSimon Safar #define XCHAL_DATARAM0_PADDR 0x3FFC0000 242*8c48e365SSimon Safar #define XCHAL_DATARAM0_SIZE 262144 243*8c48e365SSimon Safar #define XCHAL_DATARAM0_ECC_PARITY 0 244*8c48e365SSimon Safar 245*8c48e365SSimon Safar /* Data RAM 1: */ 246*8c48e365SSimon Safar #define XCHAL_DATARAM1_VADDR 0x3FF80000 247*8c48e365SSimon Safar #define XCHAL_DATARAM1_PADDR 0x3FF80000 248*8c48e365SSimon Safar #define XCHAL_DATARAM1_SIZE 262144 249*8c48e365SSimon Safar #define XCHAL_DATARAM1_ECC_PARITY 0 250*8c48e365SSimon Safar 251*8c48e365SSimon Safar /* XLMI Port 0: */ 252*8c48e365SSimon Safar #define XCHAL_XLMI0_VADDR 0x3FF00000 253*8c48e365SSimon Safar #define XCHAL_XLMI0_PADDR 0x3FF00000 254*8c48e365SSimon Safar #define XCHAL_XLMI0_SIZE 262144 255*8c48e365SSimon Safar #define XCHAL_XLMI0_ECC_PARITY 0 256*8c48e365SSimon Safar 257*8c48e365SSimon Safar 258*8c48e365SSimon Safar /*---------------------------------------------------------------------- 259*8c48e365SSimon Safar INTERRUPTS and TIMERS 260*8c48e365SSimon Safar ----------------------------------------------------------------------*/ 261*8c48e365SSimon Safar 262*8c48e365SSimon Safar #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ 263*8c48e365SSimon Safar #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ 264*8c48e365SSimon Safar #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ 265*8c48e365SSimon Safar #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ 266*8c48e365SSimon Safar #define XCHAL_NUM_TIMERS 1 /* number of CCOMPAREn regs */ 267*8c48e365SSimon Safar #define XCHAL_NUM_INTERRUPTS 15 /* number of interrupts */ 268*8c48e365SSimon Safar #define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */ 269*8c48e365SSimon Safar #define XCHAL_NUM_EXTINTERRUPTS 13 /* num of external interrupts */ 270*8c48e365SSimon Safar #define XCHAL_NUM_INTLEVELS 2 /* number of interrupt levels 271*8c48e365SSimon Safar (not including level zero) */ 272*8c48e365SSimon Safar #define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */ 273*8c48e365SSimon Safar /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ 274*8c48e365SSimon Safar 275*8c48e365SSimon Safar /* Masks of interrupts at each interrupt level: */ 276*8c48e365SSimon Safar #define XCHAL_INTLEVEL1_MASK 0x00003FFF 277*8c48e365SSimon Safar #define XCHAL_INTLEVEL2_MASK 0x00000000 278*8c48e365SSimon Safar #define XCHAL_INTLEVEL3_MASK 0x00004000 279*8c48e365SSimon Safar #define XCHAL_INTLEVEL4_MASK 0x00000000 280*8c48e365SSimon Safar #define XCHAL_INTLEVEL5_MASK 0x00000000 281*8c48e365SSimon Safar #define XCHAL_INTLEVEL6_MASK 0x00000000 282*8c48e365SSimon Safar #define XCHAL_INTLEVEL7_MASK 0x00000000 283*8c48e365SSimon Safar 284*8c48e365SSimon Safar /* Masks of interrupts at each range 1..n of interrupt levels: */ 285*8c48e365SSimon Safar #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00003FFF 286*8c48e365SSimon Safar #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00003FFF 287*8c48e365SSimon Safar #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00007FFF 288*8c48e365SSimon Safar #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00007FFF 289*8c48e365SSimon Safar #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00007FFF 290*8c48e365SSimon Safar #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00007FFF 291*8c48e365SSimon Safar #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00007FFF 292*8c48e365SSimon Safar 293*8c48e365SSimon Safar /* Level of each interrupt: */ 294*8c48e365SSimon Safar #define XCHAL_INT0_LEVEL 1 295*8c48e365SSimon Safar #define XCHAL_INT1_LEVEL 1 296*8c48e365SSimon Safar #define XCHAL_INT2_LEVEL 1 297*8c48e365SSimon Safar #define XCHAL_INT3_LEVEL 1 298*8c48e365SSimon Safar #define XCHAL_INT4_LEVEL 1 299*8c48e365SSimon Safar #define XCHAL_INT5_LEVEL 1 300*8c48e365SSimon Safar #define XCHAL_INT6_LEVEL 1 301*8c48e365SSimon Safar #define XCHAL_INT7_LEVEL 1 302*8c48e365SSimon Safar #define XCHAL_INT8_LEVEL 1 303*8c48e365SSimon Safar #define XCHAL_INT9_LEVEL 1 304*8c48e365SSimon Safar #define XCHAL_INT10_LEVEL 1 305*8c48e365SSimon Safar #define XCHAL_INT11_LEVEL 1 306*8c48e365SSimon Safar #define XCHAL_INT12_LEVEL 1 307*8c48e365SSimon Safar #define XCHAL_INT13_LEVEL 1 308*8c48e365SSimon Safar #define XCHAL_INT14_LEVEL 3 309*8c48e365SSimon Safar #define XCHAL_DEBUGLEVEL 2 /* debug interrupt level */ 310*8c48e365SSimon Safar #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ 311*8c48e365SSimon Safar #define XCHAL_NMILEVEL 3 /* NMI "level" (for use with 312*8c48e365SSimon Safar EXCSAVE/EPS/EPC_n, RFI n) */ 313*8c48e365SSimon Safar 314*8c48e365SSimon Safar /* Type of each interrupt: */ 315*8c48e365SSimon Safar #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 316*8c48e365SSimon Safar #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 317*8c48e365SSimon Safar #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 318*8c48e365SSimon Safar #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 319*8c48e365SSimon Safar #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 320*8c48e365SSimon Safar #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 321*8c48e365SSimon Safar #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER 322*8c48e365SSimon Safar #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE 323*8c48e365SSimon Safar #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_EDGE 324*8c48e365SSimon Safar #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_EDGE 325*8c48e365SSimon Safar #define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE 326*8c48e365SSimon Safar #define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_EDGE 327*8c48e365SSimon Safar #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_EDGE 328*8c48e365SSimon Safar #define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_EDGE 329*8c48e365SSimon Safar #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI 330*8c48e365SSimon Safar 331*8c48e365SSimon Safar /* Masks of interrupts for each type of interrupt: */ 332*8c48e365SSimon Safar #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFF8000 333*8c48e365SSimon Safar #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000080 334*8c48e365SSimon Safar #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00003F00 335*8c48e365SSimon Safar #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000003F 336*8c48e365SSimon Safar #define XCHAL_INTTYPE_MASK_TIMER 0x00000040 337*8c48e365SSimon Safar #define XCHAL_INTTYPE_MASK_NMI 0x00004000 338*8c48e365SSimon Safar #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 339*8c48e365SSimon Safar 340*8c48e365SSimon Safar /* Interrupt numbers assigned to specific interrupt sources: */ 341*8c48e365SSimon Safar #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ 342*8c48e365SSimon Safar #define XCHAL_TIMER1_INTERRUPT XTHAL_TIMER_UNCONFIGURED 343*8c48e365SSimon Safar #define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED 344*8c48e365SSimon Safar #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED 345*8c48e365SSimon Safar #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ 346*8c48e365SSimon Safar 347*8c48e365SSimon Safar /* Interrupt numbers for levels at which only one interrupt is configured: */ 348*8c48e365SSimon Safar #define XCHAL_INTLEVEL3_NUM 14 349*8c48e365SSimon Safar /* (There are many interrupts each at level(s) 1.) */ 350*8c48e365SSimon Safar 351*8c48e365SSimon Safar 352*8c48e365SSimon Safar /* 353*8c48e365SSimon Safar * External interrupt vectors/levels. 354*8c48e365SSimon Safar * These macros describe how Xtensa processor interrupt numbers 355*8c48e365SSimon Safar * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) 356*8c48e365SSimon Safar * map to external BInterrupt<n> pins, for those interrupts 357*8c48e365SSimon Safar * configured as external (level-triggered, edge-triggered, or NMI). 358*8c48e365SSimon Safar * See the Xtensa processor databook for more details. 359*8c48e365SSimon Safar */ 360*8c48e365SSimon Safar 361*8c48e365SSimon Safar /* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ 362*8c48e365SSimon Safar #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ 363*8c48e365SSimon Safar #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ 364*8c48e365SSimon Safar #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ 365*8c48e365SSimon Safar #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ 366*8c48e365SSimon Safar #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ 367*8c48e365SSimon Safar #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ 368*8c48e365SSimon Safar #define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */ 369*8c48e365SSimon Safar #define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */ 370*8c48e365SSimon Safar #define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */ 371*8c48e365SSimon Safar #define XCHAL_EXTINT9_NUM 11 /* (intlevel 1) */ 372*8c48e365SSimon Safar #define XCHAL_EXTINT10_NUM 12 /* (intlevel 1) */ 373*8c48e365SSimon Safar #define XCHAL_EXTINT11_NUM 13 /* (intlevel 1) */ 374*8c48e365SSimon Safar #define XCHAL_EXTINT12_NUM 14 /* (intlevel 3) */ 375*8c48e365SSimon Safar 376*8c48e365SSimon Safar 377*8c48e365SSimon Safar /*---------------------------------------------------------------------- 378*8c48e365SSimon Safar EXCEPTIONS and VECTORS 379*8c48e365SSimon Safar ----------------------------------------------------------------------*/ 380*8c48e365SSimon Safar 381*8c48e365SSimon Safar #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture 382*8c48e365SSimon Safar number: 1 == XEA1 (old) 383*8c48e365SSimon Safar 2 == XEA2 (new) 384*8c48e365SSimon Safar 0 == XEAX (extern) */ 385*8c48e365SSimon Safar #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ 386*8c48e365SSimon Safar #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ 387*8c48e365SSimon Safar #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ 388*8c48e365SSimon Safar #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ 389*8c48e365SSimon Safar #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ 390*8c48e365SSimon Safar #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ 391*8c48e365SSimon Safar #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ 392*8c48e365SSimon Safar #define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ 393*8c48e365SSimon Safar #define XCHAL_VECBASE_RESET_PADDR 0x40000000 394*8c48e365SSimon Safar #define XCHAL_RESET_VECBASE_OVERLAP 0 395*8c48e365SSimon Safar 396*8c48e365SSimon Safar #define XCHAL_RESET_VECTOR0_VADDR 0x50000000 397*8c48e365SSimon Safar #define XCHAL_RESET_VECTOR0_PADDR 0x50000000 398*8c48e365SSimon Safar #define XCHAL_RESET_VECTOR1_VADDR 0x40000080 399*8c48e365SSimon Safar #define XCHAL_RESET_VECTOR1_PADDR 0x40000080 400*8c48e365SSimon Safar #define XCHAL_RESET_VECTOR_VADDR 0x50000000 401*8c48e365SSimon Safar #define XCHAL_RESET_VECTOR_PADDR 0x50000000 402*8c48e365SSimon Safar 403*8c48e365SSimon Safar // #define XCHAL_RESET_VECTOR0_VADDR 0x4000f8 404*8c48e365SSimon Safar // #define XCHAL_RESET_VECTOR0_PADDR 0x4000f8 405*8c48e365SSimon Safar // #define XCHAL_RESET_VECTOR1_VADDR 0x40000080 406*8c48e365SSimon Safar // #define XCHAL_RESET_VECTOR1_PADDR 0x40000080 407*8c48e365SSimon Safar // #define XCHAL_RESET_VECTOR_VADDR 0x4000f8 408*8c48e365SSimon Safar // #define XCHAL_RESET_VECTOR_PADDR 0x4000f8 409*8c48e365SSimon Safar 410*8c48e365SSimon Safar 411*8c48e365SSimon Safar #define XCHAL_USER_VECOFS 0x00000050 412*8c48e365SSimon Safar #define XCHAL_USER_VECTOR_VADDR 0x40000050 413*8c48e365SSimon Safar #define XCHAL_USER_VECTOR_PADDR 0x40000050 414*8c48e365SSimon Safar #define XCHAL_KERNEL_VECOFS 0x00000030 415*8c48e365SSimon Safar #define XCHAL_KERNEL_VECTOR_VADDR 0x40000030 416*8c48e365SSimon Safar #define XCHAL_KERNEL_VECTOR_PADDR 0x40000030 417*8c48e365SSimon Safar #define XCHAL_DOUBLEEXC_VECOFS 0x00000070 418*8c48e365SSimon Safar #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x40000070 419*8c48e365SSimon Safar #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x40000070 420*8c48e365SSimon Safar #define XCHAL_INTLEVEL2_VECOFS 0x00000010 421*8c48e365SSimon Safar #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000010 422*8c48e365SSimon Safar #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000010 423*8c48e365SSimon Safar #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL2_VECOFS 424*8c48e365SSimon Safar #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL2_VECTOR_VADDR 425*8c48e365SSimon Safar #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL2_VECTOR_PADDR 426*8c48e365SSimon Safar #define XCHAL_NMI_VECOFS 0x00000020 427*8c48e365SSimon Safar #define XCHAL_NMI_VECTOR_VADDR 0x40000020 428*8c48e365SSimon Safar #define XCHAL_NMI_VECTOR_PADDR 0x40000020 429*8c48e365SSimon Safar #define XCHAL_INTLEVEL3_VECOFS XCHAL_NMI_VECOFS 430*8c48e365SSimon Safar #define XCHAL_INTLEVEL3_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR 431*8c48e365SSimon Safar #define XCHAL_INTLEVEL3_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR 432*8c48e365SSimon Safar 433*8c48e365SSimon Safar 434*8c48e365SSimon Safar /*---------------------------------------------------------------------- 435*8c48e365SSimon Safar DEBUG 436*8c48e365SSimon Safar ----------------------------------------------------------------------*/ 437*8c48e365SSimon Safar 438*8c48e365SSimon Safar #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ 439*8c48e365SSimon Safar #define XCHAL_NUM_IBREAK 1 /* number of IBREAKn regs */ 440*8c48e365SSimon Safar #define XCHAL_NUM_DBREAK 1 /* number of DBREAKn regs */ 441*8c48e365SSimon Safar #define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option */ 442*8c48e365SSimon Safar 443*8c48e365SSimon Safar 444*8c48e365SSimon Safar /*---------------------------------------------------------------------- 445*8c48e365SSimon Safar MMU 446*8c48e365SSimon Safar ----------------------------------------------------------------------*/ 447*8c48e365SSimon Safar 448*8c48e365SSimon Safar /* See core-matmap.h header file for more details. */ 449*8c48e365SSimon Safar 450*8c48e365SSimon Safar #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ 451*8c48e365SSimon Safar #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ 452*8c48e365SSimon Safar #define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ 453*8c48e365SSimon Safar #define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ 454*8c48e365SSimon Safar #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ 455*8c48e365SSimon Safar #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ 456*8c48e365SSimon Safar #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ 457*8c48e365SSimon Safar #define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table 458*8c48e365SSimon Safar [autorefill] and protection) 459*8c48e365SSimon Safar usable for an MMU-based OS */ 460*8c48e365SSimon Safar /* If none of the above last 4 are set, it's a custom TLB configuration. */ 461*8c48e365SSimon Safar 462*8c48e365SSimon Safar #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ 463*8c48e365SSimon Safar #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ 464*8c48e365SSimon Safar #define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ 465*8c48e365SSimon Safar 466*8c48e365SSimon Safar #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 467*8c48e365SSimon Safar 468*8c48e365SSimon Safar 469*8c48e365SSimon Safar #endif /* _XTENSA_CORE_CONFIGURATION_H */ 470*8c48e365SSimon Safar 471