1bfd5bb6fSMax Filippov /* 2bfd5bb6fSMax Filippov * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 3bfd5bb6fSMax Filippov * processor CORE configuration 4bfd5bb6fSMax Filippov * 5bfd5bb6fSMax Filippov * See <xtensa/config/core.h>, which includes this file, for more details. 6bfd5bb6fSMax Filippov */ 7bfd5bb6fSMax Filippov 8bfd5bb6fSMax Filippov /* Xtensa processor core configuration information. 9bfd5bb6fSMax Filippov 10bfd5bb6fSMax Filippov Copyright (c) 1999-2015 Tensilica Inc. 11bfd5bb6fSMax Filippov 12bfd5bb6fSMax Filippov Permission is hereby granted, free of charge, to any person obtaining 13bfd5bb6fSMax Filippov a copy of this software and associated documentation files (the 14bfd5bb6fSMax Filippov "Software"), to deal in the Software without restriction, including 15bfd5bb6fSMax Filippov without limitation the rights to use, copy, modify, merge, publish, 16bfd5bb6fSMax Filippov distribute, sublicense, and/or sell copies of the Software, and to 17bfd5bb6fSMax Filippov permit persons to whom the Software is furnished to do so, subject to 18bfd5bb6fSMax Filippov the following conditions: 19bfd5bb6fSMax Filippov 20bfd5bb6fSMax Filippov The above copyright notice and this permission notice shall be included 21bfd5bb6fSMax Filippov in all copies or substantial portions of the Software. 22bfd5bb6fSMax Filippov 23bfd5bb6fSMax Filippov THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24bfd5bb6fSMax Filippov EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25bfd5bb6fSMax Filippov MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 26bfd5bb6fSMax Filippov IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 27bfd5bb6fSMax Filippov CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 28bfd5bb6fSMax Filippov TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 29bfd5bb6fSMax Filippov SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 30bfd5bb6fSMax Filippov 31bfd5bb6fSMax Filippov #ifndef _XTENSA_CORE_CONFIGURATION_H 32bfd5bb6fSMax Filippov #define _XTENSA_CORE_CONFIGURATION_H 33bfd5bb6fSMax Filippov 34bfd5bb6fSMax Filippov 35bfd5bb6fSMax Filippov /**************************************************************************** 36bfd5bb6fSMax Filippov Parameters Useful for Any Code, USER or PRIVILEGED 37bfd5bb6fSMax Filippov ****************************************************************************/ 38bfd5bb6fSMax Filippov 39bfd5bb6fSMax Filippov /* 40bfd5bb6fSMax Filippov * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is 41bfd5bb6fSMax Filippov * configured, and a value of 0 otherwise. These macros are always defined. 42bfd5bb6fSMax Filippov */ 43bfd5bb6fSMax Filippov 44bfd5bb6fSMax Filippov 45bfd5bb6fSMax Filippov /*---------------------------------------------------------------------- 46bfd5bb6fSMax Filippov ISA 47bfd5bb6fSMax Filippov ----------------------------------------------------------------------*/ 48bfd5bb6fSMax Filippov 49bfd5bb6fSMax Filippov #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */ 50bfd5bb6fSMax Filippov #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ 51bfd5bb6fSMax Filippov #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ 52bfd5bb6fSMax Filippov #define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ 53bfd5bb6fSMax Filippov #define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ 54bfd5bb6fSMax Filippov #define XCHAL_HAVE_DEBUG 1 /* debug option */ 55bfd5bb6fSMax Filippov #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 56bfd5bb6fSMax Filippov #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 57bfd5bb6fSMax Filippov #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ 58bfd5bb6fSMax Filippov #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ 59bfd5bb6fSMax Filippov #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ 60bfd5bb6fSMax Filippov #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ 61bfd5bb6fSMax Filippov #define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ 62bfd5bb6fSMax Filippov #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ 63bfd5bb6fSMax Filippov #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ 64bfd5bb6fSMax Filippov #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ 65bfd5bb6fSMax Filippov #define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ 66bfd5bb6fSMax Filippov #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ 67bfd5bb6fSMax Filippov #define XCHAL_HAVE_L32R 1 /* L32R instruction */ 68bfd5bb6fSMax Filippov #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ 69bfd5bb6fSMax Filippov #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ 70bfd5bb6fSMax Filippov #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ 71bfd5bb6fSMax Filippov #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ 72bfd5bb6fSMax Filippov #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ 73bfd5bb6fSMax Filippov #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ 74bfd5bb6fSMax Filippov #define XCHAL_HAVE_ABS 1 /* ABS instruction */ 75bfd5bb6fSMax Filippov /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ 76bfd5bb6fSMax Filippov /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ 77bfd5bb6fSMax Filippov #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ 78bfd5bb6fSMax Filippov #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ 79bfd5bb6fSMax Filippov #define XCHAL_HAVE_SPECULATION 0 /* speculation */ 80bfd5bb6fSMax Filippov #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ 81bfd5bb6fSMax Filippov #define XCHAL_NUM_CONTEXTS 1 /* */ 82bfd5bb6fSMax Filippov #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ 83bfd5bb6fSMax Filippov #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ 84bfd5bb6fSMax Filippov #define XCHAL_HAVE_PRID 1 /* processor ID register */ 85bfd5bb6fSMax Filippov #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ 86bfd5bb6fSMax Filippov #define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ 87bfd5bb6fSMax Filippov #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ 88bfd5bb6fSMax Filippov #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ 89bfd5bb6fSMax Filippov #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ 90bfd5bb6fSMax Filippov #define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ 91bfd5bb6fSMax Filippov #define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ 92bfd5bb6fSMax Filippov #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ 93bfd5bb6fSMax Filippov #define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ 94bfd5bb6fSMax Filippov #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ 95bfd5bb6fSMax Filippov #define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ 96bfd5bb6fSMax Filippov #define XCHAL_HAVE_MAC16 1 /* MAC16 package */ 97bfd5bb6fSMax Filippov 98bfd5bb6fSMax Filippov #define XCHAL_HAVE_FUSION 0 /* Fusion*/ 99bfd5bb6fSMax Filippov #define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ 100bfd5bb6fSMax Filippov #define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ 101bfd5bb6fSMax Filippov #define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ 102bfd5bb6fSMax Filippov #define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ 103bfd5bb6fSMax Filippov #define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ 104bfd5bb6fSMax Filippov #define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ 105bfd5bb6fSMax Filippov #define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ 106bfd5bb6fSMax Filippov #define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ 107bfd5bb6fSMax Filippov #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ 108bfd5bb6fSMax Filippov #define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ 109bfd5bb6fSMax Filippov #define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ 110bfd5bb6fSMax Filippov #define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ 111bfd5bb6fSMax Filippov #define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ 112bfd5bb6fSMax Filippov #define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */ 113bfd5bb6fSMax Filippov #define XCHAL_HAVE_HIFI2_MUL32X24 1 /* HiFi2 and 32x24 MACs */ 114bfd5bb6fSMax Filippov #define XCHAL_HAVE_HIFI2EP 1 /* HiFi2EP */ 115bfd5bb6fSMax Filippov #define XCHAL_HAVE_HIFI_MINI 0 116bfd5bb6fSMax Filippov 117bfd5bb6fSMax Filippov 118bfd5bb6fSMax Filippov #define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ 119bfd5bb6fSMax Filippov #define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ 120bfd5bb6fSMax Filippov #define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ 121bfd5bb6fSMax Filippov #define XCHAL_HAVE_FP 0 /* single prec floating point */ 122bfd5bb6fSMax Filippov #define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ 123bfd5bb6fSMax Filippov #define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ 124bfd5bb6fSMax Filippov #define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ 125bfd5bb6fSMax Filippov #define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ 126bfd5bb6fSMax Filippov #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ 127bfd5bb6fSMax Filippov #define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ 128bfd5bb6fSMax Filippov #define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ 129bfd5bb6fSMax Filippov #define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ 130bfd5bb6fSMax Filippov #define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ 131bfd5bb6fSMax Filippov #define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ 132bfd5bb6fSMax Filippov #define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ 133bfd5bb6fSMax Filippov 134bfd5bb6fSMax Filippov #define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ 135bfd5bb6fSMax Filippov #define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ 136bfd5bb6fSMax Filippov #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ 137bfd5bb6fSMax Filippov #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ 138bfd5bb6fSMax Filippov #define XCHAL_HAVE_PDX4 0 /* PDX4 */ 139bfd5bb6fSMax Filippov #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ 140bfd5bb6fSMax Filippov #define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ 141bfd5bb6fSMax Filippov #define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ 142bfd5bb6fSMax Filippov #define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ 143bfd5bb6fSMax Filippov #define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ 144bfd5bb6fSMax Filippov #define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ 145bfd5bb6fSMax Filippov #define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ 146bfd5bb6fSMax Filippov #define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ 147bfd5bb6fSMax Filippov #define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ 148bfd5bb6fSMax Filippov #define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ 149bfd5bb6fSMax Filippov #define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ 150bfd5bb6fSMax Filippov #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ 151bfd5bb6fSMax Filippov #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ 152bfd5bb6fSMax Filippov #define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ 153bfd5bb6fSMax Filippov #define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ 154bfd5bb6fSMax Filippov #define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ 155bfd5bb6fSMax Filippov 156bfd5bb6fSMax Filippov 157bfd5bb6fSMax Filippov /*---------------------------------------------------------------------- 158bfd5bb6fSMax Filippov MISC 159bfd5bb6fSMax Filippov ----------------------------------------------------------------------*/ 160bfd5bb6fSMax Filippov 161bfd5bb6fSMax Filippov #define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ 162bfd5bb6fSMax Filippov #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ 163bfd5bb6fSMax Filippov #define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ 164bfd5bb6fSMax Filippov #define XCHAL_DATA_WIDTH 8 /* data width in bytes */ 165bfd5bb6fSMax Filippov #define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay 166bfd5bb6fSMax Filippov (1 = 5-stage, 2 = 7-stage) */ 167bfd5bb6fSMax Filippov #define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */ 168bfd5bb6fSMax Filippov #define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct. unit clock gating */ 169bfd5bb6fSMax Filippov /* In T1050, applies to selected core load and store instructions (see ISA): */ 170bfd5bb6fSMax Filippov #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ 171bfd5bb6fSMax Filippov #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ 172bfd5bb6fSMax Filippov #define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ 173bfd5bb6fSMax Filippov #define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ 174bfd5bb6fSMax Filippov 175bfd5bb6fSMax Filippov #define XCHAL_SW_VERSION 1100002 /* sw version of this header */ 176bfd5bb6fSMax Filippov 177bfd5bb6fSMax Filippov #define XCHAL_CORE_ID "test_kc705_be" /* alphanum core name 178bfd5bb6fSMax Filippov (CoreID) set in the Xtensa 179bfd5bb6fSMax Filippov Processor Generator */ 180bfd5bb6fSMax Filippov 181bfd5bb6fSMax Filippov #define XCHAL_BUILD_UNIQUE_ID 0x00058D8C /* 22-bit sw build ID */ 182bfd5bb6fSMax Filippov 183bfd5bb6fSMax Filippov /* 184bfd5bb6fSMax Filippov * These definitions describe the hardware targeted by this software. 185bfd5bb6fSMax Filippov */ 186bfd5bb6fSMax Filippov #define XCHAL_HW_CONFIGID0 0xC1B3FFFF /* ConfigID hi 32 bits*/ 187bfd5bb6fSMax Filippov #define XCHAL_HW_CONFIGID1 0x1C858D8C /* ConfigID lo 32 bits*/ 188bfd5bb6fSMax Filippov #define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */ 189bfd5bb6fSMax Filippov #define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ 190bfd5bb6fSMax Filippov #define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */ 191bfd5bb6fSMax Filippov #define XCHAL_HW_VERSION 260002 /* major*100+minor */ 192bfd5bb6fSMax Filippov #define XCHAL_HW_REL_LX6 1 193bfd5bb6fSMax Filippov #define XCHAL_HW_REL_LX6_0 1 194bfd5bb6fSMax Filippov #define XCHAL_HW_REL_LX6_0_2 1 195bfd5bb6fSMax Filippov #define XCHAL_HW_CONFIGID_RELIABLE 1 196bfd5bb6fSMax Filippov /* If software targets a *range* of hardware versions, these are the bounds: */ 197bfd5bb6fSMax Filippov #define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ 198bfd5bb6fSMax Filippov #define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */ 199bfd5bb6fSMax Filippov #define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */ 200bfd5bb6fSMax Filippov #define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ 201bfd5bb6fSMax Filippov #define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */ 202bfd5bb6fSMax Filippov #define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */ 203bfd5bb6fSMax Filippov 204bfd5bb6fSMax Filippov 205bfd5bb6fSMax Filippov /*---------------------------------------------------------------------- 206bfd5bb6fSMax Filippov CACHE 207bfd5bb6fSMax Filippov ----------------------------------------------------------------------*/ 208bfd5bb6fSMax Filippov 209bfd5bb6fSMax Filippov #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ 210bfd5bb6fSMax Filippov #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ 211bfd5bb6fSMax Filippov #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ 212bfd5bb6fSMax Filippov #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ 213bfd5bb6fSMax Filippov 214bfd5bb6fSMax Filippov #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ 215bfd5bb6fSMax Filippov #define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */ 216bfd5bb6fSMax Filippov 217bfd5bb6fSMax Filippov #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ 218bfd5bb6fSMax Filippov #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ 219bfd5bb6fSMax Filippov 220bfd5bb6fSMax Filippov #define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ 221bfd5bb6fSMax Filippov #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ 222bfd5bb6fSMax Filippov #define XCHAL_PREFETCH_CASTOUT_LINES 1 /* dcache pref. castout bufsz */ 223bfd5bb6fSMax Filippov #define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */ 224bfd5bb6fSMax Filippov #define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ 225bfd5bb6fSMax Filippov #define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ 226bfd5bb6fSMax Filippov #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ 227bfd5bb6fSMax Filippov #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ 228bfd5bb6fSMax Filippov #define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ 229bfd5bb6fSMax Filippov #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ 230bfd5bb6fSMax Filippov 231bfd5bb6fSMax Filippov 232bfd5bb6fSMax Filippov 233bfd5bb6fSMax Filippov 234bfd5bb6fSMax Filippov /**************************************************************************** 235bfd5bb6fSMax Filippov Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 236bfd5bb6fSMax Filippov ****************************************************************************/ 237bfd5bb6fSMax Filippov 238bfd5bb6fSMax Filippov 239bfd5bb6fSMax Filippov #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 240bfd5bb6fSMax Filippov 241bfd5bb6fSMax Filippov /*---------------------------------------------------------------------- 242bfd5bb6fSMax Filippov CACHE 243bfd5bb6fSMax Filippov ----------------------------------------------------------------------*/ 244bfd5bb6fSMax Filippov 245bfd5bb6fSMax Filippov #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ 246bfd5bb6fSMax Filippov 247bfd5bb6fSMax Filippov /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ 248bfd5bb6fSMax Filippov 249bfd5bb6fSMax Filippov /* Number of cache sets in log2(lines per way): */ 250bfd5bb6fSMax Filippov #define XCHAL_ICACHE_SETWIDTH 7 251bfd5bb6fSMax Filippov #define XCHAL_DCACHE_SETWIDTH 7 252bfd5bb6fSMax Filippov 253bfd5bb6fSMax Filippov /* Cache set associativity (number of ways): */ 254bfd5bb6fSMax Filippov #define XCHAL_ICACHE_WAYS 4 255bfd5bb6fSMax Filippov #define XCHAL_DCACHE_WAYS 4 256bfd5bb6fSMax Filippov 257bfd5bb6fSMax Filippov /* Cache features: */ 258bfd5bb6fSMax Filippov #define XCHAL_ICACHE_LINE_LOCKABLE 1 259bfd5bb6fSMax Filippov #define XCHAL_DCACHE_LINE_LOCKABLE 1 260bfd5bb6fSMax Filippov #define XCHAL_ICACHE_ECC_PARITY 0 261bfd5bb6fSMax Filippov #define XCHAL_DCACHE_ECC_PARITY 0 262bfd5bb6fSMax Filippov 263bfd5bb6fSMax Filippov /* Cache access size in bytes (affects operation of SICW instruction): */ 264bfd5bb6fSMax Filippov #define XCHAL_ICACHE_ACCESS_SIZE 8 265bfd5bb6fSMax Filippov #define XCHAL_DCACHE_ACCESS_SIZE 8 266bfd5bb6fSMax Filippov 267bfd5bb6fSMax Filippov #define XCHAL_DCACHE_BANKS 1 /* number of banks */ 268bfd5bb6fSMax Filippov 269bfd5bb6fSMax Filippov /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ 270bfd5bb6fSMax Filippov #define XCHAL_CA_BITS 4 271bfd5bb6fSMax Filippov 272bfd5bb6fSMax Filippov /* Whether MEMCTL register has anything useful */ 273bfd5bb6fSMax Filippov #define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \ 274bfd5bb6fSMax Filippov XCHAL_DCACHE_IS_COHERENT || \ 275bfd5bb6fSMax Filippov XCHAL_HAVE_ICACHE_DYN_WAYS || \ 276bfd5bb6fSMax Filippov XCHAL_HAVE_DCACHE_DYN_WAYS) && \ 277bfd5bb6fSMax Filippov (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0)) 278bfd5bb6fSMax Filippov 279bfd5bb6fSMax Filippov 280bfd5bb6fSMax Filippov /*---------------------------------------------------------------------- 281bfd5bb6fSMax Filippov INTERNAL I/D RAM/ROMs and XLMI 282bfd5bb6fSMax Filippov ----------------------------------------------------------------------*/ 283bfd5bb6fSMax Filippov 284bfd5bb6fSMax Filippov #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ 285bfd5bb6fSMax Filippov #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ 286bfd5bb6fSMax Filippov #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ 287bfd5bb6fSMax Filippov #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ 288bfd5bb6fSMax Filippov #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ 289bfd5bb6fSMax Filippov #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ 290bfd5bb6fSMax Filippov 291bfd5bb6fSMax Filippov #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ 292bfd5bb6fSMax Filippov 293bfd5bb6fSMax Filippov 294bfd5bb6fSMax Filippov /*---------------------------------------------------------------------- 295bfd5bb6fSMax Filippov INTERRUPTS and TIMERS 296bfd5bb6fSMax Filippov ----------------------------------------------------------------------*/ 297bfd5bb6fSMax Filippov 298bfd5bb6fSMax Filippov #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ 299bfd5bb6fSMax Filippov #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ 300bfd5bb6fSMax Filippov #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ 301bfd5bb6fSMax Filippov #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ 302bfd5bb6fSMax Filippov #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ 303bfd5bb6fSMax Filippov #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ 304bfd5bb6fSMax Filippov #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ 305bfd5bb6fSMax Filippov #define XCHAL_NUM_EXTINTERRUPTS 16 /* num of external interrupts */ 306bfd5bb6fSMax Filippov #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels 307bfd5bb6fSMax Filippov (not including level zero) */ 308bfd5bb6fSMax Filippov #define XCHAL_EXCM_LEVEL 4 /* level masked by PS.EXCM */ 309bfd5bb6fSMax Filippov /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ 310bfd5bb6fSMax Filippov 311bfd5bb6fSMax Filippov /* Masks of interrupts at each interrupt level: */ 312bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL1_MASK 0x001F00BF 313bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL2_MASK 0x00000140 314bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL3_MASK 0x00200E00 315bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL4_MASK 0x00008000 316bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL5_MASK 0x00003000 317bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL6_MASK 0x00000000 318bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL7_MASK 0x00004000 319bfd5bb6fSMax Filippov 320bfd5bb6fSMax Filippov /* Masks of interrupts at each range 1..n of interrupt levels: */ 321bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F00BF 322bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F01FF 323bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F0FFF 324bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F8FFF 325bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF 326bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF 327bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF 328bfd5bb6fSMax Filippov 329bfd5bb6fSMax Filippov /* Level of each interrupt: */ 330bfd5bb6fSMax Filippov #define XCHAL_INT0_LEVEL 1 331bfd5bb6fSMax Filippov #define XCHAL_INT1_LEVEL 1 332bfd5bb6fSMax Filippov #define XCHAL_INT2_LEVEL 1 333bfd5bb6fSMax Filippov #define XCHAL_INT3_LEVEL 1 334bfd5bb6fSMax Filippov #define XCHAL_INT4_LEVEL 1 335bfd5bb6fSMax Filippov #define XCHAL_INT5_LEVEL 1 336bfd5bb6fSMax Filippov #define XCHAL_INT6_LEVEL 2 337bfd5bb6fSMax Filippov #define XCHAL_INT7_LEVEL 1 338bfd5bb6fSMax Filippov #define XCHAL_INT8_LEVEL 2 339bfd5bb6fSMax Filippov #define XCHAL_INT9_LEVEL 3 340bfd5bb6fSMax Filippov #define XCHAL_INT10_LEVEL 3 341bfd5bb6fSMax Filippov #define XCHAL_INT11_LEVEL 3 342bfd5bb6fSMax Filippov #define XCHAL_INT12_LEVEL 5 343bfd5bb6fSMax Filippov #define XCHAL_INT13_LEVEL 5 344bfd5bb6fSMax Filippov #define XCHAL_INT14_LEVEL 7 345bfd5bb6fSMax Filippov #define XCHAL_INT15_LEVEL 4 346bfd5bb6fSMax Filippov #define XCHAL_INT16_LEVEL 1 347bfd5bb6fSMax Filippov #define XCHAL_INT17_LEVEL 1 348bfd5bb6fSMax Filippov #define XCHAL_INT18_LEVEL 1 349bfd5bb6fSMax Filippov #define XCHAL_INT19_LEVEL 1 350bfd5bb6fSMax Filippov #define XCHAL_INT20_LEVEL 1 351bfd5bb6fSMax Filippov #define XCHAL_INT21_LEVEL 3 352bfd5bb6fSMax Filippov #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ 353bfd5bb6fSMax Filippov #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ 354bfd5bb6fSMax Filippov #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with 355bfd5bb6fSMax Filippov EXCSAVE/EPS/EPC_n, RFI n) */ 356bfd5bb6fSMax Filippov 357bfd5bb6fSMax Filippov /* Type of each interrupt: */ 358bfd5bb6fSMax Filippov #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 359bfd5bb6fSMax Filippov #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 360bfd5bb6fSMax Filippov #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 361bfd5bb6fSMax Filippov #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 362bfd5bb6fSMax Filippov #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 363bfd5bb6fSMax Filippov #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 364bfd5bb6fSMax Filippov #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER 365bfd5bb6fSMax Filippov #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE 366bfd5bb6fSMax Filippov #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 367bfd5bb6fSMax Filippov #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 368bfd5bb6fSMax Filippov #define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER 369bfd5bb6fSMax Filippov #define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE 370bfd5bb6fSMax Filippov #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 371bfd5bb6fSMax Filippov #define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER 372bfd5bb6fSMax Filippov #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI 373bfd5bb6fSMax Filippov #define XCHAL_INT15_TYPE XTHAL_INTTYPE_PROFILING 374bfd5bb6fSMax Filippov #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE 375bfd5bb6fSMax Filippov #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE 376bfd5bb6fSMax Filippov #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE 377bfd5bb6fSMax Filippov #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE 378bfd5bb6fSMax Filippov #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE 379bfd5bb6fSMax Filippov #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE 380bfd5bb6fSMax Filippov 381bfd5bb6fSMax Filippov /* Masks of interrupts for each type of interrupt: */ 382bfd5bb6fSMax Filippov #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 383bfd5bb6fSMax Filippov #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 384bfd5bb6fSMax Filippov #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F0000 385bfd5bb6fSMax Filippov #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F 386bfd5bb6fSMax Filippov #define XCHAL_INTTYPE_MASK_TIMER 0x00002440 387bfd5bb6fSMax Filippov #define XCHAL_INTTYPE_MASK_NMI 0x00004000 388bfd5bb6fSMax Filippov #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 389bfd5bb6fSMax Filippov #define XCHAL_INTTYPE_MASK_PROFILING 0x00008000 390bfd5bb6fSMax Filippov 391bfd5bb6fSMax Filippov /* Interrupt numbers assigned to specific interrupt sources: */ 392bfd5bb6fSMax Filippov #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ 393bfd5bb6fSMax Filippov #define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ 394bfd5bb6fSMax Filippov #define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ 395bfd5bb6fSMax Filippov #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED 396bfd5bb6fSMax Filippov #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ 397bfd5bb6fSMax Filippov #define XCHAL_PROFILING_INTERRUPT 15 /* profiling interrupt */ 398bfd5bb6fSMax Filippov 399bfd5bb6fSMax Filippov /* Interrupt numbers for levels at which only one interrupt is configured: */ 400bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL4_NUM 15 401bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL7_NUM 14 402bfd5bb6fSMax Filippov /* (There are many interrupts each at level(s) 1, 2, 3, 5.) */ 403bfd5bb6fSMax Filippov 404bfd5bb6fSMax Filippov 405bfd5bb6fSMax Filippov /* 406bfd5bb6fSMax Filippov * External interrupt mapping. 407bfd5bb6fSMax Filippov * These macros describe how Xtensa processor interrupt numbers 408bfd5bb6fSMax Filippov * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) 409bfd5bb6fSMax Filippov * map to external BInterrupt<n> pins, for those interrupts 410bfd5bb6fSMax Filippov * configured as external (level-triggered, edge-triggered, or NMI). 411bfd5bb6fSMax Filippov * See the Xtensa processor databook for more details. 412bfd5bb6fSMax Filippov */ 413bfd5bb6fSMax Filippov 414bfd5bb6fSMax Filippov /* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ 415bfd5bb6fSMax Filippov #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ 416bfd5bb6fSMax Filippov #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ 417bfd5bb6fSMax Filippov #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ 418bfd5bb6fSMax Filippov #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ 419bfd5bb6fSMax Filippov #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ 420bfd5bb6fSMax Filippov #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ 421bfd5bb6fSMax Filippov #define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ 422bfd5bb6fSMax Filippov #define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ 423bfd5bb6fSMax Filippov #define XCHAL_EXTINT8_NUM 12 /* (intlevel 5) */ 424bfd5bb6fSMax Filippov #define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ 425bfd5bb6fSMax Filippov #define XCHAL_EXTINT10_NUM 16 /* (intlevel 1) */ 426bfd5bb6fSMax Filippov #define XCHAL_EXTINT11_NUM 17 /* (intlevel 1) */ 427bfd5bb6fSMax Filippov #define XCHAL_EXTINT12_NUM 18 /* (intlevel 1) */ 428bfd5bb6fSMax Filippov #define XCHAL_EXTINT13_NUM 19 /* (intlevel 1) */ 429bfd5bb6fSMax Filippov #define XCHAL_EXTINT14_NUM 20 /* (intlevel 1) */ 430bfd5bb6fSMax Filippov #define XCHAL_EXTINT15_NUM 21 /* (intlevel 3) */ 431bfd5bb6fSMax Filippov /* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ 432bfd5bb6fSMax Filippov #define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ 433bfd5bb6fSMax Filippov #define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ 434bfd5bb6fSMax Filippov #define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ 435bfd5bb6fSMax Filippov #define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ 436bfd5bb6fSMax Filippov #define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ 437bfd5bb6fSMax Filippov #define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ 438bfd5bb6fSMax Filippov #define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */ 439bfd5bb6fSMax Filippov #define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */ 440bfd5bb6fSMax Filippov #define XCHAL_INT12_EXTNUM 8 /* (intlevel 5) */ 441bfd5bb6fSMax Filippov #define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */ 442bfd5bb6fSMax Filippov #define XCHAL_INT16_EXTNUM 10 /* (intlevel 1) */ 443bfd5bb6fSMax Filippov #define XCHAL_INT17_EXTNUM 11 /* (intlevel 1) */ 444bfd5bb6fSMax Filippov #define XCHAL_INT18_EXTNUM 12 /* (intlevel 1) */ 445bfd5bb6fSMax Filippov #define XCHAL_INT19_EXTNUM 13 /* (intlevel 1) */ 446bfd5bb6fSMax Filippov #define XCHAL_INT20_EXTNUM 14 /* (intlevel 1) */ 447bfd5bb6fSMax Filippov #define XCHAL_INT21_EXTNUM 15 /* (intlevel 3) */ 448bfd5bb6fSMax Filippov 449bfd5bb6fSMax Filippov 450bfd5bb6fSMax Filippov /*---------------------------------------------------------------------- 451bfd5bb6fSMax Filippov EXCEPTIONS and VECTORS 452bfd5bb6fSMax Filippov ----------------------------------------------------------------------*/ 453bfd5bb6fSMax Filippov 454bfd5bb6fSMax Filippov #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture 455bfd5bb6fSMax Filippov number: 1 == XEA1 (old) 456bfd5bb6fSMax Filippov 2 == XEA2 (new) 457bfd5bb6fSMax Filippov 0 == XEAX (extern) or TX */ 458bfd5bb6fSMax Filippov #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ 459bfd5bb6fSMax Filippov #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ 460bfd5bb6fSMax Filippov #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ 461bfd5bb6fSMax Filippov #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ 462bfd5bb6fSMax Filippov #define XCHAL_HAVE_HALT 0 /* halt architecture option */ 463bfd5bb6fSMax Filippov #define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ 464bfd5bb6fSMax Filippov #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ 465bfd5bb6fSMax Filippov #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ 466bfd5bb6fSMax Filippov #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ 467bfd5bb6fSMax Filippov #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ 468bfd5bb6fSMax Filippov #define XCHAL_VECBASE_RESET_PADDR 0x00002000 469bfd5bb6fSMax Filippov #define XCHAL_RESET_VECBASE_OVERLAP 0 470bfd5bb6fSMax Filippov 471bfd5bb6fSMax Filippov #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 472bfd5bb6fSMax Filippov #define XCHAL_RESET_VECTOR0_PADDR 0xFE000000 473bfd5bb6fSMax Filippov #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 474bfd5bb6fSMax Filippov #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 475bfd5bb6fSMax Filippov #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 476bfd5bb6fSMax Filippov #define XCHAL_RESET_VECTOR_PADDR 0xFE000000 477bfd5bb6fSMax Filippov #define XCHAL_USER_VECOFS 0x00000340 478bfd5bb6fSMax Filippov #define XCHAL_USER_VECTOR_VADDR 0x00002340 479bfd5bb6fSMax Filippov #define XCHAL_USER_VECTOR_PADDR 0x00002340 480bfd5bb6fSMax Filippov #define XCHAL_KERNEL_VECOFS 0x00000300 481bfd5bb6fSMax Filippov #define XCHAL_KERNEL_VECTOR_VADDR 0x00002300 482bfd5bb6fSMax Filippov #define XCHAL_KERNEL_VECTOR_PADDR 0x00002300 483bfd5bb6fSMax Filippov #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 484bfd5bb6fSMax Filippov #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0 485bfd5bb6fSMax Filippov #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0 486bfd5bb6fSMax Filippov #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 487bfd5bb6fSMax Filippov #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 488bfd5bb6fSMax Filippov #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 489bfd5bb6fSMax Filippov #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 490bfd5bb6fSMax Filippov #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 491bfd5bb6fSMax Filippov #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 492bfd5bb6fSMax Filippov #define XCHAL_WINDOW_VECTORS_VADDR 0x00002000 493bfd5bb6fSMax Filippov #define XCHAL_WINDOW_VECTORS_PADDR 0x00002000 494bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL2_VECOFS 0x00000180 495bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180 496bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180 497bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 498bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0 499bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0 500bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL4_VECOFS 0x00000200 501bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200 502bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200 503bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL5_VECOFS 0x00000240 504bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240 505bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240 506bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL6_VECOFS 0x00000280 507bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280 508bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280 509bfd5bb6fSMax Filippov #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS 510bfd5bb6fSMax Filippov #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR 511bfd5bb6fSMax Filippov #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR 512bfd5bb6fSMax Filippov #define XCHAL_NMI_VECOFS 0x000002C0 513bfd5bb6fSMax Filippov #define XCHAL_NMI_VECTOR_VADDR 0x000022C0 514bfd5bb6fSMax Filippov #define XCHAL_NMI_VECTOR_PADDR 0x000022C0 515bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS 516bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR 517bfd5bb6fSMax Filippov #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR 518bfd5bb6fSMax Filippov 519bfd5bb6fSMax Filippov 520bfd5bb6fSMax Filippov /*---------------------------------------------------------------------- 521bfd5bb6fSMax Filippov DEBUG MODULE 522bfd5bb6fSMax Filippov ----------------------------------------------------------------------*/ 523bfd5bb6fSMax Filippov 524bfd5bb6fSMax Filippov /* Misc */ 525bfd5bb6fSMax Filippov #define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ 526bfd5bb6fSMax Filippov #define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ 527bfd5bb6fSMax Filippov #define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ 528bfd5bb6fSMax Filippov 529bfd5bb6fSMax Filippov /* On-Chip Debug (OCD) */ 530bfd5bb6fSMax Filippov #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ 531bfd5bb6fSMax Filippov #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ 532bfd5bb6fSMax Filippov #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ 533bfd5bb6fSMax Filippov #define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ 534bfd5bb6fSMax Filippov #define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ 535bfd5bb6fSMax Filippov 536bfd5bb6fSMax Filippov /* TRAX (in core) */ 537bfd5bb6fSMax Filippov #define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ 538bfd5bb6fSMax Filippov #define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */ 539bfd5bb6fSMax Filippov #define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ 540bfd5bb6fSMax Filippov #define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ 541bfd5bb6fSMax Filippov #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ 542bfd5bb6fSMax Filippov 543bfd5bb6fSMax Filippov /* Perf counters */ 544bfd5bb6fSMax Filippov #define XCHAL_NUM_PERF_COUNTERS 8 /* performance counters */ 545bfd5bb6fSMax Filippov 546bfd5bb6fSMax Filippov 547bfd5bb6fSMax Filippov /*---------------------------------------------------------------------- 548bfd5bb6fSMax Filippov MMU 549bfd5bb6fSMax Filippov ----------------------------------------------------------------------*/ 550bfd5bb6fSMax Filippov 551bfd5bb6fSMax Filippov /* See core-matmap.h header file for more details. */ 552bfd5bb6fSMax Filippov 553bfd5bb6fSMax Filippov #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ 554bfd5bb6fSMax Filippov #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ 555bfd5bb6fSMax Filippov #define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */ 556bfd5bb6fSMax Filippov #define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ 557bfd5bb6fSMax Filippov #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ 558bfd5bb6fSMax Filippov #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ 559bfd5bb6fSMax Filippov #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ 560bfd5bb6fSMax Filippov #define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table 561bfd5bb6fSMax Filippov [autorefill] and protection) 562bfd5bb6fSMax Filippov usable for an MMU-based OS */ 563bfd5bb6fSMax Filippov /* If none of the above last 4 are set, it's a custom TLB configuration. */ 564bfd5bb6fSMax Filippov #define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 565bfd5bb6fSMax Filippov #define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 566bfd5bb6fSMax Filippov 567bfd5bb6fSMax Filippov #define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ 568bfd5bb6fSMax Filippov #define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ 569bfd5bb6fSMax Filippov #define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */ 570bfd5bb6fSMax Filippov 571bfd5bb6fSMax Filippov #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 572bfd5bb6fSMax Filippov 573bfd5bb6fSMax Filippov 574bfd5bb6fSMax Filippov #endif /* _XTENSA_CORE_CONFIGURATION_H */ 575bfd5bb6fSMax Filippov 576