1d0b73b48SPete Delaney /* 2d0b73b48SPete Delaney * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 3d0b73b48SPete Delaney * processor CORE configuration 4d0b73b48SPete Delaney * 5d0b73b48SPete Delaney * See <xtensa/config/core.h>, which includes this file, for more details. 6d0b73b48SPete Delaney */ 7d0b73b48SPete Delaney 8d0b73b48SPete Delaney /* Xtensa processor core configuration information. 9d0b73b48SPete Delaney 10d0b73b48SPete Delaney Copyright (c) 1999-2010 Tensilica Inc. 11d0b73b48SPete Delaney 12d0b73b48SPete Delaney Permission is hereby granted, free of charge, to any person obtaining 13d0b73b48SPete Delaney a copy of this software and associated documentation files (the 14d0b73b48SPete Delaney "Software"), to deal in the Software without restriction, including 15d0b73b48SPete Delaney without limitation the rights to use, copy, modify, merge, publish, 16d0b73b48SPete Delaney distribute, sublicense, and/or sell copies of the Software, and to 17d0b73b48SPete Delaney permit persons to whom the Software is furnished to do so, subject to 18d0b73b48SPete Delaney the following conditions: 19d0b73b48SPete Delaney 20d0b73b48SPete Delaney The above copyright notice and this permission notice shall be included 21d0b73b48SPete Delaney in all copies or substantial portions of the Software. 22d0b73b48SPete Delaney 23d0b73b48SPete Delaney THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24d0b73b48SPete Delaney EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25d0b73b48SPete Delaney MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 26d0b73b48SPete Delaney IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 27d0b73b48SPete Delaney CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 28d0b73b48SPete Delaney TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 29d0b73b48SPete Delaney SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 30d0b73b48SPete Delaney 31d0b73b48SPete Delaney #ifndef _XTENSA_CORE_CONFIGURATION_H 32d0b73b48SPete Delaney #define _XTENSA_CORE_CONFIGURATION_H 33d0b73b48SPete Delaney 34d0b73b48SPete Delaney 35d0b73b48SPete Delaney /**************************************************************************** 36d0b73b48SPete Delaney Parameters Useful for Any Code, USER or PRIVILEGED 37d0b73b48SPete Delaney ****************************************************************************/ 38d0b73b48SPete Delaney 39d0b73b48SPete Delaney /* 40d0b73b48SPete Delaney * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is 41d0b73b48SPete Delaney * configured, and a value of 0 otherwise. These macros are always defined. 42d0b73b48SPete Delaney */ 43d0b73b48SPete Delaney 44d0b73b48SPete Delaney 45d0b73b48SPete Delaney /*---------------------------------------------------------------------- 46d0b73b48SPete Delaney ISA 47d0b73b48SPete Delaney ----------------------------------------------------------------------*/ 48d0b73b48SPete Delaney 49d0b73b48SPete Delaney #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 50d0b73b48SPete Delaney #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ 51d0b73b48SPete Delaney #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ 52d0b73b48SPete Delaney #define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ 53d0b73b48SPete Delaney #define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ 54d0b73b48SPete Delaney #define XCHAL_HAVE_DEBUG 1 /* debug option */ 55d0b73b48SPete Delaney #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 56d0b73b48SPete Delaney #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 57d0b73b48SPete Delaney #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ 58d0b73b48SPete Delaney #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ 59d0b73b48SPete Delaney #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ 60d0b73b48SPete Delaney #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ 61d0b73b48SPete Delaney #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ 62d0b73b48SPete Delaney #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ 63d0b73b48SPete Delaney #define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ 64d0b73b48SPete Delaney #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ 65d0b73b48SPete Delaney #define XCHAL_HAVE_L32R 1 /* L32R instruction */ 66d0b73b48SPete Delaney #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ 67d0b73b48SPete Delaney #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ 68d0b73b48SPete Delaney #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ 69d0b73b48SPete Delaney #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ 70d0b73b48SPete Delaney #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ 71d0b73b48SPete Delaney #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ 72d0b73b48SPete Delaney #define XCHAL_HAVE_ABS 1 /* ABS instruction */ 73d0b73b48SPete Delaney /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ 74d0b73b48SPete Delaney /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ 75d0b73b48SPete Delaney #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ 76d0b73b48SPete Delaney #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ 77d0b73b48SPete Delaney #define XCHAL_HAVE_SPECULATION 0 /* speculation */ 78d0b73b48SPete Delaney #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ 79d0b73b48SPete Delaney #define XCHAL_NUM_CONTEXTS 1 /* */ 80d0b73b48SPete Delaney #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ 81d0b73b48SPete Delaney #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ 82d0b73b48SPete Delaney #define XCHAL_HAVE_PRID 1 /* processor ID register */ 83d0b73b48SPete Delaney #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ 84d0b73b48SPete Delaney #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ 85d0b73b48SPete Delaney #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ 86d0b73b48SPete Delaney #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ 87d0b73b48SPete Delaney #define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ 88d0b73b48SPete Delaney #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ 89d0b73b48SPete Delaney #define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ 90d0b73b48SPete Delaney #define XCHAL_HAVE_MAC16 1 /* MAC16 package */ 91d0b73b48SPete Delaney #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ 92d0b73b48SPete Delaney #define XCHAL_HAVE_FP 0 /* floating point pkg */ 93d0b73b48SPete Delaney #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ 94d0b73b48SPete Delaney #define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */ 95d0b73b48SPete Delaney #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ 96d0b73b48SPete Delaney #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ 97d0b73b48SPete Delaney #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ 98d0b73b48SPete Delaney #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ 99d0b73b48SPete Delaney #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ 100d0b73b48SPete Delaney #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ 101d0b73b48SPete Delaney #define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ 102d0b73b48SPete Delaney #define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ 103d0b73b48SPete Delaney #define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ 104d0b73b48SPete Delaney #define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ 105d0b73b48SPete Delaney #define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ 106d0b73b48SPete Delaney #define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ 107d0b73b48SPete Delaney #define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ 108d0b73b48SPete Delaney #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ 109d0b73b48SPete Delaney #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ 110d0b73b48SPete Delaney 111d0b73b48SPete Delaney 112d0b73b48SPete Delaney /*---------------------------------------------------------------------- 113d0b73b48SPete Delaney MISC 114d0b73b48SPete Delaney ----------------------------------------------------------------------*/ 115d0b73b48SPete Delaney 116d0b73b48SPete Delaney #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ 117d0b73b48SPete Delaney #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ 118d0b73b48SPete Delaney #define XCHAL_DATA_WIDTH 4 /* data width in bytes */ 119d0b73b48SPete Delaney /* In T1050, applies to selected core load and store instructions (see ISA): */ 120d0b73b48SPete Delaney #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ 121d0b73b48SPete Delaney #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ 122d0b73b48SPete Delaney #define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ 123d0b73b48SPete Delaney #define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ 124d0b73b48SPete Delaney 125d0b73b48SPete Delaney #define XCHAL_SW_VERSION 900001 /* sw version of this header */ 126d0b73b48SPete Delaney 127d0b73b48SPete Delaney #define XCHAL_CORE_ID "dc233c" /* alphanum core name 128d0b73b48SPete Delaney (CoreID) set in the Xtensa 129d0b73b48SPete Delaney Processor Generator */ 130d0b73b48SPete Delaney 131d0b73b48SPete Delaney #define XCHAL_CORE_DESCRIPTION "dc233c" 132d0b73b48SPete Delaney #define XCHAL_BUILD_UNIQUE_ID 0x00004B21 /* 22-bit sw build ID */ 133d0b73b48SPete Delaney 134d0b73b48SPete Delaney /* 135d0b73b48SPete Delaney * These definitions describe the hardware targeted by this software. 136d0b73b48SPete Delaney */ 137d0b73b48SPete Delaney #define XCHAL_HW_CONFIGID0 0xC56707FE /* ConfigID hi 32 bits*/ 138d0b73b48SPete Delaney #define XCHAL_HW_CONFIGID1 0x14404B21 /* ConfigID lo 32 bits*/ 139d0b73b48SPete Delaney #define XCHAL_HW_VERSION_NAME "LX4.0.1" /* full version name */ 140d0b73b48SPete Delaney #define XCHAL_HW_VERSION_MAJOR 2400 /* major ver# of targeted hw */ 141d0b73b48SPete Delaney #define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */ 142d0b73b48SPete Delaney #define XCHAL_HW_VERSION 240001 /* major*100+minor */ 143d0b73b48SPete Delaney #define XCHAL_HW_REL_LX4 1 144d0b73b48SPete Delaney #define XCHAL_HW_REL_LX4_0 1 145d0b73b48SPete Delaney #define XCHAL_HW_REL_LX4_0_1 1 146d0b73b48SPete Delaney #define XCHAL_HW_CONFIGID_RELIABLE 1 147d0b73b48SPete Delaney /* If software targets a *range* of hardware versions, these are the bounds: */ 148d0b73b48SPete Delaney #define XCHAL_HW_MIN_VERSION_MAJOR 2400 /* major v of earliest tgt hw */ 149d0b73b48SPete Delaney #define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */ 150d0b73b48SPete Delaney #define XCHAL_HW_MIN_VERSION 240001 /* earliest targeted hw */ 151d0b73b48SPete Delaney #define XCHAL_HW_MAX_VERSION_MAJOR 2400 /* major v of latest tgt hw */ 152d0b73b48SPete Delaney #define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */ 153d0b73b48SPete Delaney #define XCHAL_HW_MAX_VERSION 240001 /* latest targeted hw */ 154d0b73b48SPete Delaney 155d0b73b48SPete Delaney 156d0b73b48SPete Delaney /*---------------------------------------------------------------------- 157d0b73b48SPete Delaney CACHE 158d0b73b48SPete Delaney ----------------------------------------------------------------------*/ 159d0b73b48SPete Delaney 160d0b73b48SPete Delaney #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ 161d0b73b48SPete Delaney #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ 162d0b73b48SPete Delaney #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ 163d0b73b48SPete Delaney #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ 164d0b73b48SPete Delaney 165d0b73b48SPete Delaney #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ 166d0b73b48SPete Delaney #define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */ 167d0b73b48SPete Delaney 168d0b73b48SPete Delaney #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ 169d0b73b48SPete Delaney #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ 170d0b73b48SPete Delaney 171d0b73b48SPete Delaney #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ 172d0b73b48SPete Delaney 173d0b73b48SPete Delaney 174d0b73b48SPete Delaney 175d0b73b48SPete Delaney 176d0b73b48SPete Delaney /**************************************************************************** 177d0b73b48SPete Delaney Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 178d0b73b48SPete Delaney ****************************************************************************/ 179d0b73b48SPete Delaney 180d0b73b48SPete Delaney 181d0b73b48SPete Delaney #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 182d0b73b48SPete Delaney 183d0b73b48SPete Delaney /*---------------------------------------------------------------------- 184d0b73b48SPete Delaney CACHE 185d0b73b48SPete Delaney ----------------------------------------------------------------------*/ 186d0b73b48SPete Delaney 187d0b73b48SPete Delaney #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ 188d0b73b48SPete Delaney 189d0b73b48SPete Delaney /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ 190d0b73b48SPete Delaney 191d0b73b48SPete Delaney /* Number of cache sets in log2(lines per way): */ 192d0b73b48SPete Delaney #define XCHAL_ICACHE_SETWIDTH 7 193d0b73b48SPete Delaney #define XCHAL_DCACHE_SETWIDTH 7 194d0b73b48SPete Delaney 195d0b73b48SPete Delaney /* Cache set associativity (number of ways): */ 196d0b73b48SPete Delaney #define XCHAL_ICACHE_WAYS 4 197d0b73b48SPete Delaney #define XCHAL_DCACHE_WAYS 4 198d0b73b48SPete Delaney 199d0b73b48SPete Delaney /* Cache features: */ 200d0b73b48SPete Delaney #define XCHAL_ICACHE_LINE_LOCKABLE 1 201d0b73b48SPete Delaney #define XCHAL_DCACHE_LINE_LOCKABLE 1 202d0b73b48SPete Delaney #define XCHAL_ICACHE_ECC_PARITY 0 203d0b73b48SPete Delaney #define XCHAL_DCACHE_ECC_PARITY 0 204d0b73b48SPete Delaney 205d0b73b48SPete Delaney /* Cache access size in bytes (affects operation of SICW instruction): */ 206d0b73b48SPete Delaney #define XCHAL_ICACHE_ACCESS_SIZE 4 207d0b73b48SPete Delaney #define XCHAL_DCACHE_ACCESS_SIZE 4 208d0b73b48SPete Delaney 209d0b73b48SPete Delaney /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ 210d0b73b48SPete Delaney #define XCHAL_CA_BITS 4 211d0b73b48SPete Delaney 212d0b73b48SPete Delaney 213d0b73b48SPete Delaney /*---------------------------------------------------------------------- 214d0b73b48SPete Delaney INTERNAL I/D RAM/ROMs and XLMI 215d0b73b48SPete Delaney ----------------------------------------------------------------------*/ 216d0b73b48SPete Delaney 217d0b73b48SPete Delaney #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ 218d0b73b48SPete Delaney #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ 219d0b73b48SPete Delaney #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ 220d0b73b48SPete Delaney #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ 221d0b73b48SPete Delaney #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ 222d0b73b48SPete Delaney #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ 223d0b73b48SPete Delaney 224d0b73b48SPete Delaney #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ 225d0b73b48SPete Delaney 226d0b73b48SPete Delaney 227d0b73b48SPete Delaney /*---------------------------------------------------------------------- 228d0b73b48SPete Delaney INTERRUPTS and TIMERS 229d0b73b48SPete Delaney ----------------------------------------------------------------------*/ 230d0b73b48SPete Delaney 231d0b73b48SPete Delaney #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ 232d0b73b48SPete Delaney #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ 233d0b73b48SPete Delaney #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ 234d0b73b48SPete Delaney #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ 235d0b73b48SPete Delaney #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ 236d0b73b48SPete Delaney #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ 237d0b73b48SPete Delaney #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ 238d0b73b48SPete Delaney #define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ 239d0b73b48SPete Delaney #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels 240d0b73b48SPete Delaney (not including level zero) */ 241d0b73b48SPete Delaney #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ 242d0b73b48SPete Delaney /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ 243d0b73b48SPete Delaney 244d0b73b48SPete Delaney /* Masks of interrupts at each interrupt level: */ 245d0b73b48SPete Delaney #define XCHAL_INTLEVEL1_MASK 0x001F80FF 246d0b73b48SPete Delaney #define XCHAL_INTLEVEL2_MASK 0x00000100 247d0b73b48SPete Delaney #define XCHAL_INTLEVEL3_MASK 0x00200E00 248d0b73b48SPete Delaney #define XCHAL_INTLEVEL4_MASK 0x00001000 249d0b73b48SPete Delaney #define XCHAL_INTLEVEL5_MASK 0x00002000 250d0b73b48SPete Delaney #define XCHAL_INTLEVEL6_MASK 0x00000000 251d0b73b48SPete Delaney #define XCHAL_INTLEVEL7_MASK 0x00004000 252d0b73b48SPete Delaney 253d0b73b48SPete Delaney /* Masks of interrupts at each range 1..n of interrupt levels: */ 254d0b73b48SPete Delaney #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF 255d0b73b48SPete Delaney #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF 256d0b73b48SPete Delaney #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF 257d0b73b48SPete Delaney #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF 258d0b73b48SPete Delaney #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF 259d0b73b48SPete Delaney #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF 260d0b73b48SPete Delaney #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF 261d0b73b48SPete Delaney 262d0b73b48SPete Delaney /* Level of each interrupt: */ 263d0b73b48SPete Delaney #define XCHAL_INT0_LEVEL 1 264d0b73b48SPete Delaney #define XCHAL_INT1_LEVEL 1 265d0b73b48SPete Delaney #define XCHAL_INT2_LEVEL 1 266d0b73b48SPete Delaney #define XCHAL_INT3_LEVEL 1 267d0b73b48SPete Delaney #define XCHAL_INT4_LEVEL 1 268d0b73b48SPete Delaney #define XCHAL_INT5_LEVEL 1 269d0b73b48SPete Delaney #define XCHAL_INT6_LEVEL 1 270d0b73b48SPete Delaney #define XCHAL_INT7_LEVEL 1 271d0b73b48SPete Delaney #define XCHAL_INT8_LEVEL 2 272d0b73b48SPete Delaney #define XCHAL_INT9_LEVEL 3 273d0b73b48SPete Delaney #define XCHAL_INT10_LEVEL 3 274d0b73b48SPete Delaney #define XCHAL_INT11_LEVEL 3 275d0b73b48SPete Delaney #define XCHAL_INT12_LEVEL 4 276d0b73b48SPete Delaney #define XCHAL_INT13_LEVEL 5 277d0b73b48SPete Delaney #define XCHAL_INT14_LEVEL 7 278d0b73b48SPete Delaney #define XCHAL_INT15_LEVEL 1 279d0b73b48SPete Delaney #define XCHAL_INT16_LEVEL 1 280d0b73b48SPete Delaney #define XCHAL_INT17_LEVEL 1 281d0b73b48SPete Delaney #define XCHAL_INT18_LEVEL 1 282d0b73b48SPete Delaney #define XCHAL_INT19_LEVEL 1 283d0b73b48SPete Delaney #define XCHAL_INT20_LEVEL 1 284d0b73b48SPete Delaney #define XCHAL_INT21_LEVEL 3 285d0b73b48SPete Delaney #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ 286d0b73b48SPete Delaney #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ 287d0b73b48SPete Delaney #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with 288d0b73b48SPete Delaney EXCSAVE/EPS/EPC_n, RFI n) */ 289d0b73b48SPete Delaney 290d0b73b48SPete Delaney /* Type of each interrupt: */ 291d0b73b48SPete Delaney #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 292d0b73b48SPete Delaney #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 293d0b73b48SPete Delaney #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 294d0b73b48SPete Delaney #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 295d0b73b48SPete Delaney #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 296d0b73b48SPete Delaney #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 297d0b73b48SPete Delaney #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER 298d0b73b48SPete Delaney #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE 299d0b73b48SPete Delaney #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 300d0b73b48SPete Delaney #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 301d0b73b48SPete Delaney #define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER 302d0b73b48SPete Delaney #define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE 303d0b73b48SPete Delaney #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 304d0b73b48SPete Delaney #define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER 305d0b73b48SPete Delaney #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI 306d0b73b48SPete Delaney #define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE 307d0b73b48SPete Delaney #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE 308d0b73b48SPete Delaney #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE 309d0b73b48SPete Delaney #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE 310d0b73b48SPete Delaney #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE 311d0b73b48SPete Delaney #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE 312d0b73b48SPete Delaney #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE 313d0b73b48SPete Delaney 314d0b73b48SPete Delaney /* Masks of interrupts for each type of interrupt: */ 315d0b73b48SPete Delaney #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 316d0b73b48SPete Delaney #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 317d0b73b48SPete Delaney #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000 318d0b73b48SPete Delaney #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F 319d0b73b48SPete Delaney #define XCHAL_INTTYPE_MASK_TIMER 0x00002440 320d0b73b48SPete Delaney #define XCHAL_INTTYPE_MASK_NMI 0x00004000 321d0b73b48SPete Delaney #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 322d0b73b48SPete Delaney 323d0b73b48SPete Delaney /* Interrupt numbers assigned to specific interrupt sources: */ 324d0b73b48SPete Delaney #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ 325d0b73b48SPete Delaney #define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ 326d0b73b48SPete Delaney #define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ 327d0b73b48SPete Delaney #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED 328d0b73b48SPete Delaney #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ 329d0b73b48SPete Delaney 330d0b73b48SPete Delaney /* Interrupt numbers for levels at which only one interrupt is configured: */ 331d0b73b48SPete Delaney #define XCHAL_INTLEVEL2_NUM 8 332d0b73b48SPete Delaney #define XCHAL_INTLEVEL4_NUM 12 333d0b73b48SPete Delaney #define XCHAL_INTLEVEL5_NUM 13 334d0b73b48SPete Delaney #define XCHAL_INTLEVEL7_NUM 14 335d0b73b48SPete Delaney /* (There are many interrupts each at level(s) 1, 3.) */ 336d0b73b48SPete Delaney 337d0b73b48SPete Delaney 338d0b73b48SPete Delaney /* 339d0b73b48SPete Delaney * External interrupt vectors/levels. 340d0b73b48SPete Delaney * These macros describe how Xtensa processor interrupt numbers 341d0b73b48SPete Delaney * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) 342d0b73b48SPete Delaney * map to external BInterrupt<n> pins, for those interrupts 343d0b73b48SPete Delaney * configured as external (level-triggered, edge-triggered, or NMI). 344d0b73b48SPete Delaney * See the Xtensa processor databook for more details. 345d0b73b48SPete Delaney */ 346d0b73b48SPete Delaney 347d0b73b48SPete Delaney /* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ 348d0b73b48SPete Delaney #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ 349d0b73b48SPete Delaney #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ 350d0b73b48SPete Delaney #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ 351d0b73b48SPete Delaney #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ 352d0b73b48SPete Delaney #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ 353d0b73b48SPete Delaney #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ 354d0b73b48SPete Delaney #define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ 355d0b73b48SPete Delaney #define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ 356d0b73b48SPete Delaney #define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ 357d0b73b48SPete Delaney #define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ 358d0b73b48SPete Delaney #define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ 359d0b73b48SPete Delaney #define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ 360d0b73b48SPete Delaney #define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ 361d0b73b48SPete Delaney #define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ 362d0b73b48SPete Delaney #define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ 363d0b73b48SPete Delaney #define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ 364d0b73b48SPete Delaney #define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ 365d0b73b48SPete Delaney 366d0b73b48SPete Delaney 367d0b73b48SPete Delaney /*---------------------------------------------------------------------- 368d0b73b48SPete Delaney EXCEPTIONS and VECTORS 369d0b73b48SPete Delaney ----------------------------------------------------------------------*/ 370d0b73b48SPete Delaney 371d0b73b48SPete Delaney #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture 372d0b73b48SPete Delaney number: 1 == XEA1 (old) 373d0b73b48SPete Delaney 2 == XEA2 (new) 374d0b73b48SPete Delaney 0 == XEAX (extern) or TX */ 375d0b73b48SPete Delaney #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ 376d0b73b48SPete Delaney #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ 377d0b73b48SPete Delaney #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ 378d0b73b48SPete Delaney #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ 379d0b73b48SPete Delaney #define XCHAL_HAVE_HALT 0 /* halt architecture option */ 380d0b73b48SPete Delaney #define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ 381d0b73b48SPete Delaney #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ 382d0b73b48SPete Delaney #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ 383d0b73b48SPete Delaney #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ 384d0b73b48SPete Delaney #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ 385d0b73b48SPete Delaney #define XCHAL_VECBASE_RESET_PADDR 0x00002000 386d0b73b48SPete Delaney #define XCHAL_RESET_VECBASE_OVERLAP 0 387d0b73b48SPete Delaney 388d0b73b48SPete Delaney #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 389d0b73b48SPete Delaney #define XCHAL_RESET_VECTOR0_PADDR 0xFE000000 390d0b73b48SPete Delaney #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 391d0b73b48SPete Delaney #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 392d0b73b48SPete Delaney #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 393d0b73b48SPete Delaney #define XCHAL_RESET_VECTOR_PADDR 0xFE000000 394d0b73b48SPete Delaney #define XCHAL_USER_VECOFS 0x00000340 395d0b73b48SPete Delaney #define XCHAL_USER_VECTOR_VADDR 0x00002340 396d0b73b48SPete Delaney #define XCHAL_USER_VECTOR_PADDR 0x00002340 397d0b73b48SPete Delaney #define XCHAL_KERNEL_VECOFS 0x00000300 398d0b73b48SPete Delaney #define XCHAL_KERNEL_VECTOR_VADDR 0x00002300 399d0b73b48SPete Delaney #define XCHAL_KERNEL_VECTOR_PADDR 0x00002300 400d0b73b48SPete Delaney #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 401d0b73b48SPete Delaney #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0 402d0b73b48SPete Delaney #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0 403d0b73b48SPete Delaney #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 404d0b73b48SPete Delaney #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 405d0b73b48SPete Delaney #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 406d0b73b48SPete Delaney #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 407d0b73b48SPete Delaney #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 408d0b73b48SPete Delaney #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 409d0b73b48SPete Delaney #define XCHAL_WINDOW_VECTORS_VADDR 0x00002000 410d0b73b48SPete Delaney #define XCHAL_WINDOW_VECTORS_PADDR 0x00002000 411d0b73b48SPete Delaney #define XCHAL_INTLEVEL2_VECOFS 0x00000180 412d0b73b48SPete Delaney #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180 413d0b73b48SPete Delaney #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180 414d0b73b48SPete Delaney #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 415d0b73b48SPete Delaney #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0 416d0b73b48SPete Delaney #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0 417d0b73b48SPete Delaney #define XCHAL_INTLEVEL4_VECOFS 0x00000200 418d0b73b48SPete Delaney #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200 419d0b73b48SPete Delaney #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200 420d0b73b48SPete Delaney #define XCHAL_INTLEVEL5_VECOFS 0x00000240 421d0b73b48SPete Delaney #define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240 422d0b73b48SPete Delaney #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240 423d0b73b48SPete Delaney #define XCHAL_INTLEVEL6_VECOFS 0x00000280 424d0b73b48SPete Delaney #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280 425d0b73b48SPete Delaney #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280 426d0b73b48SPete Delaney #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS 427d0b73b48SPete Delaney #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR 428d0b73b48SPete Delaney #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR 429d0b73b48SPete Delaney #define XCHAL_NMI_VECOFS 0x000002C0 430d0b73b48SPete Delaney #define XCHAL_NMI_VECTOR_VADDR 0x000022C0 431d0b73b48SPete Delaney #define XCHAL_NMI_VECTOR_PADDR 0x000022C0 432d0b73b48SPete Delaney #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS 433d0b73b48SPete Delaney #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR 434d0b73b48SPete Delaney #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR 435d0b73b48SPete Delaney 436d0b73b48SPete Delaney 437d0b73b48SPete Delaney /*---------------------------------------------------------------------- 438d0b73b48SPete Delaney DEBUG 439d0b73b48SPete Delaney ----------------------------------------------------------------------*/ 440d0b73b48SPete Delaney 441d0b73b48SPete Delaney #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ 442d0b73b48SPete Delaney #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ 443d0b73b48SPete Delaney #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ 444d0b73b48SPete Delaney #define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ 445d0b73b48SPete Delaney 446d0b73b48SPete Delaney 447d0b73b48SPete Delaney /*---------------------------------------------------------------------- 448d0b73b48SPete Delaney MMU 449d0b73b48SPete Delaney ----------------------------------------------------------------------*/ 450d0b73b48SPete Delaney 451d0b73b48SPete Delaney /* See core-matmap.h header file for more details. */ 452d0b73b48SPete Delaney 453d0b73b48SPete Delaney #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ 454d0b73b48SPete Delaney #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ 455d0b73b48SPete Delaney #define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */ 456d0b73b48SPete Delaney #define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ 457d0b73b48SPete Delaney #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ 458d0b73b48SPete Delaney #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ 459d0b73b48SPete Delaney #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ 460d0b73b48SPete Delaney #define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table 461d0b73b48SPete Delaney [autorefill] and protection) 462d0b73b48SPete Delaney usable for an MMU-based OS */ 463d0b73b48SPete Delaney /* If none of the above last 4 are set, it's a custom TLB configuration. */ 464d0b73b48SPete Delaney #define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 465d0b73b48SPete Delaney #define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 466d0b73b48SPete Delaney 467d0b73b48SPete Delaney #define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ 468d0b73b48SPete Delaney #define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ 469d0b73b48SPete Delaney #define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */ 470d0b73b48SPete Delaney 471d0b73b48SPete Delaney #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 472d0b73b48SPete Delaney 473d0b73b48SPete Delaney 474d0b73b48SPete Delaney #endif /* _XTENSA_CORE_CONFIGURATION_H */ 475d0b73b48SPete Delaney 476