19da8320bSMax Filippov /* 29da8320bSMax Filippov * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 39da8320bSMax Filippov * processor CORE configuration 49da8320bSMax Filippov * 59da8320bSMax Filippov * See <xtensa/config/core.h>, which includes this file, for more details. 69da8320bSMax Filippov */ 79da8320bSMax Filippov 89da8320bSMax Filippov /* Xtensa processor core configuration information. 99da8320bSMax Filippov 109da8320bSMax Filippov Copyright (c) 1999-2014 Tensilica Inc. 119da8320bSMax Filippov 129da8320bSMax Filippov Permission is hereby granted, free of charge, to any person obtaining 139da8320bSMax Filippov a copy of this software and associated documentation files (the 149da8320bSMax Filippov "Software"), to deal in the Software without restriction, including 159da8320bSMax Filippov without limitation the rights to use, copy, modify, merge, publish, 169da8320bSMax Filippov distribute, sublicense, and/or sell copies of the Software, and to 179da8320bSMax Filippov permit persons to whom the Software is furnished to do so, subject to 189da8320bSMax Filippov the following conditions: 199da8320bSMax Filippov 209da8320bSMax Filippov The above copyright notice and this permission notice shall be included 219da8320bSMax Filippov in all copies or substantial portions of the Software. 229da8320bSMax Filippov 239da8320bSMax Filippov THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 249da8320bSMax Filippov EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 259da8320bSMax Filippov MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 269da8320bSMax Filippov IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 279da8320bSMax Filippov CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 289da8320bSMax Filippov TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 299da8320bSMax Filippov SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 309da8320bSMax Filippov 319da8320bSMax Filippov #ifndef _XTENSA_CORE_CONFIGURATION_H 329da8320bSMax Filippov #define _XTENSA_CORE_CONFIGURATION_H 339da8320bSMax Filippov 349da8320bSMax Filippov 359da8320bSMax Filippov /**************************************************************************** 369da8320bSMax Filippov Parameters Useful for Any Code, USER or PRIVILEGED 379da8320bSMax Filippov ****************************************************************************/ 389da8320bSMax Filippov 399da8320bSMax Filippov /* 409da8320bSMax Filippov * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is 419da8320bSMax Filippov * configured, and a value of 0 otherwise. These macros are always defined. 429da8320bSMax Filippov */ 439da8320bSMax Filippov 449da8320bSMax Filippov 459da8320bSMax Filippov /*---------------------------------------------------------------------- 469da8320bSMax Filippov ISA 479da8320bSMax Filippov ----------------------------------------------------------------------*/ 489da8320bSMax Filippov 499da8320bSMax Filippov #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 509da8320bSMax Filippov #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ 519da8320bSMax Filippov #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ 529da8320bSMax Filippov #define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ 539da8320bSMax Filippov #define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ 549da8320bSMax Filippov #define XCHAL_HAVE_DEBUG 1 /* debug option */ 559da8320bSMax Filippov #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 569da8320bSMax Filippov #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 579da8320bSMax Filippov #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ 589da8320bSMax Filippov #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ 599da8320bSMax Filippov #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ 609da8320bSMax Filippov #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ 619da8320bSMax Filippov #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ 629da8320bSMax Filippov #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ 639da8320bSMax Filippov #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ 649da8320bSMax Filippov #define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ 659da8320bSMax Filippov #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ 669da8320bSMax Filippov #define XCHAL_HAVE_L32R 1 /* L32R instruction */ 679da8320bSMax Filippov #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ 689da8320bSMax Filippov #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ 699da8320bSMax Filippov #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ 709da8320bSMax Filippov #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ 719da8320bSMax Filippov #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ 729da8320bSMax Filippov #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ 739da8320bSMax Filippov #define XCHAL_HAVE_ABS 1 /* ABS instruction */ 749da8320bSMax Filippov /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ 759da8320bSMax Filippov /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ 769da8320bSMax Filippov #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ 779da8320bSMax Filippov #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ 789da8320bSMax Filippov #define XCHAL_HAVE_SPECULATION 0 /* speculation */ 799da8320bSMax Filippov #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ 809da8320bSMax Filippov #define XCHAL_NUM_CONTEXTS 1 /* */ 819da8320bSMax Filippov #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ 829da8320bSMax Filippov #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ 839da8320bSMax Filippov #define XCHAL_HAVE_PRID 1 /* processor ID register */ 849da8320bSMax Filippov #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ 859da8320bSMax Filippov #define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ 869da8320bSMax Filippov #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ 879da8320bSMax Filippov #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ 889da8320bSMax Filippov #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ 899da8320bSMax Filippov #define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ 909da8320bSMax Filippov #define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ 919da8320bSMax Filippov #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ 929da8320bSMax Filippov #define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ 939da8320bSMax Filippov #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ 949da8320bSMax Filippov #define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ 959da8320bSMax Filippov #define XCHAL_HAVE_MAC16 1 /* MAC16 package */ 969da8320bSMax Filippov #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ 979da8320bSMax Filippov #define XCHAL_HAVE_FP 0 /* single prec floating point */ 989da8320bSMax Filippov #define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ 999da8320bSMax Filippov #define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ 1009da8320bSMax Filippov #define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ 1019da8320bSMax Filippov #define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ 1029da8320bSMax Filippov #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ 1039da8320bSMax Filippov #define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ 1049da8320bSMax Filippov #define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ 1059da8320bSMax Filippov #define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ 1069da8320bSMax Filippov #define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ 1079da8320bSMax Filippov #define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */ 1089da8320bSMax Filippov #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ 1099da8320bSMax Filippov #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ 1109da8320bSMax Filippov #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ 1119da8320bSMax Filippov #define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */ 1129da8320bSMax Filippov #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ 1139da8320bSMax Filippov #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ 1149da8320bSMax Filippov #define XCHAL_HAVE_HIFI_MINI 0 1159da8320bSMax Filippov #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ 1169da8320bSMax Filippov #define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ 1179da8320bSMax Filippov #define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ 1189da8320bSMax Filippov #define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ 1199da8320bSMax Filippov #define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ 1209da8320bSMax Filippov #define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ 1219da8320bSMax Filippov #define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ 1229da8320bSMax Filippov #define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ 1239da8320bSMax Filippov #define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ 1249da8320bSMax Filippov #define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ 1259da8320bSMax Filippov #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ 1269da8320bSMax Filippov #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ 1279da8320bSMax Filippov #define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ 1289da8320bSMax Filippov 1299da8320bSMax Filippov 1309da8320bSMax Filippov /*---------------------------------------------------------------------- 1319da8320bSMax Filippov MISC 1329da8320bSMax Filippov ----------------------------------------------------------------------*/ 1339da8320bSMax Filippov 1349da8320bSMax Filippov #define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ 1359da8320bSMax Filippov #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ 1369da8320bSMax Filippov #define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ 1379da8320bSMax Filippov #define XCHAL_DATA_WIDTH 8 /* data width in bytes */ 1389da8320bSMax Filippov #define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay 1399da8320bSMax Filippov (1 = 5-stage, 2 = 7-stage) */ 1409da8320bSMax Filippov /* In T1050, applies to selected core load and store instructions (see ISA): */ 1419da8320bSMax Filippov #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ 1429da8320bSMax Filippov #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ 1439da8320bSMax Filippov #define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ 1449da8320bSMax Filippov #define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ 1459da8320bSMax Filippov 1469da8320bSMax Filippov #define XCHAL_SW_VERSION 1000004 /* sw version of this header */ 1479da8320bSMax Filippov 1489da8320bSMax Filippov #define XCHAL_CORE_ID "test_kc705_hifi" /* alphanum core name 1499da8320bSMax Filippov (CoreID) set in the Xtensa 1509da8320bSMax Filippov Processor Generator */ 1519da8320bSMax Filippov 1529da8320bSMax Filippov #define XCHAL_BUILD_UNIQUE_ID 0x0004983D /* 22-bit sw build ID */ 1539da8320bSMax Filippov 1549da8320bSMax Filippov /* 1559da8320bSMax Filippov * These definitions describe the hardware targeted by this software. 1569da8320bSMax Filippov */ 1579da8320bSMax Filippov #define XCHAL_HW_CONFIGID0 0xC1B3FFFE /* ConfigID hi 32 bits*/ 1589da8320bSMax Filippov #define XCHAL_HW_CONFIGID1 0x1904983D /* ConfigID lo 32 bits*/ 1599da8320bSMax Filippov #define XCHAL_HW_VERSION_NAME "LX5.0.4" /* full version name */ 1609da8320bSMax Filippov #define XCHAL_HW_VERSION_MAJOR 2500 /* major ver# of targeted hw */ 1619da8320bSMax Filippov #define XCHAL_HW_VERSION_MINOR 4 /* minor ver# of targeted hw */ 1629da8320bSMax Filippov #define XCHAL_HW_VERSION 250004 /* major*100+minor */ 1639da8320bSMax Filippov #define XCHAL_HW_REL_LX5 1 1649da8320bSMax Filippov #define XCHAL_HW_REL_LX5_0 1 1659da8320bSMax Filippov #define XCHAL_HW_REL_LX5_0_4 1 1669da8320bSMax Filippov #define XCHAL_HW_CONFIGID_RELIABLE 1 1679da8320bSMax Filippov /* If software targets a *range* of hardware versions, these are the bounds: */ 1689da8320bSMax Filippov #define XCHAL_HW_MIN_VERSION_MAJOR 2500 /* major v of earliest tgt hw */ 1699da8320bSMax Filippov #define XCHAL_HW_MIN_VERSION_MINOR 4 /* minor v of earliest tgt hw */ 1709da8320bSMax Filippov #define XCHAL_HW_MIN_VERSION 250004 /* earliest targeted hw */ 1719da8320bSMax Filippov #define XCHAL_HW_MAX_VERSION_MAJOR 2500 /* major v of latest tgt hw */ 1729da8320bSMax Filippov #define XCHAL_HW_MAX_VERSION_MINOR 4 /* minor v of latest tgt hw */ 1739da8320bSMax Filippov #define XCHAL_HW_MAX_VERSION 250004 /* latest targeted hw */ 1749da8320bSMax Filippov 1759da8320bSMax Filippov 1769da8320bSMax Filippov /*---------------------------------------------------------------------- 1779da8320bSMax Filippov CACHE 1789da8320bSMax Filippov ----------------------------------------------------------------------*/ 1799da8320bSMax Filippov 1809da8320bSMax Filippov #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ 1819da8320bSMax Filippov #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ 1829da8320bSMax Filippov #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ 1839da8320bSMax Filippov #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ 1849da8320bSMax Filippov 1859da8320bSMax Filippov #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ 1869da8320bSMax Filippov #define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */ 1879da8320bSMax Filippov 1889da8320bSMax Filippov #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ 1899da8320bSMax Filippov #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ 1909da8320bSMax Filippov 1919da8320bSMax Filippov #define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ 1929da8320bSMax Filippov #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ 1939da8320bSMax Filippov #define XCHAL_PREFETCH_CASTOUT_LINES 1 /* dcache pref. castout bufsz */ 1949da8320bSMax Filippov 1959da8320bSMax Filippov 1969da8320bSMax Filippov 1979da8320bSMax Filippov 1989da8320bSMax Filippov /**************************************************************************** 1999da8320bSMax Filippov Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 2009da8320bSMax Filippov ****************************************************************************/ 2019da8320bSMax Filippov 2029da8320bSMax Filippov 2039da8320bSMax Filippov #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 2049da8320bSMax Filippov 2059da8320bSMax Filippov /*---------------------------------------------------------------------- 2069da8320bSMax Filippov CACHE 2079da8320bSMax Filippov ----------------------------------------------------------------------*/ 2089da8320bSMax Filippov 2099da8320bSMax Filippov #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ 2109da8320bSMax Filippov 2119da8320bSMax Filippov /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ 2129da8320bSMax Filippov 2139da8320bSMax Filippov /* Number of cache sets in log2(lines per way): */ 2149da8320bSMax Filippov #define XCHAL_ICACHE_SETWIDTH 7 2159da8320bSMax Filippov #define XCHAL_DCACHE_SETWIDTH 7 2169da8320bSMax Filippov 2179da8320bSMax Filippov /* Cache set associativity (number of ways): */ 2189da8320bSMax Filippov #define XCHAL_ICACHE_WAYS 4 2199da8320bSMax Filippov #define XCHAL_DCACHE_WAYS 4 2209da8320bSMax Filippov 2219da8320bSMax Filippov /* Cache features: */ 2229da8320bSMax Filippov #define XCHAL_ICACHE_LINE_LOCKABLE 1 2239da8320bSMax Filippov #define XCHAL_DCACHE_LINE_LOCKABLE 1 2249da8320bSMax Filippov #define XCHAL_ICACHE_ECC_PARITY 0 2259da8320bSMax Filippov #define XCHAL_DCACHE_ECC_PARITY 0 2269da8320bSMax Filippov 2279da8320bSMax Filippov /* Cache access size in bytes (affects operation of SICW instruction): */ 2289da8320bSMax Filippov #define XCHAL_ICACHE_ACCESS_SIZE 8 2299da8320bSMax Filippov #define XCHAL_DCACHE_ACCESS_SIZE 8 2309da8320bSMax Filippov 2319da8320bSMax Filippov #define XCHAL_DCACHE_BANKS 1 /* number of banks */ 2329da8320bSMax Filippov 2339da8320bSMax Filippov /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ 2349da8320bSMax Filippov #define XCHAL_CA_BITS 4 2359da8320bSMax Filippov 2369da8320bSMax Filippov 2379da8320bSMax Filippov /*---------------------------------------------------------------------- 2389da8320bSMax Filippov INTERNAL I/D RAM/ROMs and XLMI 2399da8320bSMax Filippov ----------------------------------------------------------------------*/ 2409da8320bSMax Filippov 2419da8320bSMax Filippov #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ 2429da8320bSMax Filippov #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ 2439da8320bSMax Filippov #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ 2449da8320bSMax Filippov #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ 2459da8320bSMax Filippov #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ 2469da8320bSMax Filippov #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ 2479da8320bSMax Filippov 2489da8320bSMax Filippov #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ 2499da8320bSMax Filippov 2509da8320bSMax Filippov 2519da8320bSMax Filippov /*---------------------------------------------------------------------- 2529da8320bSMax Filippov INTERRUPTS and TIMERS 2539da8320bSMax Filippov ----------------------------------------------------------------------*/ 2549da8320bSMax Filippov 2559da8320bSMax Filippov #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ 2569da8320bSMax Filippov #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ 2579da8320bSMax Filippov #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ 2589da8320bSMax Filippov #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ 2599da8320bSMax Filippov #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ 2609da8320bSMax Filippov #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ 2619da8320bSMax Filippov #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ 2629da8320bSMax Filippov #define XCHAL_NUM_EXTINTERRUPTS 16 /* num of external interrupts */ 2639da8320bSMax Filippov #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels 2649da8320bSMax Filippov (not including level zero) */ 2659da8320bSMax Filippov #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ 2669da8320bSMax Filippov /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ 2679da8320bSMax Filippov 2689da8320bSMax Filippov /* Masks of interrupts at each interrupt level: */ 2699da8320bSMax Filippov #define XCHAL_INTLEVEL1_MASK 0x001F00BF 2709da8320bSMax Filippov #define XCHAL_INTLEVEL2_MASK 0x00000140 2719da8320bSMax Filippov #define XCHAL_INTLEVEL3_MASK 0x00200E00 2729da8320bSMax Filippov #define XCHAL_INTLEVEL4_MASK 0x00009000 2739da8320bSMax Filippov #define XCHAL_INTLEVEL5_MASK 0x00002000 2749da8320bSMax Filippov #define XCHAL_INTLEVEL6_MASK 0x00000000 2759da8320bSMax Filippov #define XCHAL_INTLEVEL7_MASK 0x00004000 2769da8320bSMax Filippov 2779da8320bSMax Filippov /* Masks of interrupts at each range 1..n of interrupt levels: */ 2789da8320bSMax Filippov #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F00BF 2799da8320bSMax Filippov #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F01FF 2809da8320bSMax Filippov #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F0FFF 2819da8320bSMax Filippov #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF 2829da8320bSMax Filippov #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF 2839da8320bSMax Filippov #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF 2849da8320bSMax Filippov #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF 2859da8320bSMax Filippov 2869da8320bSMax Filippov /* Level of each interrupt: */ 2879da8320bSMax Filippov #define XCHAL_INT0_LEVEL 1 2889da8320bSMax Filippov #define XCHAL_INT1_LEVEL 1 2899da8320bSMax Filippov #define XCHAL_INT2_LEVEL 1 2909da8320bSMax Filippov #define XCHAL_INT3_LEVEL 1 2919da8320bSMax Filippov #define XCHAL_INT4_LEVEL 1 2929da8320bSMax Filippov #define XCHAL_INT5_LEVEL 1 2939da8320bSMax Filippov #define XCHAL_INT6_LEVEL 2 2949da8320bSMax Filippov #define XCHAL_INT7_LEVEL 1 2959da8320bSMax Filippov #define XCHAL_INT8_LEVEL 2 2969da8320bSMax Filippov #define XCHAL_INT9_LEVEL 3 2979da8320bSMax Filippov #define XCHAL_INT10_LEVEL 3 2989da8320bSMax Filippov #define XCHAL_INT11_LEVEL 3 2999da8320bSMax Filippov #define XCHAL_INT12_LEVEL 4 3009da8320bSMax Filippov #define XCHAL_INT13_LEVEL 5 3019da8320bSMax Filippov #define XCHAL_INT14_LEVEL 7 3029da8320bSMax Filippov #define XCHAL_INT15_LEVEL 4 3039da8320bSMax Filippov #define XCHAL_INT16_LEVEL 1 3049da8320bSMax Filippov #define XCHAL_INT17_LEVEL 1 3059da8320bSMax Filippov #define XCHAL_INT18_LEVEL 1 3069da8320bSMax Filippov #define XCHAL_INT19_LEVEL 1 3079da8320bSMax Filippov #define XCHAL_INT20_LEVEL 1 3089da8320bSMax Filippov #define XCHAL_INT21_LEVEL 3 3099da8320bSMax Filippov #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ 3109da8320bSMax Filippov #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ 3119da8320bSMax Filippov #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with 3129da8320bSMax Filippov EXCSAVE/EPS/EPC_n, RFI n) */ 3139da8320bSMax Filippov 3149da8320bSMax Filippov /* Type of each interrupt: */ 3159da8320bSMax Filippov #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3169da8320bSMax Filippov #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3179da8320bSMax Filippov #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3189da8320bSMax Filippov #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3199da8320bSMax Filippov #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3209da8320bSMax Filippov #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3219da8320bSMax Filippov #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER 3229da8320bSMax Filippov #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE 3239da8320bSMax Filippov #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3249da8320bSMax Filippov #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3259da8320bSMax Filippov #define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER 3269da8320bSMax Filippov #define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE 3279da8320bSMax Filippov #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3289da8320bSMax Filippov #define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER 3299da8320bSMax Filippov #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI 3309da8320bSMax Filippov #define XCHAL_INT15_TYPE XTHAL_INTTYPE_PROFILING 3319da8320bSMax Filippov #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE 3329da8320bSMax Filippov #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE 3339da8320bSMax Filippov #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE 3349da8320bSMax Filippov #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE 3359da8320bSMax Filippov #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE 3369da8320bSMax Filippov #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE 3379da8320bSMax Filippov 3389da8320bSMax Filippov /* Masks of interrupts for each type of interrupt: */ 3399da8320bSMax Filippov #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 3409da8320bSMax Filippov #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 3419da8320bSMax Filippov #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F0000 3429da8320bSMax Filippov #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F 3439da8320bSMax Filippov #define XCHAL_INTTYPE_MASK_TIMER 0x00002440 3449da8320bSMax Filippov #define XCHAL_INTTYPE_MASK_NMI 0x00004000 3459da8320bSMax Filippov #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 3469da8320bSMax Filippov #define XCHAL_INTTYPE_MASK_PROFILING 0x00008000 3479da8320bSMax Filippov 3489da8320bSMax Filippov /* Interrupt numbers assigned to specific interrupt sources: */ 3499da8320bSMax Filippov #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ 3509da8320bSMax Filippov #define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ 3519da8320bSMax Filippov #define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ 3529da8320bSMax Filippov #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED 3539da8320bSMax Filippov #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ 3549da8320bSMax Filippov #define XCHAL_PROFILING_INTERRUPT 15 /* profiling interrupt */ 3559da8320bSMax Filippov 3569da8320bSMax Filippov /* Interrupt numbers for levels at which only one interrupt is configured: */ 3579da8320bSMax Filippov #define XCHAL_INTLEVEL5_NUM 13 3589da8320bSMax Filippov #define XCHAL_INTLEVEL7_NUM 14 3599da8320bSMax Filippov /* (There are many interrupts each at level(s) 1, 2, 3, 4.) */ 3609da8320bSMax Filippov 3619da8320bSMax Filippov 3629da8320bSMax Filippov /* 3639da8320bSMax Filippov * External interrupt mapping. 3649da8320bSMax Filippov * These macros describe how Xtensa processor interrupt numbers 3659da8320bSMax Filippov * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) 3669da8320bSMax Filippov * map to external BInterrupt<n> pins, for those interrupts 3679da8320bSMax Filippov * configured as external (level-triggered, edge-triggered, or NMI). 3689da8320bSMax Filippov * See the Xtensa processor databook for more details. 3699da8320bSMax Filippov */ 3709da8320bSMax Filippov 3719da8320bSMax Filippov /* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ 3729da8320bSMax Filippov #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ 3739da8320bSMax Filippov #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ 3749da8320bSMax Filippov #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ 3759da8320bSMax Filippov #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ 3769da8320bSMax Filippov #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ 3779da8320bSMax Filippov #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ 3789da8320bSMax Filippov #define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ 3799da8320bSMax Filippov #define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ 3809da8320bSMax Filippov #define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ 3819da8320bSMax Filippov #define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ 3829da8320bSMax Filippov #define XCHAL_EXTINT10_NUM 16 /* (intlevel 1) */ 3839da8320bSMax Filippov #define XCHAL_EXTINT11_NUM 17 /* (intlevel 1) */ 3849da8320bSMax Filippov #define XCHAL_EXTINT12_NUM 18 /* (intlevel 1) */ 3859da8320bSMax Filippov #define XCHAL_EXTINT13_NUM 19 /* (intlevel 1) */ 3869da8320bSMax Filippov #define XCHAL_EXTINT14_NUM 20 /* (intlevel 1) */ 3879da8320bSMax Filippov #define XCHAL_EXTINT15_NUM 21 /* (intlevel 3) */ 3889da8320bSMax Filippov /* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ 3899da8320bSMax Filippov #define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ 3909da8320bSMax Filippov #define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ 3919da8320bSMax Filippov #define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ 3929da8320bSMax Filippov #define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ 3939da8320bSMax Filippov #define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ 3949da8320bSMax Filippov #define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ 3959da8320bSMax Filippov #define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */ 3969da8320bSMax Filippov #define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */ 3979da8320bSMax Filippov #define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */ 3989da8320bSMax Filippov #define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */ 3999da8320bSMax Filippov #define XCHAL_INT16_EXTNUM 10 /* (intlevel 1) */ 4009da8320bSMax Filippov #define XCHAL_INT17_EXTNUM 11 /* (intlevel 1) */ 4019da8320bSMax Filippov #define XCHAL_INT18_EXTNUM 12 /* (intlevel 1) */ 4029da8320bSMax Filippov #define XCHAL_INT19_EXTNUM 13 /* (intlevel 1) */ 4039da8320bSMax Filippov #define XCHAL_INT20_EXTNUM 14 /* (intlevel 1) */ 4049da8320bSMax Filippov #define XCHAL_INT21_EXTNUM 15 /* (intlevel 3) */ 4059da8320bSMax Filippov 4069da8320bSMax Filippov 4079da8320bSMax Filippov /*---------------------------------------------------------------------- 4089da8320bSMax Filippov EXCEPTIONS and VECTORS 4099da8320bSMax Filippov ----------------------------------------------------------------------*/ 4109da8320bSMax Filippov 4119da8320bSMax Filippov #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture 4129da8320bSMax Filippov number: 1 == XEA1 (old) 4139da8320bSMax Filippov 2 == XEA2 (new) 4149da8320bSMax Filippov 0 == XEAX (extern) or TX */ 4159da8320bSMax Filippov #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ 4169da8320bSMax Filippov #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ 4179da8320bSMax Filippov #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ 4189da8320bSMax Filippov #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ 4199da8320bSMax Filippov #define XCHAL_HAVE_HALT 0 /* halt architecture option */ 4209da8320bSMax Filippov #define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ 4219da8320bSMax Filippov #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ 4229da8320bSMax Filippov #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ 4239da8320bSMax Filippov #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ 4249da8320bSMax Filippov #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ 4259da8320bSMax Filippov #define XCHAL_VECBASE_RESET_PADDR 0x00002000 4269da8320bSMax Filippov #define XCHAL_RESET_VECBASE_OVERLAP 0 4279da8320bSMax Filippov 4289da8320bSMax Filippov #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 4299da8320bSMax Filippov #define XCHAL_RESET_VECTOR0_PADDR 0xFE000000 4309da8320bSMax Filippov #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 4319da8320bSMax Filippov #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 4329da8320bSMax Filippov #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 4339da8320bSMax Filippov #define XCHAL_RESET_VECTOR_PADDR 0xFE000000 4349da8320bSMax Filippov #define XCHAL_USER_VECOFS 0x00000340 4359da8320bSMax Filippov #define XCHAL_USER_VECTOR_VADDR 0x00002340 4369da8320bSMax Filippov #define XCHAL_USER_VECTOR_PADDR 0x00002340 4379da8320bSMax Filippov #define XCHAL_KERNEL_VECOFS 0x00000300 4389da8320bSMax Filippov #define XCHAL_KERNEL_VECTOR_VADDR 0x00002300 4399da8320bSMax Filippov #define XCHAL_KERNEL_VECTOR_PADDR 0x00002300 4409da8320bSMax Filippov #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 4419da8320bSMax Filippov #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0 4429da8320bSMax Filippov #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0 4439da8320bSMax Filippov #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 4449da8320bSMax Filippov #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 4459da8320bSMax Filippov #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 4469da8320bSMax Filippov #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 4479da8320bSMax Filippov #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 4489da8320bSMax Filippov #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 4499da8320bSMax Filippov #define XCHAL_WINDOW_VECTORS_VADDR 0x00002000 4509da8320bSMax Filippov #define XCHAL_WINDOW_VECTORS_PADDR 0x00002000 4519da8320bSMax Filippov #define XCHAL_INTLEVEL2_VECOFS 0x00000180 4529da8320bSMax Filippov #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180 4539da8320bSMax Filippov #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180 4549da8320bSMax Filippov #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 4559da8320bSMax Filippov #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0 4569da8320bSMax Filippov #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0 4579da8320bSMax Filippov #define XCHAL_INTLEVEL4_VECOFS 0x00000200 4589da8320bSMax Filippov #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200 4599da8320bSMax Filippov #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200 4609da8320bSMax Filippov #define XCHAL_INTLEVEL5_VECOFS 0x00000240 4619da8320bSMax Filippov #define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240 4629da8320bSMax Filippov #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240 4639da8320bSMax Filippov #define XCHAL_INTLEVEL6_VECOFS 0x00000280 4649da8320bSMax Filippov #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280 4659da8320bSMax Filippov #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280 4669da8320bSMax Filippov #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS 4679da8320bSMax Filippov #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR 4689da8320bSMax Filippov #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR 4699da8320bSMax Filippov #define XCHAL_NMI_VECOFS 0x000002C0 4709da8320bSMax Filippov #define XCHAL_NMI_VECTOR_VADDR 0x000022C0 4719da8320bSMax Filippov #define XCHAL_NMI_VECTOR_PADDR 0x000022C0 4729da8320bSMax Filippov #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS 4739da8320bSMax Filippov #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR 4749da8320bSMax Filippov #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR 4759da8320bSMax Filippov 4769da8320bSMax Filippov 4779da8320bSMax Filippov /*---------------------------------------------------------------------- 4789da8320bSMax Filippov DEBUG MODULE 4799da8320bSMax Filippov ----------------------------------------------------------------------*/ 4809da8320bSMax Filippov 4819da8320bSMax Filippov /* Misc */ 4829da8320bSMax Filippov #define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ 4839da8320bSMax Filippov #define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ 4849da8320bSMax Filippov #define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ 4859da8320bSMax Filippov 4869da8320bSMax Filippov /* On-Chip Debug (OCD) */ 4879da8320bSMax Filippov #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ 4889da8320bSMax Filippov #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ 4899da8320bSMax Filippov #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ 4909da8320bSMax Filippov #define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ 4919da8320bSMax Filippov #define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ 4929da8320bSMax Filippov 4939da8320bSMax Filippov /* TRAX (in core) */ 4949da8320bSMax Filippov #define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ 4959da8320bSMax Filippov #define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */ 4969da8320bSMax Filippov #define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ 4979da8320bSMax Filippov #define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ 4989da8320bSMax Filippov #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ 4999da8320bSMax Filippov 5009da8320bSMax Filippov /* Perf counters */ 5019da8320bSMax Filippov #define XCHAL_NUM_PERF_COUNTERS 8 /* performance counters */ 5029da8320bSMax Filippov 5039da8320bSMax Filippov 5049da8320bSMax Filippov /*---------------------------------------------------------------------- 5059da8320bSMax Filippov MMU 5069da8320bSMax Filippov ----------------------------------------------------------------------*/ 5079da8320bSMax Filippov 5089da8320bSMax Filippov /* See core-matmap.h header file for more details. */ 5099da8320bSMax Filippov 5109da8320bSMax Filippov #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ 5119da8320bSMax Filippov #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ 5129da8320bSMax Filippov #define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */ 5139da8320bSMax Filippov #define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ 5149da8320bSMax Filippov #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ 5159da8320bSMax Filippov #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ 5169da8320bSMax Filippov #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ 5179da8320bSMax Filippov #define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table 5189da8320bSMax Filippov [autorefill] and protection) 5199da8320bSMax Filippov usable for an MMU-based OS */ 5209da8320bSMax Filippov /* If none of the above last 4 are set, it's a custom TLB configuration. */ 5219da8320bSMax Filippov #define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 5229da8320bSMax Filippov #define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 5239da8320bSMax Filippov 5249da8320bSMax Filippov #define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ 5259da8320bSMax Filippov #define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ 5269da8320bSMax Filippov #define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */ 5279da8320bSMax Filippov 5289da8320bSMax Filippov #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 5299da8320bSMax Filippov 5309da8320bSMax Filippov 5319da8320bSMax Filippov #endif /* _XTENSA_CORE_CONFIGURATION_H */ 532