| /openbmc/u-boot/arch/xtensa/include/asm/ |
| H A D | cacheasm.h | 18 #define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
93 __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
131 XCHAL_ICACHE_LINEWIDTH
168 __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
205 __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
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| /openbmc/linux/arch/xtensa/include/asm/ |
| H A D | cacheasm.h | 97 XCHAL_ICACHE_LINEWIDTH 240
137 XCHAL_ICACHE_LINEWIDTH 1020
174 __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
211 __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 1020
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| H A D | cache.h | 23 #define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
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| /openbmc/linux/arch/xtensa/variants/fsf/include/variant/ |
| H A D | core.h | 116 #define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */ macro
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| /openbmc/qemu/target/xtensa/core-fsf/ |
| H A D | core-isa.h | 118 #define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */ macro
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| /openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/ |
| H A D | core.h | 131 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
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| /openbmc/linux/arch/xtensa/variants/dc232b/include/variant/ |
| H A D | core.h | 123 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
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| /openbmc/qemu/target/xtensa/core-dc232b/ |
| H A D | core-isa.h | 122 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
|
| /openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/ |
| H A D | core.h | 121 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
|
| /openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/ |
| H A D | core-isa.h | 182 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
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| /openbmc/qemu/target/xtensa/core-lx106/ |
| H A D | core-isa.h | 151 #define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ macro
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| /openbmc/qemu/target/xtensa/core-dsp3400/ |
| H A D | core-isa.h | 158 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
|
| /openbmc/linux/arch/xtensa/variants/dc233c/include/variant/ |
| H A D | core.h | 162 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
|
| /openbmc/qemu/target/xtensa/core-dc233c/ |
| H A D | core-isa.h | 161 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
|
| /openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/ |
| H A D | core.h | 140 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
|
| /openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
| H A D | core.h | 182 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
|
| /openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/ |
| H A D | core.h | 211 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
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| /openbmc/linux/arch/xtensa/variants/de212/include/variant/ |
| H A D | core.h | 210 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
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| /openbmc/linux/arch/xtensa/variants/csp/include/variant/ |
| H A D | core.h | 210 #define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */ macro
|
| /openbmc/qemu/target/xtensa/core-test_kc705_be/ |
| H A D | core-isa.h | 210 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
|
| /openbmc/u-boot/arch/xtensa/include/asm/arch-de212/ |
| H A D | core.h | 188 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
|
| /openbmc/qemu/target/xtensa/core-de212/ |
| H A D | core-isa.h | 219 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
|
| /openbmc/qemu/target/xtensa/core-sample_controller/ |
| H A D | core-isa.h | 233 #define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ macro
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| /openbmc/qemu/target/xtensa/core-de233_fpu/ |
| H A D | core-isa.h | 282 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
|