| /openbmc/linux/arch/xtensa/include/asm/ |
| H A D | mmu_context.h | 30 #if (XCHAL_HAVE_TLBS != 1)
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| H A D | initialize_mmu.h | 181 #if !defined(CONFIG_MMU) && (XCHAL_HAVE_TLBS || XCHAL_HAVE_MPU)
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| /openbmc/linux/arch/xtensa/variants/fsf/include/variant/ |
| H A D | core.h | 338 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/qemu/target/xtensa/core-fsf/ |
| H A D | core-isa.h | 340 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/ |
| H A D | core.h | 363 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/linux/arch/xtensa/variants/dc232b/include/variant/ |
| H A D | core.h | 403 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/qemu/target/xtensa/core-dc232b/ |
| H A D | core-isa.h | 402 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/ |
| H A D | core.h | 401 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/ |
| H A D | core-isa.h | 452 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/qemu/target/xtensa/core-lx106/ |
| H A D | core-isa.h | 450 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/qemu/target/xtensa/core-dsp3400/ |
| H A D | core-isa.h | 431 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/linux/arch/xtensa/variants/dc233c/include/variant/ |
| H A D | core.h | 453 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/qemu/target/xtensa/core-dc233c/ |
| H A D | core-isa.h | 452 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/ |
| H A D | core.h | 431 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
| H A D | core.h | 510 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/ |
| H A D | core.h | 553 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/linux/arch/xtensa/variants/de212/include/variant/ |
| H A D | core.h | 574 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/linux/arch/xtensa/variants/csp/include/variant/ |
| H A D | core.h | 553 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/qemu/target/xtensa/core-test_kc705_be/ |
| H A D | core-isa.h | 552 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/u-boot/arch/xtensa/include/asm/arch-de212/ |
| H A D | core.h | 552 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/qemu/target/xtensa/core-de212/ |
| H A D | core-isa.h | 588 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/qemu/target/xtensa/core-sample_controller/ |
| H A D | core-isa.h | 609 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
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| /openbmc/qemu/target/xtensa/core-de233_fpu/ |
| H A D | core-isa.h | 691 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
|