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Searched refs:XCHAL_HAVE_BE (Results 1 – 25 of 31) sorted by relevance

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/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_b.S88 #if XCHAL_HAVE_BE
99 #if XCHAL_HAVE_BE
208 #if XCHAL_HAVE_BE
219 #if XCHAL_HAVE_BE
H A Dlinker.ld.S17 #if XCHAL_HAVE_BE
H A Dtest_sr.S5 #if XCHAL_HAVE_BE
/openbmc/linux/arch/xtensa/platforms/xtfpga/
H A Dsetup.c188 .big_endian = XCHAL_HAVE_BE,
249 .iotype = XCHAL_HAVE_BE ? UPIO_MEM32BE : UPIO_MEM32,
/openbmc/linux/arch/xtensa/platforms/xt2000/
H A Dsetup.c101 #if XCHAL_HAVE_BE
/openbmc/linux/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h29 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */ macro
/openbmc/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h28 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */ macro
/openbmc/u-boot/examples/standalone/
H A Dstubs.c232 #if XCHAL_HAVE_BE
/openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h28 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/openbmc/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h29 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h28 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h27 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/openbmc/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/openbmc/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h27 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h49 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */ macro
/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/openbmc/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h48 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h27 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro

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