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Searched refs:XCHAL_DCACHE_LINEWIDTH (Results 1 – 24 of 24) sorted by relevance

/openbmc/u-boot/arch/xtensa/include/asm/
H A Dcacheasm.h17 #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
84 __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
102 __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
111 __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
121 XCHAL_DCACHE_LINEWIDTH
141 __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
150 __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
159 __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
178 __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
187 __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
[all …]
/openbmc/linux/arch/xtensa/include/asm/
H A Dcacheasm.h87 XCHAL_DCACHE_LINEWIDTH 240
107 XCHAL_DCACHE_LINEWIDTH 240
117 XCHAL_DCACHE_LINEWIDTH 240
127 XCHAL_DCACHE_LINEWIDTH 1020
147 __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
156 __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
165 __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
184 __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 1020
193 __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 1020
202 __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 1020
H A Dcache.h16 #define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH
22 #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
/openbmc/linux/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h117 #define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h119 #define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */ macro
/openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h132 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/openbmc/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h124 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h123 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h122 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h183 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h152 #define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h159 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/openbmc/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h163 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h162 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h141 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h183 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h212 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h211 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/openbmc/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h211 #define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h211 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h189 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h220 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h234 #define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h283 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro