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Searched refs:WREG32_FIELD15 (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dhdp_v4_0.c146 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); in hdp_v4_0_init_registers()
152 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); in hdp_v4_0_init_registers()
155 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2); in hdp_v4_0_init_registers()
H A Ddf_v1_7.c117 WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0, in df_v1_7_enable_ecc_force_par_wr_rmw()
H A Dnbio_v7_4.c212 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); in nbio_v7_4_enable_doorbell_aperture()
648 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL_ALDE, in nbio_v7_4_enable_doorbell_interrupt()
651 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL, in nbio_v7_4_enable_doorbell_interrupt()
H A Dgfxhub_v1_0.c137 WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v1_0_init_system_aperture_regs()
366 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v1_0_gart_disable()
H A Dgfxhub_v2_0.c181 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v2_0_init_system_aperture_regs()
381 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v2_0_gart_disable()
H A Dvega20_ih.c366 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN, in vega20_ih_irq_init()
369 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1); in vega20_ih_irq_init()
H A Dnbio_v7_0.c108 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); in nbio_v7_0_enable_doorbell_aperture()
H A Dgfx_v9_0.c1626 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_lbpw()
2641 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); in gfx_v9_0_enable_save_restore_machine()
2839 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v9_0_rlc_stop()
2846 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v9_0_rlc_reset()
2848 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v9_0_rlc_reset()
2858 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v9_0_rlc_start()
3387 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_0_kiq_init_register()
3489 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v9_0_kiq_init_register()
3796 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_0_hw_fini()
5723 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_gfx_eop_interrupt_state()
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H A Dgfxhub_v2_1.c182 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v2_1_init_system_aperture_regs()
404 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v2_1_gart_disable()
H A Dnbio_v6_1.c110 WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); in nbio_v6_1_enable_doorbell_aperture()
H A Dsoc15_common.h50 #define WREG32_FIELD15(ip, idx, reg, field, val) \ macro
H A Dnbio_v2_3.c159 WREG32_FIELD15(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, in nbio_v2_3_enable_doorbell_aperture()
H A Damdgpu_amdkfd_gfx_v10_3.c513 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); in hqd_destroy_v10_3()
H A Dgmc_v9_0.c2338 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v9_0_hw_init()
2340 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in gmc_v9_0_hw_init()
H A Damdgpu_amdkfd_gfx_v10.c534 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); in kgd_hqd_destroy()
H A Dgfx_v10_0.c4976 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); in gfx_v10_0_constants_init()
5061 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v10_0_rlc_reset()
5063 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v10_0_rlc_reset()
5098 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v10_0_rlc_start()
6625 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v10_0_kiq_init_register()
6718 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v10_0_kiq_init_register()
8956 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v10_0_set_priv_reg_fault_state()
8975 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v10_0_set_priv_inst_fault_state()
9502 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); in gfx_v10_3_program_pbb_mode()