Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37 |
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#
f51f2088 |
| 30-Jun-2023 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amdgpu: Fix warnings in gfxhub_v2_1.c
Fix the below checkpatch warnings:
WARNING: static const char * array should probably be static const char * const +static const char *gfxhub_client_ids[]
drm/amdgpu: Fix warnings in gfxhub_v2_1.c
Fix the below checkpatch warnings:
WARNING: static const char * array should probably be static const char * const +static const char *gfxhub_client_ids[] = {
WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + unsigned i;
WARNING: Missing a blank line after declarations + int i; + adev->gmc.VM_L2_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
WARNING: Missing a blank line after declarations + int i; + WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, adev->gmc.VM_L2_CNTL);
WARNING: braces {} are not necessary for single statement blocks + if (!time) { + DRM_WARN("failed to wait for GRBM(EA) idle\n"); + }
Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68 |
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#
f4caf584 |
| 14-Sep-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: introduce vmhub definition for multi-partition cases (v3)
v1: Each partition has its own gfxhub or mmhub. adjust the num of MAX_VMHUBS and the GFXHUB/MMHUB layout (Le)
v2: re-design the
drm/amdgpu: introduce vmhub definition for multi-partition cases (v3)
v1: Each partition has its own gfxhub or mmhub. adjust the num of MAX_VMHUBS and the GFXHUB/MMHUB layout (Le)
v2: re-design the AMDGPU_GFXHUB/AMDGPU_MMHUB layout (Le)
v3: apply the gfxhub/mmhub layout to new IPs (Hawking)
v4: fix up gmc11 (Alex)
v5: rebase (Alex)
Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17 |
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#
7ccfd79f |
| 21-Jan-2022 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: rename vram_scratch into mem_scratch
Rename vram_scratch into mem_scratch and allow allocating it into GTT as well.
The only problem with that is that we won't have a default page for t
drm/amdgpu: rename vram_scratch into mem_scratch
Rename vram_scratch into mem_scratch and allow allocating it into GTT as well.
The only problem with that is that we won't have a default page for the system aperture any more.
Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f8638ad7 |
| 28-Oct-2022 |
Peng Ju Zhou <PengJu.Zhou@amd.com> |
drm/amdgpu: Remove unnecessary register program in SRIOV
Remove unnecessary register program in SRIOV
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd
drm/amdgpu: Remove unnecessary register program in SRIOV
Remove unnecessary register program in SRIOV
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
72fadb13 |
| 23-Jun-2022 |
Victor Zhao <Victor.Zhao@amd.com> |
drm/amdgpu: revert context to stop engine before mode2 reset
For some hang caused by slow tests, engine cannot be stopped which may cause resume failure after reset. In this case, force halt engine
drm/amdgpu: revert context to stop engine before mode2 reset
For some hang caused by slow tests, engine cannot be stopped which may cause resume failure after reset. In this case, force halt engine by reverting context addresses
Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bfaced6e |
| 21-Jun-2022 |
Victor Zhao <Victor.Zhao@amd.com> |
drm/amdgpu: save and restore gc hub regs
Save and restore gfxhub regs as they will be reset during mode 2
Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzo
drm/amdgpu: save and restore gc hub regs
Save and restore gfxhub regs as they will be reset during mode 2
Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119 |
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#
d7dab4fc |
| 12-May-2021 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: save the setting of VM_CONTEXT_CNTL
MES firmware needs the setting of VM_CONTEXT_CNTL to perform vmid switch. Save the initial setting when hub initializing.
Signed-off-by: Jack Xiao <J
drm/amdgpu: save the setting of VM_CONTEXT_CNTL
MES firmware needs the setting of VM_CONTEXT_CNTL to perform vmid switch. Save the initial setting when hub initializing.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a072312f |
| 28-Jan-2022 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add utcl2_harvest to gc 10.3.1
Confirmed with hardware team, there is harvesting for gc 10.3.1.
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> S
drm/amdgpu: add utcl2_harvest to gc 10.3.1
Confirmed with hardware team, there is harvesting for gc 10.3.1.
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6d53b115 |
| 28-Jan-2022 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add utcl2_harvest to gc 10.3.1
Confirmed with hardware team, there is harvesting for gc 10.3.1.
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> S
drm/amdgpu: add utcl2_harvest to gc 10.3.1
Confirmed with hardware team, there is harvesting for gc 10.3.1.
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
841933d5 |
| 04-Dec-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: don't override default ECO_BITs setting
Leave this bit as hardware default setting
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.
drm/amdgpu: don't override default ECO_BITs setting
Leave this bit as hardware default setting
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
4ac955ba |
| 04-Dec-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: don't override default ECO_BITs setting
Leave this bit as hardware default setting
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.
drm/amdgpu: don't override default ECO_BITs setting
Leave this bit as hardware default setting
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1d789535 |
| 04-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: convert IP version array to include instances
Allow us to query instances versions more cleanly.
Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cich
drm/amdgpu: convert IP version array to include instances
Allow us to query instances versions more cleanly.
Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms.
v2: rebase v3: clarify instancing support
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
fac17723 |
| 27-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/gfxhub2.1: convert to IP version checking
Use IP versions rather than asic_type to differentiate IP version specific features.
Acked-by: Christian König <christian.koenig@amd.com> Signed
drm/amdgpu/gfxhub2.1: convert to IP version checking
Use IP versions rather than asic_type to differentiate IP version specific features.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a386ae52 |
| 04-Dec-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: don't override default ECO_BITs setting
commit 841933d5b8aa853abe68e63827f68f50fab37226 upstream.
Leave this bit as hardware default setting
Signed-off-by: Hawking Zhang <Hawking.Zhang
drm/amdgpu: don't override default ECO_BITs setting
commit 841933d5b8aa853abe68e63827f68f50fab37226 upstream.
Leave this bit as hardware default setting
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30 |
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#
b3accd6f |
| 05-Apr-2021 |
Xiaomeng Hou <Xiaomeng.Hou@amd.com> |
drm/amdgpu: add gpu harvest support for yellow carp (v2)
Register callback in gfxhub functions to program the bypass groups in gc_utcl2 corresponding to harvested SA.
v2: update comments (Alex)
Si
drm/amdgpu: add gpu harvest support for yellow carp (v2)
Register callback in gfxhub functions to program the bypass groups in gc_utcl2 corresponding to harvested SA.
v2: update comments (Alex)
Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0ca565ab |
| 01-Apr-2021 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Calling address translation functions to simplify codes
Use amdgpu_gmc_vram_pa and amdgpu_gmc_vram_cpu_pa to simplify codes. No logic change.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
drm/amdgpu: Calling address translation functions to simplify codes
Use amdgpu_gmc_vram_pa and amdgpu_gmc_vram_cpu_pa to simplify codes. No logic change.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10 |
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#
99698b51 |
| 30-Nov-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: enable AGP aperture on gmc10.x (v2)
Just a small optimization for accessing system pages directly. Was missed for gmc v10 since the feature landed for older gmcs while we were still on t
drm/amdgpu: enable AGP aperture on gmc10.x (v2)
Just a small optimization for accessing system pages directly. Was missed for gmc v10 since the feature landed for older gmcs while we were still on the emulator or gmc10 and we use the AGP aperture for zfb on the emulator.
v2: fix up the system aperture as well
Reviewed-and-tested-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11 |
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#
8ffff9b4 |
| 17-Sep-2020 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: use function pointer for gfxhub functions
gfxhub functions are now called from function pointers, instead of from asic-specific functions.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Rev
drm/amdgpu: use function pointer for gfxhub functions
gfxhub functions are now called from function pointers, instead of from asic-specific functions.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9b498efa |
| 23-Sep-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: store noretry parameter per driver instance
This will allow us to have different defaults per asic in a future patch.
Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by
drm/amdgpu: store noretry parameter per driver instance
This will allow us to have different defaults per asic in a future patch.
Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62 |
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#
93fabd84 |
| 01-Sep-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/gmc10: print client id string for gfxhub
Print the name of the client rather than the number. This makes it easier to debug what block is causing the fault.
Reviewed-by: Felix Kuehling
drm/amdgpu/gmc10: print client id string for gfxhub
Print the name of the client rather than the number. This makes it easier to debug what block is causing the fault.
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57 |
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#
d5bbb476 |
| 06-Aug-2020 |
Liu ChengZhe <ChengZhe.Liu@amd.com> |
drm/amdgpu: Skip some registers config for SRIOV
Some registers are not accessible to virtual function setup, so skip their initialization when in VF-SRIOV mode.
v2: move SRIOV VF check into specif
drm/amdgpu: Skip some registers config for SRIOV
Some registers are not accessible to virtual function setup, so skip their initialization when in VF-SRIOV mode.
v2: move SRIOV VF check into specify functions; modify commit description and comment.
Signed-off-by: Liu ChengZhe <ChengZhe.Liu@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1d447326 |
| 06-Aug-2020 |
Liu ChengZhe <ChengZhe.Liu@amd.com> |
drm/amdgpu: Skip some registers config for SRIOV
Some registers are not accessible to virtual function setup, so skip their initialization when in VF-SRIOV mode.
v2: move SRIOV VF check into specif
drm/amdgpu: Skip some registers config for SRIOV
Some registers are not accessible to virtual function setup, so skip their initialization when in VF-SRIOV mode.
v2: move SRIOV VF check into specify functions; modify commit description and comment.
Signed-off-by: Liu ChengZhe <ChengZhe.Liu@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53 |
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#
caa9f483 |
| 21-Jul-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: move get_invalidate_req function into gfxhub/mmhub level
This patch is to move get_invalidate_req into gfxhub/mmhub level. It will avoid mismatch of the different gfxhub/mmhub register o
drm/amdgpu: move get_invalidate_req function into gfxhub/mmhub level
This patch is to move get_invalidate_req into gfxhub/mmhub level. It will avoid mismatch of the different gfxhub/mmhub register offsets and fields in the same gmc block.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2577db91 |
| 21-Jul-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add vmhub funcs helper (v2)
This patch is to introduce vmhub funcs helper to add following callback (print_l2_protection_fault_status). Each GC/MMHUB register specific programming should
drm/amdgpu: add vmhub funcs helper (v2)
This patch is to introduce vmhub funcs helper to add following callback (print_l2_protection_fault_status). Each GC/MMHUB register specific programming should be in gfxhub/mmhub level.
v2: remove the condition of funcs assignment.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5befb6fc |
| 21-Jul-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add member to store vm fault interrupt masks
This patch adds a member in vmhub structure to store the vm fault interrupt masks for different version gfxhubs/mmhubs.
Signed-off-by: Huang
drm/amdgpu: add member to store vm fault interrupt masks
This patch adds a member in vmhub structure to store the vm fault interrupt masks for different version gfxhubs/mmhubs.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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