Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35 |
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#
8ed49dd1 |
| 16-Jun-2023 |
Victor Lu <victorchengchi.lu@amd.com> |
drm/amdgpu: Add RLCG interface driver implementation for gfx v9.4.3 (v3)
Add RLCG interface support for gfx v9.4.3 and multiple XCCs. Do not enable it yet.
v2: Fix amdgpu_rlcg_reg_access_ctrl init,
drm/amdgpu: Add RLCG interface driver implementation for gfx v9.4.3 (v3)
Add RLCG interface support for gfx v9.4.3 and multiple XCCs. Do not enable it yet.
v2: Fix amdgpu_rlcg_reg_access_ctrl init, add support for multiple XCCs in amdgpu_mm_wreg_mmio_rlc
v3: Use GET_INST() when indexing amdgpu_rlcg_reg_access_ctrl
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15 |
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#
af2ba368 |
| 27-Feb-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: convert logical instance mask to physical one
Convert instance mask for the convenience of RAS TA.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@
drm/amdgpu: convert logical instance mask to physical one
Convert instance mask for the convenience of RAS TA.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
55ff23d9 |
| 22-Mar-2023 |
Sonny Jiang <sonjiang@amd.com> |
drm/amdgpu: fixes a JPEG get write/read pointer bug
Need parentheses for the micro parameters.
Signed-off-by: Sonny Jiang <sonjiang@amd.com> Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com> S
drm/amdgpu: fixes a JPEG get write/read pointer bug
Need parentheses for the micro parameters.
Signed-off-by: Sonny Jiang <sonjiang@amd.com> Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71 |
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#
2fa480d3 |
| 27-Sep-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add helpers to access registers on different AIDs
SMN address which is larger than 32bit has different indications through bit[34:32] on different AIDs.
v2: put smn addressing of differ
drm/amdgpu: add helpers to access registers on different AIDs
SMN address which is larger than 32bit has different indications through bit[34:32] on different AIDs.
v2: put smn addressing of different AIDs into asic specific place v3: change to ext_id/ext_offset naming
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53 |
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#
659a4ab8 |
| 04-Jul-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use instance lookup table for GC 9.4.3
Register accesses need to be based on physical instance on bare metal. Pass the right instance using logical to physical instance lookup table befo
drm/amdgpu: Use instance lookup table for GC 9.4.3
Register accesses need to be based on physical instance on bare metal. Pass the right instance using logical to physical instance lookup table before accessing registers. Add a macro GET_INST to get the right physical instance of an IP corresponding to a logical instance.
v2: fix gfx_v9_4_3_check_rlcg_range() (Alex)
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16 |
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#
81283fee |
| 19-Jan-2022 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/: add more macro to support offset variant
Add more macro to support offset variant and simplify macro SOC15_WAIT_ON_RREG.
Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo L
drm/amdgpu/: add more macro to support offset variant
Add more macro to support offset variant and simplify macro SOC15_WAIT_ON_RREG.
Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6 |
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#
99951878 |
| 29-Nov-2021 |
Shiwu Zhang <shiwu.zhang@amd.com> |
drm/amdgpu: make the WREG32_SOC15_xx macro to support multi GC
To write regs on different GCDs, use the inst index.
Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.co
drm/amdgpu: make the WREG32_SOC15_xx macro to support multi GC
To write regs on different GCDs, use the inst index.
Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60 |
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#
ba9e7a4a |
| 04-Aug-2021 |
Stanley.Yang <Stanley.Yang@amd.com> |
drm/amdgpu: add new write field for soc21
add new write field macro to handle soc21 registers with reg prefix
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Stanley.Yang <Stanl
drm/amdgpu: add new write field for soc21
add new write field macro to handle soc21 registers with reg prefix
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1b2dc99e |
| 18-Jan-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to amdgpu_sriov_rreg/wreg
Instead of ip specific implementation for rlcg indirect register access
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Zhou, Peng Ju
drm/amdgpu: switch to amdgpu_sriov_rreg/wreg
Instead of ip specific implementation for rlcg indirect register access
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Zhou, Peng Ju <PengJu.Zhou@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0da6f6e5 |
| 13-Dec-2021 |
Victor Skvortsov <victor.skvortsov@amd.com> |
drm/amdgpu: Add *_SOC15_IP_NO_KIQ() macro definitions
Add helper macros to change register access from direct to indirect.
Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by: Da
drm/amdgpu: Add *_SOC15_IP_NO_KIQ() macro definitions
Add helper macros to change register access from direct to indirect.
Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by: David Nieto <david.nieto@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49 |
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#
1a4772d9 |
| 05-Jul-2021 |
Roy Sun <Roy.Sun@amd.com> |
drm/amdgpu: Change the imprecise function name
The callback functions are used for SRIOV read/write instead of just for rlcg read/write
Signed-off-by: Roy Sun <Roy.Sun@amd.com> Reviewed-by: Zhou pe
drm/amdgpu: Change the imprecise function name
The callback functions are used for SRIOV read/write instead of just for rlcg read/write
Signed-off-by: Roy Sun <Roy.Sun@amd.com> Reviewed-by: Zhou pengju <pengju.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.13, v5.10.46, v5.10.43 |
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#
9a3bf287 |
| 07-Jun-2021 |
Peng Ju Zhou <PengJu.Zhou@amd.com> |
drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10
The NV12 and VEGA10 share the same interface W/RREG32_SOC15*, the callback functions in these macros may not be defined, so
drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10
The NV12 and VEGA10 share the same interface W/RREG32_SOC15*, the callback functions in these macros may not be defined, so NULL pointer must be checked but not in macro __WREG32_SOC15_RLC__, fixing the lock of NULL pointer check.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.42 |
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#
23e4aa51 |
| 01-Jun-2021 |
shaoyunl <shaoyun.liu@amd.com> |
drm/amdgpu: soc15 register access through RLC should only apply to sriov runtime
On SRIOV, driver should only access register through RLC in runtime
Acked-by: Alex Deucher <alexander.deucher@amd.co
drm/amdgpu: soc15 register access through RLC should only apply to sriov runtime
On SRIOV, driver should only access register through RLC in runtime
Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.41, v5.10.40, v5.10.39, v5.4.119 |
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#
a5504e9a |
| 14-May-2021 |
Peng Ju Zhou <PengJu.Zhou@amd.com> |
drm/amdgpu: Indirect register access for Navi12 sriov
This patch series are used for GC/MMHUB(part)/IH_RB_CNTL indirect access in the SRIOV environment.
There are 4 bits, controlled by host, to con
drm/amdgpu: Indirect register access for Navi12 sriov
This patch series are used for GC/MMHUB(part)/IH_RB_CNTL indirect access in the SRIOV environment.
There are 4 bits, controlled by host, to control if GC/MMHUB(part)/IH_RB_CNTL indirect access enabled. (one bit is master bit controls other 3 bits)
For GC registers, changing all the register access from MMIO to RLC and use RLC as the default access method in the full access time.
For partial MMHUB registers, changing their access from MMIO to RLC in the full access time, the remaining registers keep the original access method.
For IH_RB_CNTL register, changing it's access from MMIO to PSP.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26 |
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#
5e025531 |
| 22-Mar-2021 |
Peng Ju Zhou <PengJu.Zhou@amd.com> |
drm/amdgpu: indirect register access for nv12 sriov
1. expand rlcg interface for gc & mmhub indirect access 2. add rlcg interface for no kiq
v2: squash in fix for gfx9 (Changfeng)
Signed-off-by: P
drm/amdgpu: indirect register access for nv12 sriov
1. expand rlcg interface for gc & mmhub indirect access 2. add rlcg interface for no kiq
v2: squash in fix for gfx9 (Changfeng)
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by: Emily.Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21 |
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#
88f8575b |
| 05-Mar-2021 |
Dennis Li <Dennis.Li@amd.com> |
drm/amdgpu: enable watchdog feature for SQ of aldebaran
SQ's watchdog timer monitors forward progress, a mask of which waves caused the watchdog timeout is recorded into ras status registers and the
drm/amdgpu: enable watchdog feature for SQ of aldebaran
SQ's watchdog timer monitors forward progress, a mask of which waves caused the watchdog timeout is recorded into ras status registers and then trigger a system fatal error event.
v2: 1. change *query_timeout_status to *query_sq_timeout_status. 2. move query_sq_timeout_status into amdgpu_ras_do_recovery. 3. add module parameters to enable/disable fatal error event and modify the watchdog timer.
v3: 1. remove unused parameters of *enable_watchdog_timer
Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
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#
22616eb5 |
| 25-Jan-2021 |
Dennis Li <Dennis.Li@amd.com> |
drm/amdgpu: add ras support for gfx of aldebaran
add edc counter/status reset and query functions for gfx block of aldebaran.
v2: change to clear edc counter explicitly aldebaran hardware will not
drm/amdgpu: add ras support for gfx of aldebaran
add edc counter/status reset and query functions for gfx block of aldebaran.
v2: change to clear edc counter explicitly aldebaran hardware will not clear edc counter after driver reading them, so driver should clear them explicitly.
Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4 |
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#
450da2ef |
| 17-Jun-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: fix unused variable
SOC15_WAIT_ON_RREG's return value needn't always been handled by caller. new design is to fix this kind of unused variable.
Signed-off-by: James Zhu <James.Zhu@amd.c
drm/amdgpu: fix unused variable
SOC15_WAIT_ON_RREG's return value needn't always been handled by caller. new design is to fix this kind of unused variable.
Signed-off-by: James Zhu <James.Zhu@amd.com> Reported-by: kernel test robot <lkp@intel.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35 |
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#
c2ce6aeb |
| 22-Apr-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: provide RREG32_SOC15_NO_KIQ, will be used later
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Yintian Tao <yttao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25 |
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#
2e0cc4d4 |
| 10-Mar-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: revise RLCG access path
what changed: 1)provide new implementation interface for the rlcg access path 2)put SQ_CMD/SQ_IND_INDEX to GFX9 RLCG path to let debugfs's reg_op function can acc
drm/amdgpu: revise RLCG access path
what changed: 1)provide new implementation interface for the rlcg access path 2)put SQ_CMD/SQ_IND_INDEX to GFX9 RLCG path to let debugfs's reg_op function can access reg that need RLCG path help
now even debugfs's reg_op can used to dump wave.
tested-by: Monk Liu <monk.liu@amd.com> tested-by: Zhou pengju <pengju.zhou@amd.com> Signed-off-by: Zhou pengju <pengju.zhou@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13 |
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#
a63141e3 |
| 23-Nov-2019 |
Nathan Chancellor <natechancellor@gmail.com> |
drm/amdgpu: Ensure ret is always initialized when using SOC15_WAIT_ON_RREG
Commit b0f3cd3191cd ("drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0") introduced a new clang warning in the vcn_v
drm/amdgpu: Ensure ret is always initialized when using SOC15_WAIT_ON_RREG
Commit b0f3cd3191cd ("drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0") introduced a new clang warning in the vcn_v2_0_stop function:
../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1082:2: warning: variable 'r' is used uninitialized whenever 'while' loop exits because its condition is false [-Wsometimes-uninitialized] SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../drivers/gpu/drm/amd/amdgpu/../amdgpu/soc15_common.h:55:10: note: expanded from macro 'SOC15_WAIT_ON_RREG' while ((tmp_ & (mask)) != (expected_value)) { \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1083:6: note: uninitialized use occurs here if (r) ^ ../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1082:2: note: remove the condition if it is always true SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r); ^ ../drivers/gpu/drm/amd/amdgpu/../amdgpu/soc15_common.h:55:10: note: expanded from macro 'SOC15_WAIT_ON_RREG' while ((tmp_ & (mask)) != (expected_value)) { \ ^ ../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1072:7: note: initialize the variable 'r' to silence this warning int r; ^ = 0 1 warning generated.
To prevent warnings like this from happening in the future, make the SOC15_WAIT_ON_RREG macro initialize its ret variable before the while loop that can time out. This macro's return value is always checked so it should set ret in both the success and fail path.
Link: https://github.com/ClangBuiltLinux/linux/issues/776 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5 |
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4cd4c5c0 |
| 30-Jul-2019 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: cleanup vega10 SRIOV code path
we can simplify all those unnecessary function under SRIOV for vega10 since: 1) PSP L1 policy is by force enabled in SRIOV 2) original logic always set all
drm/amdgpu: cleanup vega10 SRIOV code path
we can simplify all those unnecessary function under SRIOV for vega10 since: 1) PSP L1 policy is by force enabled in SRIOV 2) original logic always set all flags which make itself a dummy step
besides, 1) the ih_doorbell_range set should also be skipped for VEGA10 SRIOV. 2) the gfx_common registers should also be skipped for VEGA10 SRIOV.
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3, v5.1.2 |
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05eee12d |
| 13-May-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: move the VCN DPG mode read and write to VCN
Since this is VCN specific and only used by VCN
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com
drm/amdgpu: move the VCN DPG mode read and write to VCN
Since this is VCN specific and only used by VCN
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0 |
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6b1ff3dd |
| 28-Feb-2019 |
Trigger Huang <Trigger.Huang@amd.com> |
drm/amdgpu: add basic func for RLC program reg
New feature for RLC, some registers can be programmed by RLC interface under SR-IOV VF:
WREG32_SOC15_RLC_SHADOW: 1, for GRBM_GFX_CNTL, firstly the ne
drm/amdgpu: add basic func for RLC program reg
New feature for RLC, some registers can be programmed by RLC interface under SR-IOV VF:
WREG32_SOC15_RLC_SHADOW: 1, for GRBM_GFX_CNTL, firstly the new register value should be be programmed to SCRATCH_REG2 1, for GRBM_GFX_INDEX, firstly the new register value should be be programmed to SCRATCH_REG3
WREG32_RLC: for registers supported to be programmed by RLC interface, the following sequence should be used: 1, write the value to SCRATCH_REG0 2, write reg | 0x80000000 to SCRATCH_REG1 3, write 0x1 to RLC_SPARE_INT to notify RLC 4, polling SCRATCH_REG1 to check if finished
Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11 |
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7ab3f021 |
| 17-Dec-2018 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu:Improves robustness of SOC15_WAIT_ON_RREG
If register value is updating, reset timeout counter. It improves robustness of SOC15_WAIT_ON_RREG.
Signed-off-by: James Zhu <James.Zhu@amd.com>
drm/amdgpu:Improves robustness of SOC15_WAIT_ON_RREG
If register value is updating, reset timeout counter. It improves robustness of SOC15_WAIT_ON_RREG.
Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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