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Searched refs:UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h783 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x00000014 macro
H A Duvd_4_2_sh_mask.h562 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 macro
H A Duvd_3_1_sh_mask.h558 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 macro
H A Duvd_6_0_sh_mask.h598 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 macro
H A Duvd_5_0_sh_mask.h596 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1186 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2752 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2750 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h105 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3810 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h4056 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4093 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c746 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v4_0_3_start_dpg_mode()
795 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v4_0_3_start_dpg_mode()
H A Dvcn_v4_0.c936 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v4_0_start_dpg_mode()
983 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v4_0_start_dpg_mode()
H A Dvcn_v2_5.c841 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v2_5_start_dpg_mode()
904 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v2_5_start_dpg_mode()
H A Dvcn_v3_0.c964 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v3_0_start_dpg_mode()
1025 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v3_0_start_dpg_mode()
H A Dvcn_v2_0.c816 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v2_0_start_dpg_mode()
H A Dvcn_v1_0.c984 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v1_0_start_dpg_mode()