18da1170aSLeo Liu /*
28da1170aSLeo Liu * Copyright 2021 Advanced Micro Devices, Inc.
38da1170aSLeo Liu *
48da1170aSLeo Liu * Permission is hereby granted, free of charge, to any person obtaining a
58da1170aSLeo Liu * copy of this software and associated documentation files (the "Software"),
68da1170aSLeo Liu * to deal in the Software without restriction, including without limitation
78da1170aSLeo Liu * the rights to use, copy, modify, merge, publish, distribute, sublicense,
88da1170aSLeo Liu * and/or sell copies of the Software, and to permit persons to whom the
98da1170aSLeo Liu * Software is furnished to do so, subject to the following conditions:
108da1170aSLeo Liu *
118da1170aSLeo Liu * The above copyright notice and this permission notice shall be included in
128da1170aSLeo Liu * all copies or substantial portions of the Software.
138da1170aSLeo Liu *
148da1170aSLeo Liu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
158da1170aSLeo Liu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
168da1170aSLeo Liu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
178da1170aSLeo Liu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
188da1170aSLeo Liu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
198da1170aSLeo Liu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
208da1170aSLeo Liu * OTHER DEALINGS IN THE SOFTWARE.
218da1170aSLeo Liu *
228da1170aSLeo Liu */
238da1170aSLeo Liu
248da1170aSLeo Liu #include <linux/firmware.h>
258da1170aSLeo Liu #include "amdgpu.h"
268da1170aSLeo Liu #include "amdgpu_vcn.h"
278da1170aSLeo Liu #include "amdgpu_pm.h"
280b15205cSSonny Jiang #include "amdgpu_cs.h"
298da1170aSLeo Liu #include "soc15.h"
308da1170aSLeo Liu #include "soc15d.h"
318da1170aSLeo Liu #include "soc15_hw_ip.h"
328da1170aSLeo Liu #include "vcn_v2_0.h"
33aa44beb5SJane Jian #include "mmsch_v4_0.h"
34377d0221STao Zhou #include "vcn_v4_0.h"
358da1170aSLeo Liu
368da1170aSLeo Liu #include "vcn/vcn_4_0_0_offset.h"
378da1170aSLeo Liu #include "vcn/vcn_4_0_0_sh_mask.h"
388da1170aSLeo Liu #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
398da1170aSLeo Liu
408da1170aSLeo Liu #include <drm/drm_drv.h>
418da1170aSLeo Liu
428da1170aSLeo Liu #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL
438da1170aSLeo Liu #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX
448da1170aSLeo Liu #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA
458da1170aSLeo Liu #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX
468da1170aSLeo Liu
478da1170aSLeo Liu #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
488da1170aSLeo Liu #define VCN1_VID_SOC_ADDRESS_3_0 0x48300
498da1170aSLeo Liu
50aa44beb5SJane Jian #define VCN_HARVEST_MMSCH 0
51aa44beb5SJane Jian
520b15205cSSonny Jiang #define RDECODE_MSG_CREATE 0x00000000
530b15205cSSonny Jiang #define RDECODE_MESSAGE_CREATE 0x00000001
540b15205cSSonny Jiang
558da1170aSLeo Liu static int amdgpu_ih_clientid_vcns[] = {
568da1170aSLeo Liu SOC15_IH_CLIENTID_VCN,
578da1170aSLeo Liu SOC15_IH_CLIENTID_VCN1
588da1170aSLeo Liu };
598da1170aSLeo Liu
60aa44beb5SJane Jian static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
61bb4f196bSRuijing Dong static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
628da1170aSLeo Liu static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
638da1170aSLeo Liu static int vcn_v4_0_set_powergating_state(void *handle,
648da1170aSLeo Liu enum amd_powergating_state state);
658da1170aSLeo Liu static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
668da1170aSLeo Liu int inst_idx, struct dpg_pause_state *new_state);
67aa44beb5SJane Jian static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring);
68377d0221STao Zhou static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev);
698da1170aSLeo Liu
708da1170aSLeo Liu /**
7169939009SMario Limonciello * vcn_v4_0_early_init - set function pointers and load microcode
728da1170aSLeo Liu *
738da1170aSLeo Liu * @handle: amdgpu_device pointer
748da1170aSLeo Liu *
758da1170aSLeo Liu * Set ring and irq function pointers
7669939009SMario Limonciello * Load microcode from filesystem
778da1170aSLeo Liu */
vcn_v4_0_early_init(void * handle)788da1170aSLeo Liu static int vcn_v4_0_early_init(void *handle)
798da1170aSLeo Liu {
808da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
81e68d1e07Sbobzhou int i;
828da1170aSLeo Liu
836dcb38a1SJane Jian if (amdgpu_sriov_vf(adev)) {
84aa44beb5SJane Jian adev->vcn.harvest_config = VCN_HARVEST_MMSCH;
85e68d1e07Sbobzhou for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
866dcb38a1SJane Jian if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {
876dcb38a1SJane Jian adev->vcn.harvest_config |= 1 << i;
886dcb38a1SJane Jian dev_info(adev->dev, "VCN%d is disabled by hypervisor\n", i);
896dcb38a1SJane Jian }
906dcb38a1SJane Jian }
916dcb38a1SJane Jian }
92aa44beb5SJane Jian
93bb4f196bSRuijing Dong /* re-use enc ring as unified ring */
948da1170aSLeo Liu adev->vcn.num_enc_rings = 1;
958da1170aSLeo Liu
96bb4f196bSRuijing Dong vcn_v4_0_set_unified_ring_funcs(adev);
978da1170aSLeo Liu vcn_v4_0_set_irq_funcs(adev);
98377d0221STao Zhou vcn_v4_0_set_ras_funcs(adev);
998da1170aSLeo Liu
10069939009SMario Limonciello return amdgpu_vcn_early_init(adev);
1018da1170aSLeo Liu }
1028da1170aSLeo Liu
1038da1170aSLeo Liu /**
1048da1170aSLeo Liu * vcn_v4_0_sw_init - sw init for VCN block
1058da1170aSLeo Liu *
1068da1170aSLeo Liu * @handle: amdgpu_device pointer
1078da1170aSLeo Liu *
1088da1170aSLeo Liu * Load firmware and sw initialization
1098da1170aSLeo Liu */
vcn_v4_0_sw_init(void * handle)1108da1170aSLeo Liu static int vcn_v4_0_sw_init(void *handle)
1118da1170aSLeo Liu {
1128da1170aSLeo Liu struct amdgpu_ring *ring;
1138da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
114bb4f196bSRuijing Dong int i, r;
1158da1170aSLeo Liu
1168da1170aSLeo Liu r = amdgpu_vcn_sw_init(adev);
1178da1170aSLeo Liu if (r)
1188da1170aSLeo Liu return r;
1198da1170aSLeo Liu
1208da1170aSLeo Liu amdgpu_vcn_setup_ucode(adev);
1218da1170aSLeo Liu
1228da1170aSLeo Liu r = amdgpu_vcn_resume(adev);
1238da1170aSLeo Liu if (r)
1248da1170aSLeo Liu return r;
1258da1170aSLeo Liu
1268da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1278da1170aSLeo Liu volatile struct amdgpu_vcn4_fw_shared *fw_shared;
128bb4f196bSRuijing Dong
1298da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i))
1308da1170aSLeo Liu continue;
1318da1170aSLeo Liu
132188d3f80SSonny Jiang /* Init instance 0 sched_score to 1, so it's scheduled after other instances */
133188d3f80SSonny Jiang if (i == 0)
134188d3f80SSonny Jiang atomic_set(&adev->vcn.inst[i].sched_score, 1);
135188d3f80SSonny Jiang else
1368da1170aSLeo Liu atomic_set(&adev->vcn.inst[i].sched_score, 0);
1378da1170aSLeo Liu
138bb4f196bSRuijing Dong /* VCN UNIFIED TRAP */
1398da1170aSLeo Liu r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
140bb4f196bSRuijing Dong VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
1418da1170aSLeo Liu if (r)
1428da1170aSLeo Liu return r;
1438da1170aSLeo Liu
144ea5309deSTao Zhou /* VCN POISON TRAP */
145ea5309deSTao Zhou r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
14666a11ecbSHoratio Zhang VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].ras_poison_irq);
147ea5309deSTao Zhou if (r)
148ea5309deSTao Zhou return r;
149ea5309deSTao Zhou
150bb4f196bSRuijing Dong ring = &adev->vcn.inst[i].ring_enc[0];
1518da1170aSLeo Liu ring->use_doorbell = true;
152aa44beb5SJane Jian if (amdgpu_sriov_vf(adev))
15398928baeSJane Jian ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1) + 1;
154aa44beb5SJane Jian else
155bb4f196bSRuijing Dong ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
156f4caf584SHawking Zhang ring->vm_hub = AMDGPU_MMHUB0(0);
157bb4f196bSRuijing Dong sprintf(ring->name, "vcn_unified_%d", i);
1588da1170aSLeo Liu
1598da1170aSLeo Liu r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
160bb4f196bSRuijing Dong AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
1618da1170aSLeo Liu if (r)
1628da1170aSLeo Liu return r;
1638da1170aSLeo Liu
1648da1170aSLeo Liu fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
165bb4f196bSRuijing Dong fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
1668da1170aSLeo Liu fw_shared->sq.is_enabled = 1;
1678da1170aSLeo Liu
168167be852SRuijing Dong fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
169167be852SRuijing Dong fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
170167be852SRuijing Dong AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
171167be852SRuijing Dong
172c6195ef5Ssguttula if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 2)) {
173c6195ef5Ssguttula fw_shared->present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT;
174c6195ef5Ssguttula fw_shared->drm_key_wa.method =
175c6195ef5Ssguttula AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING;
176c6195ef5Ssguttula }
177c6195ef5Ssguttula
178aa44beb5SJane Jian if (amdgpu_sriov_vf(adev))
179aa44beb5SJane Jian fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
180aa44beb5SJane Jian
1818da1170aSLeo Liu if (amdgpu_vcnfw_log)
1828da1170aSLeo Liu amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
1838da1170aSLeo Liu }
1848da1170aSLeo Liu
185aa44beb5SJane Jian if (amdgpu_sriov_vf(adev)) {
186aa44beb5SJane Jian r = amdgpu_virt_alloc_mm_table(adev);
187aa44beb5SJane Jian if (r)
188aa44beb5SJane Jian return r;
189aa44beb5SJane Jian }
190aa44beb5SJane Jian
1918da1170aSLeo Liu if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1928da1170aSLeo Liu adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode;
193bb4f196bSRuijing Dong
194f81c31d9SHawking Zhang r = amdgpu_vcn_ras_sw_init(adev);
195f81c31d9SHawking Zhang if (r)
196f81c31d9SHawking Zhang return r;
197f81c31d9SHawking Zhang
1988da1170aSLeo Liu return 0;
1998da1170aSLeo Liu }
2008da1170aSLeo Liu
2018da1170aSLeo Liu /**
2028da1170aSLeo Liu * vcn_v4_0_sw_fini - sw fini for VCN block
2038da1170aSLeo Liu *
2048da1170aSLeo Liu * @handle: amdgpu_device pointer
2058da1170aSLeo Liu *
2068da1170aSLeo Liu * VCN suspend and free up sw allocation
2078da1170aSLeo Liu */
vcn_v4_0_sw_fini(void * handle)2088da1170aSLeo Liu static int vcn_v4_0_sw_fini(void *handle)
2098da1170aSLeo Liu {
2108da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2118da1170aSLeo Liu int i, r, idx;
2128da1170aSLeo Liu
2138585732bSGuchun Chen if (drm_dev_enter(adev_to_drm(adev), &idx)) {
2148da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2158da1170aSLeo Liu volatile struct amdgpu_vcn4_fw_shared *fw_shared;
2168da1170aSLeo Liu
2178da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i))
2188da1170aSLeo Liu continue;
2198da1170aSLeo Liu
2208da1170aSLeo Liu fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
2218da1170aSLeo Liu fw_shared->present_flag_0 = 0;
2228da1170aSLeo Liu fw_shared->sq.is_enabled = 0;
2238da1170aSLeo Liu }
2248da1170aSLeo Liu
2258da1170aSLeo Liu drm_dev_exit(idx);
2268da1170aSLeo Liu }
2278da1170aSLeo Liu
228aa44beb5SJane Jian if (amdgpu_sriov_vf(adev))
229aa44beb5SJane Jian amdgpu_virt_free_mm_table(adev);
230aa44beb5SJane Jian
2318da1170aSLeo Liu r = amdgpu_vcn_suspend(adev);
2328da1170aSLeo Liu if (r)
2338da1170aSLeo Liu return r;
2348da1170aSLeo Liu
2358da1170aSLeo Liu r = amdgpu_vcn_sw_fini(adev);
2368da1170aSLeo Liu
2378da1170aSLeo Liu return r;
2388da1170aSLeo Liu }
2398da1170aSLeo Liu
2408da1170aSLeo Liu /**
2418da1170aSLeo Liu * vcn_v4_0_hw_init - start and test VCN block
2428da1170aSLeo Liu *
2438da1170aSLeo Liu * @handle: amdgpu_device pointer
2448da1170aSLeo Liu *
2458da1170aSLeo Liu * Initialize the hardware, boot up the VCPU and do some testing
2468da1170aSLeo Liu */
vcn_v4_0_hw_init(void * handle)2478da1170aSLeo Liu static int vcn_v4_0_hw_init(void *handle)
2488da1170aSLeo Liu {
2498da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2508da1170aSLeo Liu struct amdgpu_ring *ring;
251bb4f196bSRuijing Dong int i, r;
2528da1170aSLeo Liu
253aa44beb5SJane Jian if (amdgpu_sriov_vf(adev)) {
254aa44beb5SJane Jian r = vcn_v4_0_start_sriov(adev);
255aa44beb5SJane Jian if (r)
256aa44beb5SJane Jian goto done;
257aa44beb5SJane Jian
258aa44beb5SJane Jian for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
259aa44beb5SJane Jian if (adev->vcn.harvest_config & (1 << i))
260aa44beb5SJane Jian continue;
261aa44beb5SJane Jian
262aa44beb5SJane Jian ring = &adev->vcn.inst[i].ring_enc[0];
263aa44beb5SJane Jian ring->wptr = 0;
264aa44beb5SJane Jian ring->wptr_old = 0;
265aa44beb5SJane Jian vcn_v4_0_unified_ring_set_wptr(ring);
266aa44beb5SJane Jian ring->sched.ready = true;
2676dcb38a1SJane Jian
268aa44beb5SJane Jian }
269aa44beb5SJane Jian } else {
2708da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2718da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i))
2728da1170aSLeo Liu continue;
273bb4f196bSRuijing Dong
2748da1170aSLeo Liu ring = &adev->vcn.inst[i].ring_enc[0];
2758da1170aSLeo Liu
2768da1170aSLeo Liu adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
2778da1170aSLeo Liu ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
2788da1170aSLeo Liu
2798da1170aSLeo Liu r = amdgpu_ring_test_helper(ring);
2808da1170aSLeo Liu if (r)
2818da1170aSLeo Liu goto done;
282aa44beb5SJane Jian
283aa44beb5SJane Jian }
2848da1170aSLeo Liu }
2858da1170aSLeo Liu
2868da1170aSLeo Liu done:
2878da1170aSLeo Liu if (!r)
2888da1170aSLeo Liu DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
2898da1170aSLeo Liu (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
2908da1170aSLeo Liu
2918da1170aSLeo Liu return r;
2928da1170aSLeo Liu }
2938da1170aSLeo Liu
2948da1170aSLeo Liu /**
2958da1170aSLeo Liu * vcn_v4_0_hw_fini - stop the hardware block
2968da1170aSLeo Liu *
2978da1170aSLeo Liu * @handle: amdgpu_device pointer
2988da1170aSLeo Liu *
2998da1170aSLeo Liu * Stop the VCN block, mark ring as not ready any more
3008da1170aSLeo Liu */
vcn_v4_0_hw_fini(void * handle)3018da1170aSLeo Liu static int vcn_v4_0_hw_fini(void *handle)
3028da1170aSLeo Liu {
3038da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3048da1170aSLeo Liu int i;
3058da1170aSLeo Liu
3068da1170aSLeo Liu cancel_delayed_work_sync(&adev->vcn.idle_work);
3078da1170aSLeo Liu
3088da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
3098da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i))
3108da1170aSLeo Liu continue;
311aa44beb5SJane Jian if (!amdgpu_sriov_vf(adev)) {
3128da1170aSLeo Liu if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
3138da1170aSLeo Liu (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
3148da1170aSLeo Liu RREG32_SOC15(VCN, i, regUVD_STATUS))) {
3158da1170aSLeo Liu vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
3168da1170aSLeo Liu }
3178da1170aSLeo Liu }
31866a11ecbSHoratio Zhang if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
31966a11ecbSHoratio Zhang amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
320aa44beb5SJane Jian }
321aa44beb5SJane Jian
3228da1170aSLeo Liu return 0;
3238da1170aSLeo Liu }
3248da1170aSLeo Liu
3258da1170aSLeo Liu /**
3268da1170aSLeo Liu * vcn_v4_0_suspend - suspend VCN block
3278da1170aSLeo Liu *
3288da1170aSLeo Liu * @handle: amdgpu_device pointer
3298da1170aSLeo Liu *
3308da1170aSLeo Liu * HW fini and suspend VCN block
3318da1170aSLeo Liu */
vcn_v4_0_suspend(void * handle)3328da1170aSLeo Liu static int vcn_v4_0_suspend(void *handle)
3338da1170aSLeo Liu {
3348da1170aSLeo Liu int r;
3358da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3368da1170aSLeo Liu
3378da1170aSLeo Liu r = vcn_v4_0_hw_fini(adev);
3388da1170aSLeo Liu if (r)
3398da1170aSLeo Liu return r;
3408da1170aSLeo Liu
3418da1170aSLeo Liu r = amdgpu_vcn_suspend(adev);
3428da1170aSLeo Liu
3438da1170aSLeo Liu return r;
3448da1170aSLeo Liu }
3458da1170aSLeo Liu
3468da1170aSLeo Liu /**
3478da1170aSLeo Liu * vcn_v4_0_resume - resume VCN block
3488da1170aSLeo Liu *
3498da1170aSLeo Liu * @handle: amdgpu_device pointer
3508da1170aSLeo Liu *
3518da1170aSLeo Liu * Resume firmware and hw init VCN block
3528da1170aSLeo Liu */
vcn_v4_0_resume(void * handle)3538da1170aSLeo Liu static int vcn_v4_0_resume(void *handle)
3548da1170aSLeo Liu {
3558da1170aSLeo Liu int r;
3568da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3578da1170aSLeo Liu
3588da1170aSLeo Liu r = amdgpu_vcn_resume(adev);
3598da1170aSLeo Liu if (r)
3608da1170aSLeo Liu return r;
3618da1170aSLeo Liu
3628da1170aSLeo Liu r = vcn_v4_0_hw_init(adev);
3638da1170aSLeo Liu
3648da1170aSLeo Liu return r;
3658da1170aSLeo Liu }
3668da1170aSLeo Liu
3678da1170aSLeo Liu /**
3688da1170aSLeo Liu * vcn_v4_0_mc_resume - memory controller programming
3698da1170aSLeo Liu *
3708da1170aSLeo Liu * @adev: amdgpu_device pointer
3718da1170aSLeo Liu * @inst: instance number
3728da1170aSLeo Liu *
3738da1170aSLeo Liu * Let the VCN memory controller know it's offsets
3748da1170aSLeo Liu */
vcn_v4_0_mc_resume(struct amdgpu_device * adev,int inst)3758da1170aSLeo Liu static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst)
3768da1170aSLeo Liu {
3778da1170aSLeo Liu uint32_t offset, size;
3788da1170aSLeo Liu const struct common_firmware_header *hdr;
3798da1170aSLeo Liu
3808da1170aSLeo Liu hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
3818da1170aSLeo Liu size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
3828da1170aSLeo Liu
3838da1170aSLeo Liu /* cache window 0: fw */
3848da1170aSLeo Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3858da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
3868da1170aSLeo Liu (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
3878da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
3888da1170aSLeo Liu (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
3898da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
3908da1170aSLeo Liu offset = 0;
3918da1170aSLeo Liu } else {
3928da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
3938da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst].gpu_addr));
3948da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
3958da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst].gpu_addr));
3968da1170aSLeo Liu offset = size;
3978da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
3988da1170aSLeo Liu }
3998da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);
4008da1170aSLeo Liu
4018da1170aSLeo Liu /* cache window 1: stack */
4028da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
4038da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
4048da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
4058da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
4068da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);
4078da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
4088da1170aSLeo Liu
4098da1170aSLeo Liu /* cache window 2: context */
4108da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
4118da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
4128da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
4138da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
4148da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);
4158da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
4168da1170aSLeo Liu
4178da1170aSLeo Liu /* non-cache window */
4188da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
4198da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
4208da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
4218da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
4228da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
4238da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
4248da1170aSLeo Liu AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
4258da1170aSLeo Liu }
4268da1170aSLeo Liu
4278da1170aSLeo Liu /**
4288da1170aSLeo Liu * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode
4298da1170aSLeo Liu *
4308da1170aSLeo Liu * @adev: amdgpu_device pointer
4318da1170aSLeo Liu * @inst_idx: instance number index
4328da1170aSLeo Liu * @indirect: indirectly write sram
4338da1170aSLeo Liu *
4348da1170aSLeo Liu * Let the VCN memory controller know it's offsets with dpg mode
4358da1170aSLeo Liu */
vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device * adev,int inst_idx,bool indirect)4368da1170aSLeo Liu static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
4378da1170aSLeo Liu {
4388da1170aSLeo Liu uint32_t offset, size;
4398da1170aSLeo Liu const struct common_firmware_header *hdr;
4408da1170aSLeo Liu hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
4418da1170aSLeo Liu size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
4428da1170aSLeo Liu
4438da1170aSLeo Liu /* cache window 0: fw */
4448da1170aSLeo Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4458da1170aSLeo Liu if (!indirect) {
4468da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4478da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
4488da1170aSLeo Liu (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
4498da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4508da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
4518da1170aSLeo Liu (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
4528da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4538da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
4548da1170aSLeo Liu } else {
4558da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4568da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
4578da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4588da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
4598da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4608da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
4618da1170aSLeo Liu }
4628da1170aSLeo Liu offset = 0;
4638da1170aSLeo Liu } else {
4648da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4658da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
4668da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
4678da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4688da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
4698da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
4708da1170aSLeo Liu offset = size;
4718da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4728da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
4738da1170aSLeo Liu AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
4748da1170aSLeo Liu }
4758da1170aSLeo Liu
4768da1170aSLeo Liu if (!indirect)
4778da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4788da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
4798da1170aSLeo Liu else
4808da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4818da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
4828da1170aSLeo Liu
4838da1170aSLeo Liu /* cache window 1: stack */
4848da1170aSLeo Liu if (!indirect) {
4858da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4868da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
4878da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
4888da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4898da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
4908da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
4918da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4928da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
4938da1170aSLeo Liu } else {
4948da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4958da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
4968da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4978da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
4988da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
4998da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
5008da1170aSLeo Liu }
5018da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
5028da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
5038da1170aSLeo Liu
5048da1170aSLeo Liu /* cache window 2: context */
5058da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
5068da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
5078da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
5088da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
5098da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
5108da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
5118da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
5128da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
5138da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
5148da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
5158da1170aSLeo Liu
5168da1170aSLeo Liu /* non-cache window */
5178da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
5188da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
5198da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
5208da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
5218da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
5228da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
5238da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
5248da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
5258da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
5268da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),
5278da1170aSLeo Liu AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
5288da1170aSLeo Liu
5298da1170aSLeo Liu /* VCN global tiling registers */
5308da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
5318da1170aSLeo Liu VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
5328da1170aSLeo Liu }
5338da1170aSLeo Liu
5348da1170aSLeo Liu /**
5358da1170aSLeo Liu * vcn_v4_0_disable_static_power_gating - disable VCN static power gating
5368da1170aSLeo Liu *
5378da1170aSLeo Liu * @adev: amdgpu_device pointer
5388da1170aSLeo Liu * @inst: instance number
5398da1170aSLeo Liu *
5408da1170aSLeo Liu * Disable static power gating for VCN block
5418da1170aSLeo Liu */
vcn_v4_0_disable_static_power_gating(struct amdgpu_device * adev,int inst)5428da1170aSLeo Liu static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
5438da1170aSLeo Liu {
5448da1170aSLeo Liu uint32_t data = 0;
5458da1170aSLeo Liu
5468da1170aSLeo Liu if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
5478da1170aSLeo Liu data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
5488da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
5498da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
5508da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
5518da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
5528da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
5538da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
5548da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
5558da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
5568da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
5578da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
5588da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
5598da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
5608da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
5618da1170aSLeo Liu
5628da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
5638da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS,
5648da1170aSLeo Liu UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF);
5658da1170aSLeo Liu } else {
5668da1170aSLeo Liu uint32_t value;
5678da1170aSLeo Liu
5688da1170aSLeo Liu value = (inst) ? 0x2200800 : 0;
5698da1170aSLeo Liu data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
5708da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
5718da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
5728da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
5738da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
5748da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
5758da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
5768da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
5778da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
5788da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
5798da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
5808da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
5818da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
5828da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
5838da1170aSLeo Liu
5848da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
5858da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF);
5868da1170aSLeo Liu }
5878da1170aSLeo Liu
5888da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
5898da1170aSLeo Liu data &= ~0x103;
5908da1170aSLeo Liu if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
5918da1170aSLeo Liu data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
5928da1170aSLeo Liu UVD_POWER_STATUS__UVD_PG_EN_MASK;
5938da1170aSLeo Liu
5948da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
5958da1170aSLeo Liu
5968da1170aSLeo Liu return;
5978da1170aSLeo Liu }
5988da1170aSLeo Liu
5998da1170aSLeo Liu /**
6008da1170aSLeo Liu * vcn_v4_0_enable_static_power_gating - enable VCN static power gating
6018da1170aSLeo Liu *
6028da1170aSLeo Liu * @adev: amdgpu_device pointer
6038da1170aSLeo Liu * @inst: instance number
6048da1170aSLeo Liu *
6058da1170aSLeo Liu * Enable static power gating for VCN block
6068da1170aSLeo Liu */
vcn_v4_0_enable_static_power_gating(struct amdgpu_device * adev,int inst)6078da1170aSLeo Liu static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
6088da1170aSLeo Liu {
6098da1170aSLeo Liu uint32_t data;
6108da1170aSLeo Liu
6118da1170aSLeo Liu if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
6128da1170aSLeo Liu /* Before power off, this indicator has to be turned on */
6138da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
6148da1170aSLeo Liu data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
6158da1170aSLeo Liu data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
6168da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
6178da1170aSLeo Liu
6188da1170aSLeo Liu data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
6198da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
6208da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
6218da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
6228da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
6238da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
6248da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
6258da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
6268da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
6278da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
6288da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
6298da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
6308da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
6318da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
6328da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
6338da1170aSLeo Liu
6348da1170aSLeo Liu data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
6358da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT
6368da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
6378da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT
6388da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
6398da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT
6408da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT
6418da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
6428da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
6438da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
6448da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT
6458da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT
6468da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
6478da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
6488da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
6498da1170aSLeo Liu }
6508da1170aSLeo Liu
6518da1170aSLeo Liu return;
6528da1170aSLeo Liu }
6538da1170aSLeo Liu
6548da1170aSLeo Liu /**
6558da1170aSLeo Liu * vcn_v4_0_disable_clock_gating - disable VCN clock gating
6568da1170aSLeo Liu *
6578da1170aSLeo Liu * @adev: amdgpu_device pointer
6588da1170aSLeo Liu * @inst: instance number
6598da1170aSLeo Liu *
6608da1170aSLeo Liu * Disable clock gating for VCN block
6618da1170aSLeo Liu */
vcn_v4_0_disable_clock_gating(struct amdgpu_device * adev,int inst)6628da1170aSLeo Liu static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
6638da1170aSLeo Liu {
6648da1170aSLeo Liu uint32_t data;
6658da1170aSLeo Liu
6668da1170aSLeo Liu if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
6678da1170aSLeo Liu return;
6688da1170aSLeo Liu
6698da1170aSLeo Liu /* VCN disable CGC */
6708da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
6718da1170aSLeo Liu data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
6728da1170aSLeo Liu data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
6738da1170aSLeo Liu data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
6748da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
6758da1170aSLeo Liu
6768da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);
6778da1170aSLeo Liu data &= ~(UVD_CGC_GATE__SYS_MASK
6788da1170aSLeo Liu | UVD_CGC_GATE__UDEC_MASK
6798da1170aSLeo Liu | UVD_CGC_GATE__MPEG2_MASK
6808da1170aSLeo Liu | UVD_CGC_GATE__REGS_MASK
6818da1170aSLeo Liu | UVD_CGC_GATE__RBC_MASK
6828da1170aSLeo Liu | UVD_CGC_GATE__LMI_MC_MASK
6838da1170aSLeo Liu | UVD_CGC_GATE__LMI_UMC_MASK
6848da1170aSLeo Liu | UVD_CGC_GATE__IDCT_MASK
6858da1170aSLeo Liu | UVD_CGC_GATE__MPRD_MASK
6868da1170aSLeo Liu | UVD_CGC_GATE__MPC_MASK
6878da1170aSLeo Liu | UVD_CGC_GATE__LBSI_MASK
6888da1170aSLeo Liu | UVD_CGC_GATE__LRBBM_MASK
6898da1170aSLeo Liu | UVD_CGC_GATE__UDEC_RE_MASK
6908da1170aSLeo Liu | UVD_CGC_GATE__UDEC_CM_MASK
6918da1170aSLeo Liu | UVD_CGC_GATE__UDEC_IT_MASK
6928da1170aSLeo Liu | UVD_CGC_GATE__UDEC_DB_MASK
6938da1170aSLeo Liu | UVD_CGC_GATE__UDEC_MP_MASK
6948da1170aSLeo Liu | UVD_CGC_GATE__WCB_MASK
6958da1170aSLeo Liu | UVD_CGC_GATE__VCPU_MASK
6968da1170aSLeo Liu | UVD_CGC_GATE__MMSCH_MASK);
6978da1170aSLeo Liu
6988da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data);
6998da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF);
7008da1170aSLeo Liu
7018da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
7028da1170aSLeo Liu data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
7038da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
7048da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
7058da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
7068da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
7078da1170aSLeo Liu | UVD_CGC_CTRL__SYS_MODE_MASK
7088da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_MODE_MASK
7098da1170aSLeo Liu | UVD_CGC_CTRL__MPEG2_MODE_MASK
7108da1170aSLeo Liu | UVD_CGC_CTRL__REGS_MODE_MASK
7118da1170aSLeo Liu | UVD_CGC_CTRL__RBC_MODE_MASK
7128da1170aSLeo Liu | UVD_CGC_CTRL__LMI_MC_MODE_MASK
7138da1170aSLeo Liu | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
7148da1170aSLeo Liu | UVD_CGC_CTRL__IDCT_MODE_MASK
7158da1170aSLeo Liu | UVD_CGC_CTRL__MPRD_MODE_MASK
7168da1170aSLeo Liu | UVD_CGC_CTRL__MPC_MODE_MASK
7178da1170aSLeo Liu | UVD_CGC_CTRL__LBSI_MODE_MASK
7188da1170aSLeo Liu | UVD_CGC_CTRL__LRBBM_MODE_MASK
7198da1170aSLeo Liu | UVD_CGC_CTRL__WCB_MODE_MASK
7208da1170aSLeo Liu | UVD_CGC_CTRL__VCPU_MODE_MASK
7218da1170aSLeo Liu | UVD_CGC_CTRL__MMSCH_MODE_MASK);
7228da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
7238da1170aSLeo Liu
7248da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);
7258da1170aSLeo Liu data |= (UVD_SUVD_CGC_GATE__SRE_MASK
7268da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SIT_MASK
7278da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SMP_MASK
7288da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SCM_MASK
7298da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SDB_MASK
7308da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SRE_H264_MASK
7318da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
7328da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SIT_H264_MASK
7338da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
7348da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SCM_H264_MASK
7358da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
7368da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SDB_H264_MASK
7378da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
7388da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SCLR_MASK
7398da1170aSLeo Liu | UVD_SUVD_CGC_GATE__UVD_SC_MASK
7408da1170aSLeo Liu | UVD_SUVD_CGC_GATE__ENT_MASK
7418da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
7428da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
7438da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SITE_MASK
7448da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
7458da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
7468da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
7478da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
7488da1170aSLeo Liu | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
7498da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data);
7508da1170aSLeo Liu
7518da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
7528da1170aSLeo Liu data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
7538da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
7548da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
7558da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
7568da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
7578da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
7588da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
7598da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
7608da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
7618da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
7628da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
7638da1170aSLeo Liu }
7648da1170aSLeo Liu
7658da1170aSLeo Liu /**
7668da1170aSLeo Liu * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
7678da1170aSLeo Liu *
7688da1170aSLeo Liu * @adev: amdgpu_device pointer
7698da1170aSLeo Liu * @sram_sel: sram select
7708da1170aSLeo Liu * @inst_idx: instance number index
7718da1170aSLeo Liu * @indirect: indirectly write sram
7728da1170aSLeo Liu *
7738da1170aSLeo Liu * Disable clock gating for VCN block with dpg mode
7748da1170aSLeo Liu */
vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device * adev,uint8_t sram_sel,int inst_idx,uint8_t indirect)7758da1170aSLeo Liu static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,
7768da1170aSLeo Liu int inst_idx, uint8_t indirect)
7778da1170aSLeo Liu {
7788da1170aSLeo Liu uint32_t reg_data = 0;
7798da1170aSLeo Liu
7808da1170aSLeo Liu if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
7818da1170aSLeo Liu return;
7828da1170aSLeo Liu
7838da1170aSLeo Liu /* enable sw clock gating control */
7848da1170aSLeo Liu reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
7858da1170aSLeo Liu reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
7868da1170aSLeo Liu reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
7878da1170aSLeo Liu reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
7888da1170aSLeo Liu UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
7898da1170aSLeo Liu UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
7908da1170aSLeo Liu UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
7918da1170aSLeo Liu UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
7928da1170aSLeo Liu UVD_CGC_CTRL__SYS_MODE_MASK |
7938da1170aSLeo Liu UVD_CGC_CTRL__UDEC_MODE_MASK |
7948da1170aSLeo Liu UVD_CGC_CTRL__MPEG2_MODE_MASK |
7958da1170aSLeo Liu UVD_CGC_CTRL__REGS_MODE_MASK |
7968da1170aSLeo Liu UVD_CGC_CTRL__RBC_MODE_MASK |
7978da1170aSLeo Liu UVD_CGC_CTRL__LMI_MC_MODE_MASK |
7988da1170aSLeo Liu UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
7998da1170aSLeo Liu UVD_CGC_CTRL__IDCT_MODE_MASK |
8008da1170aSLeo Liu UVD_CGC_CTRL__MPRD_MODE_MASK |
8018da1170aSLeo Liu UVD_CGC_CTRL__MPC_MODE_MASK |
8028da1170aSLeo Liu UVD_CGC_CTRL__LBSI_MODE_MASK |
8038da1170aSLeo Liu UVD_CGC_CTRL__LRBBM_MODE_MASK |
8048da1170aSLeo Liu UVD_CGC_CTRL__WCB_MODE_MASK |
8058da1170aSLeo Liu UVD_CGC_CTRL__VCPU_MODE_MASK);
8068da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
8078da1170aSLeo Liu VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
8088da1170aSLeo Liu
8098da1170aSLeo Liu /* turn off clock gating */
8108da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
8118da1170aSLeo Liu VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);
8128da1170aSLeo Liu
8138da1170aSLeo Liu /* turn on SUVD clock gating */
8148da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
8158da1170aSLeo Liu VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
8168da1170aSLeo Liu
8178da1170aSLeo Liu /* turn on sw mode in UVD_SUVD_CGC_CTRL */
8188da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
8198da1170aSLeo Liu VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
8208da1170aSLeo Liu }
8218da1170aSLeo Liu
8228da1170aSLeo Liu /**
8238da1170aSLeo Liu * vcn_v4_0_enable_clock_gating - enable VCN clock gating
8248da1170aSLeo Liu *
8258da1170aSLeo Liu * @adev: amdgpu_device pointer
8268da1170aSLeo Liu * @inst: instance number
8278da1170aSLeo Liu *
8288da1170aSLeo Liu * Enable clock gating for VCN block
8298da1170aSLeo Liu */
vcn_v4_0_enable_clock_gating(struct amdgpu_device * adev,int inst)8308da1170aSLeo Liu static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
8318da1170aSLeo Liu {
8328da1170aSLeo Liu uint32_t data;
8338da1170aSLeo Liu
8348da1170aSLeo Liu if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
8358da1170aSLeo Liu return;
8368da1170aSLeo Liu
8378da1170aSLeo Liu /* enable VCN CGC */
8388da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
8398da1170aSLeo Liu data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
8408da1170aSLeo Liu data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
8418da1170aSLeo Liu data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
8428da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
8438da1170aSLeo Liu
8448da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
8458da1170aSLeo Liu data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
8468da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
8478da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
8488da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
8498da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
8508da1170aSLeo Liu | UVD_CGC_CTRL__SYS_MODE_MASK
8518da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_MODE_MASK
8528da1170aSLeo Liu | UVD_CGC_CTRL__MPEG2_MODE_MASK
8538da1170aSLeo Liu | UVD_CGC_CTRL__REGS_MODE_MASK
8548da1170aSLeo Liu | UVD_CGC_CTRL__RBC_MODE_MASK
8558da1170aSLeo Liu | UVD_CGC_CTRL__LMI_MC_MODE_MASK
8568da1170aSLeo Liu | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
8578da1170aSLeo Liu | UVD_CGC_CTRL__IDCT_MODE_MASK
8588da1170aSLeo Liu | UVD_CGC_CTRL__MPRD_MODE_MASK
8598da1170aSLeo Liu | UVD_CGC_CTRL__MPC_MODE_MASK
8608da1170aSLeo Liu | UVD_CGC_CTRL__LBSI_MODE_MASK
8618da1170aSLeo Liu | UVD_CGC_CTRL__LRBBM_MODE_MASK
8628da1170aSLeo Liu | UVD_CGC_CTRL__WCB_MODE_MASK
8638da1170aSLeo Liu | UVD_CGC_CTRL__VCPU_MODE_MASK
8648da1170aSLeo Liu | UVD_CGC_CTRL__MMSCH_MODE_MASK);
8658da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
8668da1170aSLeo Liu
8678da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
8688da1170aSLeo Liu data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
8698da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
8708da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
8718da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
8728da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
8738da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
8748da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
8758da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
8768da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
8778da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
8788da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
8798da1170aSLeo Liu
8808da1170aSLeo Liu return;
8818da1170aSLeo Liu }
8828da1170aSLeo Liu
vcn_v4_0_enable_ras(struct amdgpu_device * adev,int inst_idx,bool indirect)8830422c34cSTao Zhou static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx,
8840422c34cSTao Zhou bool indirect)
8850422c34cSTao Zhou {
8860422c34cSTao Zhou uint32_t tmp;
8870422c34cSTao Zhou
8880422c34cSTao Zhou if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
8890422c34cSTao Zhou return;
8900422c34cSTao Zhou
8910422c34cSTao Zhou tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
8920422c34cSTao Zhou VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |
8930422c34cSTao Zhou VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |
8940422c34cSTao Zhou VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;
8950422c34cSTao Zhou WREG32_SOC15_DPG_MODE(inst_idx,
8960422c34cSTao Zhou SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL),
8970422c34cSTao Zhou tmp, 0, indirect);
8980422c34cSTao Zhou
8990422c34cSTao Zhou tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
9000422c34cSTao Zhou WREG32_SOC15_DPG_MODE(inst_idx,
9010422c34cSTao Zhou SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN),
9020422c34cSTao Zhou tmp, 0, indirect);
9030422c34cSTao Zhou }
9040422c34cSTao Zhou
9058da1170aSLeo Liu /**
9068da1170aSLeo Liu * vcn_v4_0_start_dpg_mode - VCN start with dpg mode
9078da1170aSLeo Liu *
9088da1170aSLeo Liu * @adev: amdgpu_device pointer
9098da1170aSLeo Liu * @inst_idx: instance number index
9108da1170aSLeo Liu * @indirect: indirectly write sram
9118da1170aSLeo Liu *
9128da1170aSLeo Liu * Start VCN block with dpg mode
9138da1170aSLeo Liu */
vcn_v4_0_start_dpg_mode(struct amdgpu_device * adev,int inst_idx,bool indirect)9148da1170aSLeo Liu static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
9158da1170aSLeo Liu {
9168da1170aSLeo Liu volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
9178da1170aSLeo Liu struct amdgpu_ring *ring;
9188da1170aSLeo Liu uint32_t tmp;
9198da1170aSLeo Liu
9208da1170aSLeo Liu /* disable register anti-hang mechanism */
9218da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
9228da1170aSLeo Liu ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
9238da1170aSLeo Liu /* enable dynamic power gating mode */
9248da1170aSLeo Liu tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);
9258da1170aSLeo Liu tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
9268da1170aSLeo Liu tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
9278da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);
9288da1170aSLeo Liu
9298da1170aSLeo Liu if (indirect)
9308da1170aSLeo Liu adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
9318da1170aSLeo Liu
9328da1170aSLeo Liu /* enable clock gating */
9338da1170aSLeo Liu vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
9348da1170aSLeo Liu
9358da1170aSLeo Liu /* enable VCPU clock */
9368da1170aSLeo Liu tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
9378da1170aSLeo Liu tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
9388da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
9398da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
9408da1170aSLeo Liu
9418da1170aSLeo Liu /* disable master interupt */
9428da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
9438da1170aSLeo Liu VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);
9448da1170aSLeo Liu
9458da1170aSLeo Liu /* setup regUVD_LMI_CTRL */
9468da1170aSLeo Liu tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
9478da1170aSLeo Liu UVD_LMI_CTRL__REQ_MODE_MASK |
9488da1170aSLeo Liu UVD_LMI_CTRL__CRC_RESET_MASK |
9498da1170aSLeo Liu UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
9508da1170aSLeo Liu UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
9518da1170aSLeo Liu UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
9528da1170aSLeo Liu (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
9538da1170aSLeo Liu 0x00100000L);
9548da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
9558da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
9568da1170aSLeo Liu
9578da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
9588da1170aSLeo Liu VCN, inst_idx, regUVD_MPC_CNTL),
9598da1170aSLeo Liu 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
9608da1170aSLeo Liu
9618da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
9628da1170aSLeo Liu VCN, inst_idx, regUVD_MPC_SET_MUXA0),
9638da1170aSLeo Liu ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
9648da1170aSLeo Liu (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
9658da1170aSLeo Liu (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
9668da1170aSLeo Liu (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
9678da1170aSLeo Liu
9688da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
9698da1170aSLeo Liu VCN, inst_idx, regUVD_MPC_SET_MUXB0),
9708da1170aSLeo Liu ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
9718da1170aSLeo Liu (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
9728da1170aSLeo Liu (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
9738da1170aSLeo Liu (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
9748da1170aSLeo Liu
9758da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
9768da1170aSLeo Liu VCN, inst_idx, regUVD_MPC_SET_MUX),
9778da1170aSLeo Liu ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
9788da1170aSLeo Liu (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
9798da1170aSLeo Liu (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
9808da1170aSLeo Liu
9818da1170aSLeo Liu vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect);
9828da1170aSLeo Liu
9838da1170aSLeo Liu tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
9848da1170aSLeo Liu tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
9858da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
9868da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
9878da1170aSLeo Liu
9888da1170aSLeo Liu /* enable LMI MC and UMC channels */
9898da1170aSLeo Liu tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
9908da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
9918da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
9928da1170aSLeo Liu
9930422c34cSTao Zhou vcn_v4_0_enable_ras(adev, inst_idx, indirect);
9940422c34cSTao Zhou
9958da1170aSLeo Liu /* enable master interrupt */
9968da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
9978da1170aSLeo Liu VCN, inst_idx, regUVD_MASTINT_EN),
9988da1170aSLeo Liu UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
9998da1170aSLeo Liu
10008da1170aSLeo Liu
10018da1170aSLeo Liu if (indirect)
10021ddcdb7cSLang Yu amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
10038da1170aSLeo Liu
10048da1170aSLeo Liu ring = &adev->vcn.inst[inst_idx].ring_enc[0];
10058da1170aSLeo Liu
10068da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
10078da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
10088da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
1009bb4f196bSRuijing Dong
1010bb4f196bSRuijing Dong tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
1011bb4f196bSRuijing Dong tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
1012bb4f196bSRuijing Dong WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
1013bb4f196bSRuijing Dong fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
1014bb4f196bSRuijing Dong WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
1015bb4f196bSRuijing Dong WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);
1016bb4f196bSRuijing Dong
10178da1170aSLeo Liu tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
10188da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
10198da1170aSLeo Liu ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
10208da1170aSLeo Liu
1021bb4f196bSRuijing Dong tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
1022bb4f196bSRuijing Dong tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
1023bb4f196bSRuijing Dong WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
1024bb4f196bSRuijing Dong fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
1025bb4f196bSRuijing Dong
10268da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
10278da1170aSLeo Liu ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
10288da1170aSLeo Liu VCN_RB1_DB_CTRL__EN_MASK);
1029bb4f196bSRuijing Dong
10308da1170aSLeo Liu return 0;
10318da1170aSLeo Liu }
10328da1170aSLeo Liu
10338da1170aSLeo Liu
10348da1170aSLeo Liu /**
10358da1170aSLeo Liu * vcn_v4_0_start - VCN start
10368da1170aSLeo Liu *
10378da1170aSLeo Liu * @adev: amdgpu_device pointer
10388da1170aSLeo Liu *
10398da1170aSLeo Liu * Start VCN block
10408da1170aSLeo Liu */
vcn_v4_0_start(struct amdgpu_device * adev)10418da1170aSLeo Liu static int vcn_v4_0_start(struct amdgpu_device *adev)
10428da1170aSLeo Liu {
10438da1170aSLeo Liu volatile struct amdgpu_vcn4_fw_shared *fw_shared;
10448da1170aSLeo Liu struct amdgpu_ring *ring;
10458da1170aSLeo Liu uint32_t tmp;
10468da1170aSLeo Liu int i, j, k, r;
10478da1170aSLeo Liu
10488da1170aSLeo Liu if (adev->pm.dpm_enabled)
10498da1170aSLeo Liu amdgpu_dpm_enable_uvd(adev, true);
10508da1170aSLeo Liu
10518da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1052bb4f196bSRuijing Dong fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1053bb4f196bSRuijing Dong
10548da1170aSLeo Liu if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
10558da1170aSLeo Liu r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
10568da1170aSLeo Liu continue;
10578da1170aSLeo Liu }
10588da1170aSLeo Liu
10598da1170aSLeo Liu /* disable VCN power gating */
10608da1170aSLeo Liu vcn_v4_0_disable_static_power_gating(adev, i);
10618da1170aSLeo Liu
10628da1170aSLeo Liu /* set VCN status busy */
10638da1170aSLeo Liu tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
10648da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
10658da1170aSLeo Liu
10668da1170aSLeo Liu /*SW clock gating */
10678da1170aSLeo Liu vcn_v4_0_disable_clock_gating(adev, i);
10688da1170aSLeo Liu
10698da1170aSLeo Liu /* enable VCPU clock */
10708da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
10718da1170aSLeo Liu UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
10728da1170aSLeo Liu
10738da1170aSLeo Liu /* disable master interrupt */
10748da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
10758da1170aSLeo Liu ~UVD_MASTINT_EN__VCPU_EN_MASK);
10768da1170aSLeo Liu
10778da1170aSLeo Liu /* enable LMI MC and UMC channels */
10788da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
10798da1170aSLeo Liu ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
10808da1170aSLeo Liu
10818da1170aSLeo Liu tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
10828da1170aSLeo Liu tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
10838da1170aSLeo Liu tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
10848da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
10858da1170aSLeo Liu
10868da1170aSLeo Liu /* setup regUVD_LMI_CTRL */
10878da1170aSLeo Liu tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
10888da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
10898da1170aSLeo Liu UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
10908da1170aSLeo Liu UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
10918da1170aSLeo Liu UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
10928da1170aSLeo Liu UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
10938da1170aSLeo Liu
10948da1170aSLeo Liu /* setup regUVD_MPC_CNTL */
10958da1170aSLeo Liu tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
10968da1170aSLeo Liu tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
10978da1170aSLeo Liu tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
10988da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
10998da1170aSLeo Liu
11008da1170aSLeo Liu /* setup UVD_MPC_SET_MUXA0 */
11018da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
11028da1170aSLeo Liu ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
11038da1170aSLeo Liu (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
11048da1170aSLeo Liu (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
11058da1170aSLeo Liu (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
11068da1170aSLeo Liu
11078da1170aSLeo Liu /* setup UVD_MPC_SET_MUXB0 */
11088da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
11098da1170aSLeo Liu ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
11108da1170aSLeo Liu (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
11118da1170aSLeo Liu (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
11128da1170aSLeo Liu (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
11138da1170aSLeo Liu
11148da1170aSLeo Liu /* setup UVD_MPC_SET_MUX */
11158da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
11168da1170aSLeo Liu ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
11178da1170aSLeo Liu (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
11188da1170aSLeo Liu (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
11198da1170aSLeo Liu
11208da1170aSLeo Liu vcn_v4_0_mc_resume(adev, i);
11218da1170aSLeo Liu
11228da1170aSLeo Liu /* VCN global tiling registers */
11238da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
11248da1170aSLeo Liu adev->gfx.config.gb_addr_config);
11258da1170aSLeo Liu
11268da1170aSLeo Liu /* unblock VCPU register access */
11278da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
11288da1170aSLeo Liu ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
11298da1170aSLeo Liu
11308da1170aSLeo Liu /* release VCPU reset to boot */
11318da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
11328da1170aSLeo Liu ~UVD_VCPU_CNTL__BLK_RST_MASK);
11338da1170aSLeo Liu
11348da1170aSLeo Liu for (j = 0; j < 10; ++j) {
11358da1170aSLeo Liu uint32_t status;
11368da1170aSLeo Liu
11378da1170aSLeo Liu for (k = 0; k < 100; ++k) {
11388da1170aSLeo Liu status = RREG32_SOC15(VCN, i, regUVD_STATUS);
11398da1170aSLeo Liu if (status & 2)
11408da1170aSLeo Liu break;
11418da1170aSLeo Liu mdelay(10);
11428da1170aSLeo Liu if (amdgpu_emu_mode == 1)
11438da1170aSLeo Liu msleep(1);
11448da1170aSLeo Liu }
11458da1170aSLeo Liu
11468da1170aSLeo Liu if (amdgpu_emu_mode == 1) {
1147736f7308SSonny Jiang r = -1;
11488da1170aSLeo Liu if (status & 2) {
11498da1170aSLeo Liu r = 0;
11508da1170aSLeo Liu break;
11518da1170aSLeo Liu }
11528da1170aSLeo Liu } else {
11538da1170aSLeo Liu r = 0;
11548da1170aSLeo Liu if (status & 2)
11558da1170aSLeo Liu break;
11568da1170aSLeo Liu
1157bb4f196bSRuijing Dong dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
11588da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
11598da1170aSLeo Liu UVD_VCPU_CNTL__BLK_RST_MASK,
11608da1170aSLeo Liu ~UVD_VCPU_CNTL__BLK_RST_MASK);
11618da1170aSLeo Liu mdelay(10);
11628da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
11638da1170aSLeo Liu ~UVD_VCPU_CNTL__BLK_RST_MASK);
11648da1170aSLeo Liu
11658da1170aSLeo Liu mdelay(10);
11668da1170aSLeo Liu r = -1;
11678da1170aSLeo Liu }
11688da1170aSLeo Liu }
11698da1170aSLeo Liu
11708da1170aSLeo Liu if (r) {
1171bb4f196bSRuijing Dong dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
11728da1170aSLeo Liu return r;
11738da1170aSLeo Liu }
11748da1170aSLeo Liu
11758da1170aSLeo Liu /* enable master interrupt */
11768da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
11778da1170aSLeo Liu UVD_MASTINT_EN__VCPU_EN_MASK,
11788da1170aSLeo Liu ~UVD_MASTINT_EN__VCPU_EN_MASK);
11798da1170aSLeo Liu
11808da1170aSLeo Liu /* clear the busy bit of VCN_STATUS */
11818da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
11828da1170aSLeo Liu ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
11838da1170aSLeo Liu
11848da1170aSLeo Liu ring = &adev->vcn.inst[i].ring_enc[0];
11858da1170aSLeo Liu WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
11868da1170aSLeo Liu ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
11878da1170aSLeo Liu VCN_RB1_DB_CTRL__EN_MASK);
1188bb4f196bSRuijing Dong
11898da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
11908da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
11918da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
1192bb4f196bSRuijing Dong
1193bb4f196bSRuijing Dong tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1194bb4f196bSRuijing Dong tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
1195bb4f196bSRuijing Dong WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1196bb4f196bSRuijing Dong fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
1197bb4f196bSRuijing Dong WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
1198bb4f196bSRuijing Dong WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
1199bb4f196bSRuijing Dong
1200bb4f196bSRuijing Dong tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
1201bb4f196bSRuijing Dong WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
1202bb4f196bSRuijing Dong ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
1203bb4f196bSRuijing Dong
1204bb4f196bSRuijing Dong tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1205bb4f196bSRuijing Dong tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
1206bb4f196bSRuijing Dong WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
12078da1170aSLeo Liu fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
12088da1170aSLeo Liu }
12098da1170aSLeo Liu
12108da1170aSLeo Liu return 0;
12118da1170aSLeo Liu }
12128da1170aSLeo Liu
vcn_v4_0_start_sriov(struct amdgpu_device * adev)1213aa44beb5SJane Jian static int vcn_v4_0_start_sriov(struct amdgpu_device *adev)
1214aa44beb5SJane Jian {
1215aa44beb5SJane Jian int i;
1216aa44beb5SJane Jian struct amdgpu_ring *ring_enc;
1217aa44beb5SJane Jian uint64_t cache_addr;
1218aa44beb5SJane Jian uint64_t rb_enc_addr;
1219aa44beb5SJane Jian uint64_t ctx_addr;
1220aa44beb5SJane Jian uint32_t param, resp, expected;
1221aa44beb5SJane Jian uint32_t offset, cache_size;
1222aa44beb5SJane Jian uint32_t tmp, timeout;
1223aa44beb5SJane Jian
1224aa44beb5SJane Jian struct amdgpu_mm_table *table = &adev->virt.mm_table;
1225aa44beb5SJane Jian uint32_t *table_loc;
1226aa44beb5SJane Jian uint32_t table_size;
1227aa44beb5SJane Jian uint32_t size, size_dw;
1228aa44beb5SJane Jian uint32_t init_status;
1229aa44beb5SJane Jian uint32_t enabled_vcn;
1230aa44beb5SJane Jian
1231aa44beb5SJane Jian struct mmsch_v4_0_cmd_direct_write
1232aa44beb5SJane Jian direct_wt = { {0} };
1233aa44beb5SJane Jian struct mmsch_v4_0_cmd_direct_read_modify_write
1234aa44beb5SJane Jian direct_rd_mod_wt = { {0} };
1235aa44beb5SJane Jian struct mmsch_v4_0_cmd_end end = { {0} };
1236aa44beb5SJane Jian struct mmsch_v4_0_init_header header;
1237aa44beb5SJane Jian
1238aa44beb5SJane Jian volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1239aa44beb5SJane Jian volatile struct amdgpu_fw_shared_rb_setup *rb_setup;
1240aa44beb5SJane Jian
1241aa44beb5SJane Jian direct_wt.cmd_header.command_type =
1242aa44beb5SJane Jian MMSCH_COMMAND__DIRECT_REG_WRITE;
1243aa44beb5SJane Jian direct_rd_mod_wt.cmd_header.command_type =
1244aa44beb5SJane Jian MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1245aa44beb5SJane Jian end.cmd_header.command_type =
1246aa44beb5SJane Jian MMSCH_COMMAND__END;
1247aa44beb5SJane Jian
1248aa44beb5SJane Jian header.version = MMSCH_VERSION;
1249aa44beb5SJane Jian header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2;
1250f2bcc0c7SEmily Deng for (i = 0; i < MMSCH_V4_0_VCN_INSTANCES; i++) {
1251aa44beb5SJane Jian header.inst[i].init_status = 0;
1252aa44beb5SJane Jian header.inst[i].table_offset = 0;
1253aa44beb5SJane Jian header.inst[i].table_size = 0;
1254aa44beb5SJane Jian }
1255aa44beb5SJane Jian
1256aa44beb5SJane Jian table_loc = (uint32_t *)table->cpu_addr;
1257aa44beb5SJane Jian table_loc += header.total_size;
1258aa44beb5SJane Jian for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1259aa44beb5SJane Jian if (adev->vcn.harvest_config & (1 << i))
1260aa44beb5SJane Jian continue;
1261aa44beb5SJane Jian
1262aa44beb5SJane Jian table_size = 0;
1263aa44beb5SJane Jian
1264aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
1265aa44beb5SJane Jian regUVD_STATUS),
1266aa44beb5SJane Jian ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1267aa44beb5SJane Jian
1268aa44beb5SJane Jian cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1269aa44beb5SJane Jian
1270aa44beb5SJane Jian if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1271aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1272aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1273aa44beb5SJane Jian adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
1274aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1275aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1276aa44beb5SJane Jian adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
1277aa44beb5SJane Jian offset = 0;
1278aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1279aa44beb5SJane Jian regUVD_VCPU_CACHE_OFFSET0),
1280aa44beb5SJane Jian 0);
1281aa44beb5SJane Jian } else {
1282aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1283aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1284aa44beb5SJane Jian lower_32_bits(adev->vcn.inst[i].gpu_addr));
1285aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1286aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1287aa44beb5SJane Jian upper_32_bits(adev->vcn.inst[i].gpu_addr));
1288aa44beb5SJane Jian offset = cache_size;
1289aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1290aa44beb5SJane Jian regUVD_VCPU_CACHE_OFFSET0),
1291aa44beb5SJane Jian AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1292aa44beb5SJane Jian }
1293aa44beb5SJane Jian
1294aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1295aa44beb5SJane Jian regUVD_VCPU_CACHE_SIZE0),
1296aa44beb5SJane Jian cache_size);
1297aa44beb5SJane Jian
1298aa44beb5SJane Jian cache_addr = adev->vcn.inst[i].gpu_addr + offset;
1299aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1300aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1301aa44beb5SJane Jian lower_32_bits(cache_addr));
1302aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1303aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1304aa44beb5SJane Jian upper_32_bits(cache_addr));
1305aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1306aa44beb5SJane Jian regUVD_VCPU_CACHE_OFFSET1),
1307aa44beb5SJane Jian 0);
1308aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1309aa44beb5SJane Jian regUVD_VCPU_CACHE_SIZE1),
1310aa44beb5SJane Jian AMDGPU_VCN_STACK_SIZE);
1311aa44beb5SJane Jian
1312aa44beb5SJane Jian cache_addr = adev->vcn.inst[i].gpu_addr + offset +
1313aa44beb5SJane Jian AMDGPU_VCN_STACK_SIZE;
1314aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1315aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1316aa44beb5SJane Jian lower_32_bits(cache_addr));
1317aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1318aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1319aa44beb5SJane Jian upper_32_bits(cache_addr));
1320aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1321aa44beb5SJane Jian regUVD_VCPU_CACHE_OFFSET2),
1322aa44beb5SJane Jian 0);
1323aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1324aa44beb5SJane Jian regUVD_VCPU_CACHE_SIZE2),
1325aa44beb5SJane Jian AMDGPU_VCN_CONTEXT_SIZE);
1326aa44beb5SJane Jian
1327aa44beb5SJane Jian fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1328aa44beb5SJane Jian rb_setup = &fw_shared->rb_setup;
1329aa44beb5SJane Jian
1330aa44beb5SJane Jian ring_enc = &adev->vcn.inst[i].ring_enc[0];
1331aa44beb5SJane Jian ring_enc->wptr = 0;
1332aa44beb5SJane Jian rb_enc_addr = ring_enc->gpu_addr;
1333aa44beb5SJane Jian
1334aa44beb5SJane Jian rb_setup->is_rb_enabled_flags |= RB_ENABLED;
1335aa44beb5SJane Jian rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr);
1336aa44beb5SJane Jian rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr);
1337aa44beb5SJane Jian rb_setup->rb_size = ring_enc->ring_size / 4;
1338aa44beb5SJane Jian fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
1339aa44beb5SJane Jian
1340aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1341aa44beb5SJane Jian regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
1342aa44beb5SJane Jian lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
1343aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1344aa44beb5SJane Jian regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
1345aa44beb5SJane Jian upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
1346aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1347aa44beb5SJane Jian regUVD_VCPU_NONCACHE_SIZE0),
1348aa44beb5SJane Jian AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
1349aa44beb5SJane Jian
1350aa44beb5SJane Jian /* add end packet */
1351aa44beb5SJane Jian MMSCH_V4_0_INSERT_END();
1352aa44beb5SJane Jian
1353aa44beb5SJane Jian /* refine header */
1354aa44beb5SJane Jian header.inst[i].init_status = 0;
1355aa44beb5SJane Jian header.inst[i].table_offset = header.total_size;
1356aa44beb5SJane Jian header.inst[i].table_size = table_size;
1357aa44beb5SJane Jian header.total_size += table_size;
1358aa44beb5SJane Jian }
1359aa44beb5SJane Jian
1360aa44beb5SJane Jian /* Update init table header in memory */
1361aa44beb5SJane Jian size = sizeof(struct mmsch_v4_0_init_header);
1362aa44beb5SJane Jian table_loc = (uint32_t *)table->cpu_addr;
1363aa44beb5SJane Jian memcpy((void *)table_loc, &header, size);
1364aa44beb5SJane Jian
1365aa44beb5SJane Jian /* message MMSCH (in VCN[0]) to initialize this client
1366aa44beb5SJane Jian * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1367aa44beb5SJane Jian * of memory descriptor location
1368aa44beb5SJane Jian */
1369aa44beb5SJane Jian ctx_addr = table->gpu_addr;
1370aa44beb5SJane Jian WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1371aa44beb5SJane Jian WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1372aa44beb5SJane Jian
1373aa44beb5SJane Jian /* 2, update vmid of descriptor */
1374aa44beb5SJane Jian tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);
1375aa44beb5SJane Jian tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1376aa44beb5SJane Jian /* use domain0 for MM scheduler */
1377aa44beb5SJane Jian tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1378aa44beb5SJane Jian WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp);
1379aa44beb5SJane Jian
1380aa44beb5SJane Jian /* 3, notify mmsch about the size of this descriptor */
1381aa44beb5SJane Jian size = header.total_size;
1382aa44beb5SJane Jian WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size);
1383aa44beb5SJane Jian
1384aa44beb5SJane Jian /* 4, set resp to zero */
1385aa44beb5SJane Jian WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0);
1386aa44beb5SJane Jian
1387aa44beb5SJane Jian /* 5, kick off the initialization and wait until
1388aa44beb5SJane Jian * MMSCH_VF_MAILBOX_RESP becomes non-zero
1389aa44beb5SJane Jian */
1390aa44beb5SJane Jian param = 0x00000001;
1391aa44beb5SJane Jian WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param);
1392aa44beb5SJane Jian tmp = 0;
1393aa44beb5SJane Jian timeout = 1000;
1394aa44beb5SJane Jian resp = 0;
1395aa44beb5SJane Jian expected = MMSCH_VF_MAILBOX_RESP__OK;
1396aa44beb5SJane Jian while (resp != expected) {
1397aa44beb5SJane Jian resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP);
1398aa44beb5SJane Jian if (resp != 0)
1399aa44beb5SJane Jian break;
1400aa44beb5SJane Jian
1401aa44beb5SJane Jian udelay(10);
1402aa44beb5SJane Jian tmp = tmp + 10;
1403aa44beb5SJane Jian if (tmp >= timeout) {
1404aa44beb5SJane Jian DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1405aa44beb5SJane Jian " waiting for regMMSCH_VF_MAILBOX_RESP "\
1406aa44beb5SJane Jian "(expected=0x%08x, readback=0x%08x)\n",
1407aa44beb5SJane Jian tmp, expected, resp);
1408aa44beb5SJane Jian return -EBUSY;
1409aa44beb5SJane Jian }
1410aa44beb5SJane Jian }
1411aa44beb5SJane Jian enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0;
1412aa44beb5SJane Jian init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status;
1413aa44beb5SJane Jian if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
1414aa44beb5SJane Jian && init_status != MMSCH_VF_ENGINE_STATUS__PASS)
1415aa44beb5SJane Jian DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\
1416aa44beb5SJane Jian "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status);
1417aa44beb5SJane Jian
1418aa44beb5SJane Jian return 0;
1419aa44beb5SJane Jian }
1420aa44beb5SJane Jian
14218da1170aSLeo Liu /**
14228da1170aSLeo Liu * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode
14238da1170aSLeo Liu *
14248da1170aSLeo Liu * @adev: amdgpu_device pointer
14258da1170aSLeo Liu * @inst_idx: instance number index
14268da1170aSLeo Liu *
14278da1170aSLeo Liu * Stop VCN block with dpg mode
14288da1170aSLeo Liu */
vcn_v4_0_stop_dpg_mode(struct amdgpu_device * adev,int inst_idx)1429385bf5a8SKhalid Masum static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
14308da1170aSLeo Liu {
1431803f3181SEmily Deng struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
14328da1170aSLeo Liu uint32_t tmp;
14338da1170aSLeo Liu
1434803f3181SEmily Deng vcn_v4_0_pause_dpg_mode(adev, inst_idx, &state);
14358da1170aSLeo Liu /* Wait for power status to be 1 */
14368da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
14378da1170aSLeo Liu UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
14388da1170aSLeo Liu
14398da1170aSLeo Liu /* wait for read ptr to be equal to write ptr */
14408da1170aSLeo Liu tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
14418da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
14428da1170aSLeo Liu
14438da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
14448da1170aSLeo Liu UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
14458da1170aSLeo Liu
14468da1170aSLeo Liu /* disable dynamic power gating mode */
14478da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,
14488da1170aSLeo Liu ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
14498da1170aSLeo Liu }
14508da1170aSLeo Liu
14518da1170aSLeo Liu /**
14528da1170aSLeo Liu * vcn_v4_0_stop - VCN stop
14538da1170aSLeo Liu *
14548da1170aSLeo Liu * @adev: amdgpu_device pointer
14558da1170aSLeo Liu *
14568da1170aSLeo Liu * Stop VCN block
14578da1170aSLeo Liu */
vcn_v4_0_stop(struct amdgpu_device * adev)14588da1170aSLeo Liu static int vcn_v4_0_stop(struct amdgpu_device *adev)
14598da1170aSLeo Liu {
1460bb4f196bSRuijing Dong volatile struct amdgpu_vcn4_fw_shared *fw_shared;
14618da1170aSLeo Liu uint32_t tmp;
14628da1170aSLeo Liu int i, r = 0;
14638da1170aSLeo Liu
14648da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1465bb4f196bSRuijing Dong fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1466bb4f196bSRuijing Dong fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
1467bb4f196bSRuijing Dong
14688da1170aSLeo Liu if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1469385bf5a8SKhalid Masum vcn_v4_0_stop_dpg_mode(adev, i);
14708da1170aSLeo Liu continue;
14718da1170aSLeo Liu }
14728da1170aSLeo Liu
14738da1170aSLeo Liu /* wait for vcn idle */
14748da1170aSLeo Liu r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
14758da1170aSLeo Liu if (r)
14768da1170aSLeo Liu return r;
14778da1170aSLeo Liu
14788da1170aSLeo Liu tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
14798da1170aSLeo Liu UVD_LMI_STATUS__READ_CLEAN_MASK |
14808da1170aSLeo Liu UVD_LMI_STATUS__WRITE_CLEAN_MASK |
14818da1170aSLeo Liu UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
14828da1170aSLeo Liu r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
14838da1170aSLeo Liu if (r)
14848da1170aSLeo Liu return r;
14858da1170aSLeo Liu
14868da1170aSLeo Liu /* disable LMI UMC channel */
14878da1170aSLeo Liu tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
14888da1170aSLeo Liu tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
14898da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
14908da1170aSLeo Liu tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
14918da1170aSLeo Liu UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
14928da1170aSLeo Liu r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
14938da1170aSLeo Liu if (r)
14948da1170aSLeo Liu return r;
14958da1170aSLeo Liu
14968da1170aSLeo Liu /* block VCPU register access */
14978da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
14988da1170aSLeo Liu UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
14998da1170aSLeo Liu ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
15008da1170aSLeo Liu
15018da1170aSLeo Liu /* reset VCPU */
15028da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
15038da1170aSLeo Liu UVD_VCPU_CNTL__BLK_RST_MASK,
15048da1170aSLeo Liu ~UVD_VCPU_CNTL__BLK_RST_MASK);
15058da1170aSLeo Liu
15068da1170aSLeo Liu /* disable VCPU clock */
15078da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
15088da1170aSLeo Liu ~(UVD_VCPU_CNTL__CLK_EN_MASK));
15098da1170aSLeo Liu
15108da1170aSLeo Liu /* apply soft reset */
15118da1170aSLeo Liu tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
15128da1170aSLeo Liu tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
15138da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
15148da1170aSLeo Liu tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
15158da1170aSLeo Liu tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
15168da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
15178da1170aSLeo Liu
15188da1170aSLeo Liu /* clear status */
15198da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
15208da1170aSLeo Liu
15218da1170aSLeo Liu /* apply HW clock gating */
15228da1170aSLeo Liu vcn_v4_0_enable_clock_gating(adev, i);
15238da1170aSLeo Liu
15248da1170aSLeo Liu /* enable VCN power gating */
15258da1170aSLeo Liu vcn_v4_0_enable_static_power_gating(adev, i);
15268da1170aSLeo Liu }
15278da1170aSLeo Liu
15288da1170aSLeo Liu if (adev->pm.dpm_enabled)
15298da1170aSLeo Liu amdgpu_dpm_enable_uvd(adev, false);
15308da1170aSLeo Liu
15318da1170aSLeo Liu return 0;
15328da1170aSLeo Liu }
15338da1170aSLeo Liu
15348da1170aSLeo Liu /**
15358da1170aSLeo Liu * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode
15368da1170aSLeo Liu *
15378da1170aSLeo Liu * @adev: amdgpu_device pointer
15388da1170aSLeo Liu * @inst_idx: instance number index
15398da1170aSLeo Liu * @new_state: pause state
15408da1170aSLeo Liu *
15418da1170aSLeo Liu * Pause dpg mode for VCN block
15428da1170aSLeo Liu */
vcn_v4_0_pause_dpg_mode(struct amdgpu_device * adev,int inst_idx,struct dpg_pause_state * new_state)15438da1170aSLeo Liu static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
15448da1170aSLeo Liu struct dpg_pause_state *new_state)
15458da1170aSLeo Liu {
15468da1170aSLeo Liu uint32_t reg_data = 0;
15478da1170aSLeo Liu int ret_code;
15488da1170aSLeo Liu
15498da1170aSLeo Liu /* pause/unpause if state is changed */
15508da1170aSLeo Liu if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
15518da1170aSLeo Liu DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d",
15528da1170aSLeo Liu adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
15538da1170aSLeo Liu reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &
15548da1170aSLeo Liu (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
15558da1170aSLeo Liu
15568da1170aSLeo Liu if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
15578da1170aSLeo Liu ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,
15588da1170aSLeo Liu UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
15598da1170aSLeo Liu
15608da1170aSLeo Liu if (!ret_code) {
15618da1170aSLeo Liu /* pause DPG */
15628da1170aSLeo Liu reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
15638da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
15648da1170aSLeo Liu
15658da1170aSLeo Liu /* wait for ACK */
15668da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE,
15678da1170aSLeo Liu UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
15688da1170aSLeo Liu UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
15698da1170aSLeo Liu
15708da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS,
15718da1170aSLeo Liu UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
15728da1170aSLeo Liu }
15738da1170aSLeo Liu } else {
15748da1170aSLeo Liu /* unpause dpg, no need to wait */
15758da1170aSLeo Liu reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
15768da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
15778da1170aSLeo Liu }
15788da1170aSLeo Liu adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
15798da1170aSLeo Liu }
15808da1170aSLeo Liu
15818da1170aSLeo Liu return 0;
15828da1170aSLeo Liu }
15838da1170aSLeo Liu
15848da1170aSLeo Liu /**
1585bb4f196bSRuijing Dong * vcn_v4_0_unified_ring_get_rptr - get unified read pointer
15868da1170aSLeo Liu *
15878da1170aSLeo Liu * @ring: amdgpu_ring pointer
15888da1170aSLeo Liu *
1589bb4f196bSRuijing Dong * Returns the current hardware unified read pointer
15908da1170aSLeo Liu */
vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring * ring)1591bb4f196bSRuijing Dong static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring)
15928da1170aSLeo Liu {
15938da1170aSLeo Liu struct amdgpu_device *adev = ring->adev;
15948da1170aSLeo Liu
1595bb4f196bSRuijing Dong if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1596bb4f196bSRuijing Dong DRM_ERROR("wrong ring id is identified in %s", __func__);
15978da1170aSLeo Liu
15988da1170aSLeo Liu return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);
15998da1170aSLeo Liu }
16008da1170aSLeo Liu
16018da1170aSLeo Liu /**
1602bb4f196bSRuijing Dong * vcn_v4_0_unified_ring_get_wptr - get unified write pointer
16038da1170aSLeo Liu *
16048da1170aSLeo Liu * @ring: amdgpu_ring pointer
16058da1170aSLeo Liu *
1606bb4f196bSRuijing Dong * Returns the current hardware unified write pointer
16078da1170aSLeo Liu */
vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring * ring)1608bb4f196bSRuijing Dong static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring)
16098da1170aSLeo Liu {
16108da1170aSLeo Liu struct amdgpu_device *adev = ring->adev;
16118da1170aSLeo Liu
1612bb4f196bSRuijing Dong if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1613bb4f196bSRuijing Dong DRM_ERROR("wrong ring id is identified in %s", __func__);
1614bb4f196bSRuijing Dong
16158da1170aSLeo Liu if (ring->use_doorbell)
16168da1170aSLeo Liu return *ring->wptr_cpu_addr;
16178da1170aSLeo Liu else
16188da1170aSLeo Liu return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);
16198da1170aSLeo Liu }
16208da1170aSLeo Liu
16218da1170aSLeo Liu /**
1622bb4f196bSRuijing Dong * vcn_v4_0_unified_ring_set_wptr - set enc write pointer
16238da1170aSLeo Liu *
16248da1170aSLeo Liu * @ring: amdgpu_ring pointer
16258da1170aSLeo Liu *
16268da1170aSLeo Liu * Commits the enc write pointer to the hardware
16278da1170aSLeo Liu */
vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring * ring)1628bb4f196bSRuijing Dong static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring)
16298da1170aSLeo Liu {
16308da1170aSLeo Liu struct amdgpu_device *adev = ring->adev;
16318da1170aSLeo Liu
1632bb4f196bSRuijing Dong if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1633bb4f196bSRuijing Dong DRM_ERROR("wrong ring id is identified in %s", __func__);
1634bb4f196bSRuijing Dong
16358da1170aSLeo Liu if (ring->use_doorbell) {
16368da1170aSLeo Liu *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
16378da1170aSLeo Liu WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
16388da1170aSLeo Liu } else {
16398da1170aSLeo Liu WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
16408da1170aSLeo Liu }
16418da1170aSLeo Liu }
16428da1170aSLeo Liu
vcn_v4_0_limit_sched(struct amdgpu_cs_parser * p,struct amdgpu_job * job)1643c05d789fSChristian König static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p,
1644c05d789fSChristian König struct amdgpu_job *job)
16450b15205cSSonny Jiang {
16460b15205cSSonny Jiang struct drm_gpu_scheduler **scheds;
16470b15205cSSonny Jiang
16480b15205cSSonny Jiang /* The create msg must be in the first IB submitted */
1649c05d789fSChristian König if (atomic_read(&job->base.entity->fence_seq))
16500b15205cSSonny Jiang return -EINVAL;
16510b15205cSSonny Jiang
16526482ba5dSAlex Deucher /* if VCN0 is harvested, we can't support AV1 */
16536482ba5dSAlex Deucher if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
16546482ba5dSAlex Deucher return -EINVAL;
16556482ba5dSAlex Deucher
16560b15205cSSonny Jiang scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC]
16570b15205cSSonny Jiang [AMDGPU_RING_PRIO_0].sched;
1658c05d789fSChristian König drm_sched_entity_modify_sched(job->base.entity, scheds, 1);
16590b15205cSSonny Jiang return 0;
16600b15205cSSonny Jiang }
16610b15205cSSonny Jiang
vcn_v4_0_dec_msg(struct amdgpu_cs_parser * p,struct amdgpu_job * job,uint64_t addr)1662c05d789fSChristian König static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
1663c05d789fSChristian König uint64_t addr)
16640b15205cSSonny Jiang {
16650b15205cSSonny Jiang struct ttm_operation_ctx ctx = { false, false };
16660b15205cSSonny Jiang struct amdgpu_bo_va_mapping *map;
16670b15205cSSonny Jiang uint32_t *msg, num_buffers;
16680b15205cSSonny Jiang struct amdgpu_bo *bo;
16690b15205cSSonny Jiang uint64_t start, end;
16700b15205cSSonny Jiang unsigned int i;
16710b15205cSSonny Jiang void *ptr;
16720b15205cSSonny Jiang int r;
16730b15205cSSonny Jiang
16740b15205cSSonny Jiang addr &= AMDGPU_GMC_HOLE_MASK;
16750b15205cSSonny Jiang r = amdgpu_cs_find_mapping(p, addr, &bo, &map);
16760b15205cSSonny Jiang if (r) {
16770b15205cSSonny Jiang DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr);
16780b15205cSSonny Jiang return r;
16790b15205cSSonny Jiang }
16800b15205cSSonny Jiang
16810b15205cSSonny Jiang start = map->start * AMDGPU_GPU_PAGE_SIZE;
16820b15205cSSonny Jiang end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE;
16830b15205cSSonny Jiang if (addr & 0x7) {
16840b15205cSSonny Jiang DRM_ERROR("VCN messages must be 8 byte aligned!\n");
16850b15205cSSonny Jiang return -EINVAL;
16860b15205cSSonny Jiang }
16870b15205cSSonny Jiang
16880b15205cSSonny Jiang bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
16890b15205cSSonny Jiang amdgpu_bo_placement_from_domain(bo, bo->allowed_domains);
16900b15205cSSonny Jiang r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
16910b15205cSSonny Jiang if (r) {
16920b15205cSSonny Jiang DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r);
16930b15205cSSonny Jiang return r;
16940b15205cSSonny Jiang }
16950b15205cSSonny Jiang
16960b15205cSSonny Jiang r = amdgpu_bo_kmap(bo, &ptr);
16970b15205cSSonny Jiang if (r) {
16980b15205cSSonny Jiang DRM_ERROR("Failed mapping the VCN message (%d)!\n", r);
16990b15205cSSonny Jiang return r;
17000b15205cSSonny Jiang }
17010b15205cSSonny Jiang
17020b15205cSSonny Jiang msg = ptr + addr - start;
17030b15205cSSonny Jiang
17040b15205cSSonny Jiang /* Check length */
17050b15205cSSonny Jiang if (msg[1] > end - addr) {
17060b15205cSSonny Jiang r = -EINVAL;
17070b15205cSSonny Jiang goto out;
17080b15205cSSonny Jiang }
17090b15205cSSonny Jiang
17100b15205cSSonny Jiang if (msg[3] != RDECODE_MSG_CREATE)
17110b15205cSSonny Jiang goto out;
17120b15205cSSonny Jiang
17130b15205cSSonny Jiang num_buffers = msg[2];
17140b15205cSSonny Jiang for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) {
17150b15205cSSonny Jiang uint32_t offset, size, *create;
17160b15205cSSonny Jiang
17170b15205cSSonny Jiang if (msg[0] != RDECODE_MESSAGE_CREATE)
17180b15205cSSonny Jiang continue;
17190b15205cSSonny Jiang
17200b15205cSSonny Jiang offset = msg[1];
17210b15205cSSonny Jiang size = msg[2];
17220b15205cSSonny Jiang
17230b15205cSSonny Jiang if (offset + size > end) {
17240b15205cSSonny Jiang r = -EINVAL;
17250b15205cSSonny Jiang goto out;
17260b15205cSSonny Jiang }
17270b15205cSSonny Jiang
17280b15205cSSonny Jiang create = ptr + addr + offset - start;
17290b15205cSSonny Jiang
1730f823323bSDavid (Ming Qiang) Wu /* H264, HEVC and VP9 can run on any instance */
17310b15205cSSonny Jiang if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
17320b15205cSSonny Jiang continue;
17330b15205cSSonny Jiang
1734c05d789fSChristian König r = vcn_v4_0_limit_sched(p, job);
17350b15205cSSonny Jiang if (r)
17360b15205cSSonny Jiang goto out;
17370b15205cSSonny Jiang }
17380b15205cSSonny Jiang
17390b15205cSSonny Jiang out:
17400b15205cSSonny Jiang amdgpu_bo_kunmap(bo);
17410b15205cSSonny Jiang return r;
17420b15205cSSonny Jiang }
17430b15205cSSonny Jiang
1744f823323bSDavid (Ming Qiang) Wu #define RADEON_VCN_ENGINE_TYPE_ENCODE (0x00000002)
17450b15205cSSonny Jiang #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003)
17460b15205cSSonny Jiang
1747f823323bSDavid (Ming Qiang) Wu #define RADEON_VCN_ENGINE_INFO (0x30000001)
1748f823323bSDavid (Ming Qiang) Wu #define RADEON_VCN_ENGINE_INFO_MAX_OFFSET 16
1749f823323bSDavid (Ming Qiang) Wu
1750f823323bSDavid (Ming Qiang) Wu #define RENCODE_ENCODE_STANDARD_AV1 2
1751f823323bSDavid (Ming Qiang) Wu #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
1752f823323bSDavid (Ming Qiang) Wu #define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET 64
1753f823323bSDavid (Ming Qiang) Wu
1754f823323bSDavid (Ming Qiang) Wu /* return the offset in ib if id is found, -1 otherwise
1755f823323bSDavid (Ming Qiang) Wu * to speed up the searching we only search upto max_offset
1756f823323bSDavid (Ming Qiang) Wu */
vcn_v4_0_enc_find_ib_param(struct amdgpu_ib * ib,uint32_t id,int max_offset)1757f823323bSDavid (Ming Qiang) Wu static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset)
1758f823323bSDavid (Ming Qiang) Wu {
1759f823323bSDavid (Ming Qiang) Wu int i;
1760f823323bSDavid (Ming Qiang) Wu
1761f823323bSDavid (Ming Qiang) Wu for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) {
1762f823323bSDavid (Ming Qiang) Wu if (ib->ptr[i + 1] == id)
1763f823323bSDavid (Ming Qiang) Wu return i;
1764f823323bSDavid (Ming Qiang) Wu }
1765f823323bSDavid (Ming Qiang) Wu return -1;
1766f823323bSDavid (Ming Qiang) Wu }
1767f823323bSDavid (Ming Qiang) Wu
vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser * p,struct amdgpu_job * job,struct amdgpu_ib * ib)17680b15205cSSonny Jiang static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
17690b15205cSSonny Jiang struct amdgpu_job *job,
17700b15205cSSonny Jiang struct amdgpu_ib *ib)
17710b15205cSSonny Jiang {
1772c05d789fSChristian König struct amdgpu_ring *ring = amdgpu_job_ring(job);
1773c05d789fSChristian König struct amdgpu_vcn_decode_buffer *decode_buffer;
1774c05d789fSChristian König uint64_t addr;
17750b15205cSSonny Jiang uint32_t val;
1776f823323bSDavid (Ming Qiang) Wu int idx;
17770b15205cSSonny Jiang
17780b15205cSSonny Jiang /* The first instance can decode anything */
17790b15205cSSonny Jiang if (!ring->me)
1780c05d789fSChristian König return 0;
17810b15205cSSonny Jiang
1782f823323bSDavid (Ming Qiang) Wu /* RADEON_VCN_ENGINE_INFO is at the top of ib block */
1783f823323bSDavid (Ming Qiang) Wu idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO,
1784f823323bSDavid (Ming Qiang) Wu RADEON_VCN_ENGINE_INFO_MAX_OFFSET);
1785f823323bSDavid (Ming Qiang) Wu if (idx < 0) /* engine info is missing */
1786c05d789fSChristian König return 0;
17870b15205cSSonny Jiang
1788f823323bSDavid (Ming Qiang) Wu val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */
1789f823323bSDavid (Ming Qiang) Wu if (val == RADEON_VCN_ENGINE_TYPE_DECODE) {
1790f823323bSDavid (Ming Qiang) Wu decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6];
17910b15205cSSonny Jiang
1792c05d789fSChristian König if (!(decode_buffer->valid_buf_flag & 0x1))
1793c05d789fSChristian König return 0;
1794c05d789fSChristian König
1795c05d789fSChristian König addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 |
1796c05d789fSChristian König decode_buffer->msg_buffer_address_lo;
1797c05d789fSChristian König return vcn_v4_0_dec_msg(p, job, addr);
1798f823323bSDavid (Ming Qiang) Wu } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) {
1799f823323bSDavid (Ming Qiang) Wu idx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT,
1800f823323bSDavid (Ming Qiang) Wu RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET);
1801f823323bSDavid (Ming Qiang) Wu if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1)
1802f823323bSDavid (Ming Qiang) Wu return vcn_v4_0_limit_sched(p, job);
1803f823323bSDavid (Ming Qiang) Wu }
1804f823323bSDavid (Ming Qiang) Wu return 0;
18050b15205cSSonny Jiang }
18060b15205cSSonny Jiang
18075dbb5924Ssguttula static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
18088da1170aSLeo Liu .type = AMDGPU_RING_TYPE_VCN_ENC,
18098da1170aSLeo Liu .align_mask = 0x3f,
18108da1170aSLeo Liu .nop = VCN_ENC_CMD_NO_OP,
1811bb4f196bSRuijing Dong .get_rptr = vcn_v4_0_unified_ring_get_rptr,
1812bb4f196bSRuijing Dong .get_wptr = vcn_v4_0_unified_ring_get_wptr,
1813bb4f196bSRuijing Dong .set_wptr = vcn_v4_0_unified_ring_set_wptr,
18140b15205cSSonny Jiang .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place,
18158da1170aSLeo Liu .emit_frame_size =
18168da1170aSLeo Liu SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
18178da1170aSLeo Liu SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
18188da1170aSLeo Liu 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
18198da1170aSLeo Liu 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
18208da1170aSLeo Liu 1, /* vcn_v2_0_enc_ring_insert_end */
18218da1170aSLeo Liu .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
18228da1170aSLeo Liu .emit_ib = vcn_v2_0_enc_ring_emit_ib,
18238da1170aSLeo Liu .emit_fence = vcn_v2_0_enc_ring_emit_fence,
18248da1170aSLeo Liu .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
18258da1170aSLeo Liu .test_ring = amdgpu_vcn_enc_ring_test_ring,
1826bb4f196bSRuijing Dong .test_ib = amdgpu_vcn_unified_ring_test_ib,
18278da1170aSLeo Liu .insert_nop = amdgpu_ring_insert_nop,
18288da1170aSLeo Liu .insert_end = vcn_v2_0_enc_ring_insert_end,
18298da1170aSLeo Liu .pad_ib = amdgpu_ring_generic_pad_ib,
18308da1170aSLeo Liu .begin_use = amdgpu_vcn_ring_begin_use,
18318da1170aSLeo Liu .end_use = amdgpu_vcn_ring_end_use,
18328da1170aSLeo Liu .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
18338da1170aSLeo Liu .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
18348da1170aSLeo Liu .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
18358da1170aSLeo Liu };
18368da1170aSLeo Liu
18378da1170aSLeo Liu /**
1838bb4f196bSRuijing Dong * vcn_v4_0_set_unified_ring_funcs - set unified ring functions
18398da1170aSLeo Liu *
18408da1170aSLeo Liu * @adev: amdgpu_device pointer
18418da1170aSLeo Liu *
1842bb4f196bSRuijing Dong * Set unified ring functions
18438da1170aSLeo Liu */
vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device * adev)1844bb4f196bSRuijing Dong static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev)
18458da1170aSLeo Liu {
18468da1170aSLeo Liu int i;
18478da1170aSLeo Liu
18488da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
18498da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i))
18508da1170aSLeo Liu continue;
18518da1170aSLeo Liu
18525dbb5924Ssguttula if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 2))
18535dbb5924Ssguttula vcn_v4_0_unified_ring_vm_funcs.secure_submission_supported = true;
18545dbb5924Ssguttula
18555dbb5924Ssguttula adev->vcn.inst[i].ring_enc[0].funcs =
18565dbb5924Ssguttula (const struct amdgpu_ring_funcs *)&vcn_v4_0_unified_ring_vm_funcs;
1857bb4f196bSRuijing Dong adev->vcn.inst[i].ring_enc[0].me = i;
18588da1170aSLeo Liu
1859bb4f196bSRuijing Dong DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i);
18608da1170aSLeo Liu }
18618da1170aSLeo Liu }
18628da1170aSLeo Liu
18638da1170aSLeo Liu /**
18648da1170aSLeo Liu * vcn_v4_0_is_idle - check VCN block is idle
18658da1170aSLeo Liu *
18668da1170aSLeo Liu * @handle: amdgpu_device pointer
18678da1170aSLeo Liu *
18688da1170aSLeo Liu * Check whether VCN block is idle
18698da1170aSLeo Liu */
vcn_v4_0_is_idle(void * handle)18708da1170aSLeo Liu static bool vcn_v4_0_is_idle(void *handle)
18718da1170aSLeo Liu {
18728da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
18738da1170aSLeo Liu int i, ret = 1;
18748da1170aSLeo Liu
18758da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
18768da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i))
18778da1170aSLeo Liu continue;
18788da1170aSLeo Liu
18798da1170aSLeo Liu ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
18808da1170aSLeo Liu }
18818da1170aSLeo Liu
18828da1170aSLeo Liu return ret;
18838da1170aSLeo Liu }
18848da1170aSLeo Liu
18858da1170aSLeo Liu /**
18868da1170aSLeo Liu * vcn_v4_0_wait_for_idle - wait for VCN block idle
18878da1170aSLeo Liu *
18888da1170aSLeo Liu * @handle: amdgpu_device pointer
18898da1170aSLeo Liu *
18908da1170aSLeo Liu * Wait for VCN block idle
18918da1170aSLeo Liu */
vcn_v4_0_wait_for_idle(void * handle)18928da1170aSLeo Liu static int vcn_v4_0_wait_for_idle(void *handle)
18938da1170aSLeo Liu {
18948da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
18958da1170aSLeo Liu int i, ret = 0;
18968da1170aSLeo Liu
18978da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
18988da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i))
18998da1170aSLeo Liu continue;
19008da1170aSLeo Liu
19018da1170aSLeo Liu ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,
19028da1170aSLeo Liu UVD_STATUS__IDLE);
19038da1170aSLeo Liu if (ret)
19048da1170aSLeo Liu return ret;
19058da1170aSLeo Liu }
19068da1170aSLeo Liu
19078da1170aSLeo Liu return ret;
19088da1170aSLeo Liu }
19098da1170aSLeo Liu
19108da1170aSLeo Liu /**
19118da1170aSLeo Liu * vcn_v4_0_set_clockgating_state - set VCN block clockgating state
19128da1170aSLeo Liu *
19138da1170aSLeo Liu * @handle: amdgpu_device pointer
19148da1170aSLeo Liu * @state: clock gating state
19158da1170aSLeo Liu *
19168da1170aSLeo Liu * Set VCN block clockgating state
19178da1170aSLeo Liu */
vcn_v4_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)19188da1170aSLeo Liu static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state)
19198da1170aSLeo Liu {
19208da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
19213b780089SRuan Jinjie bool enable = state == AMD_CG_STATE_GATE;
19228da1170aSLeo Liu int i;
19238da1170aSLeo Liu
19248da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
19258da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i))
19268da1170aSLeo Liu continue;
19278da1170aSLeo Liu
19288da1170aSLeo Liu if (enable) {
19298da1170aSLeo Liu if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
19308da1170aSLeo Liu return -EBUSY;
19318da1170aSLeo Liu vcn_v4_0_enable_clock_gating(adev, i);
19328da1170aSLeo Liu } else {
19338da1170aSLeo Liu vcn_v4_0_disable_clock_gating(adev, i);
19348da1170aSLeo Liu }
19358da1170aSLeo Liu }
19368da1170aSLeo Liu
19378da1170aSLeo Liu return 0;
19388da1170aSLeo Liu }
19398da1170aSLeo Liu
19408da1170aSLeo Liu /**
19418da1170aSLeo Liu * vcn_v4_0_set_powergating_state - set VCN block powergating state
19428da1170aSLeo Liu *
19438da1170aSLeo Liu * @handle: amdgpu_device pointer
19448da1170aSLeo Liu * @state: power gating state
19458da1170aSLeo Liu *
19468da1170aSLeo Liu * Set VCN block powergating state
19478da1170aSLeo Liu */
vcn_v4_0_set_powergating_state(void * handle,enum amd_powergating_state state)19488da1170aSLeo Liu static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state)
19498da1170aSLeo Liu {
19508da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
19518da1170aSLeo Liu int ret;
19528da1170aSLeo Liu
1953aa44beb5SJane Jian /* for SRIOV, guest should not control VCN Power-gating
1954aa44beb5SJane Jian * MMSCH FW should control Power-gating and clock-gating
1955aa44beb5SJane Jian * guest should avoid touching CGC and PG
1956aa44beb5SJane Jian */
1957aa44beb5SJane Jian if (amdgpu_sriov_vf(adev)) {
1958aa44beb5SJane Jian adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
1959aa44beb5SJane Jian return 0;
1960aa44beb5SJane Jian }
1961aa44beb5SJane Jian
19628da1170aSLeo Liu if (state == adev->vcn.cur_state)
19638da1170aSLeo Liu return 0;
19648da1170aSLeo Liu
19658da1170aSLeo Liu if (state == AMD_PG_STATE_GATE)
19668da1170aSLeo Liu ret = vcn_v4_0_stop(adev);
19678da1170aSLeo Liu else
19688da1170aSLeo Liu ret = vcn_v4_0_start(adev);
19698da1170aSLeo Liu
19708da1170aSLeo Liu if (!ret)
19718da1170aSLeo Liu adev->vcn.cur_state = state;
19728da1170aSLeo Liu
19738da1170aSLeo Liu return ret;
19748da1170aSLeo Liu }
19758da1170aSLeo Liu
19768da1170aSLeo Liu /**
19778da1170aSLeo Liu * vcn_v4_0_set_interrupt_state - set VCN block interrupt state
19788da1170aSLeo Liu *
19798da1170aSLeo Liu * @adev: amdgpu_device pointer
19808da1170aSLeo Liu * @source: interrupt sources
19818da1170aSLeo Liu * @type: interrupt types
19828da1170aSLeo Liu * @state: interrupt states
19838da1170aSLeo Liu *
19848da1170aSLeo Liu * Set VCN block interrupt state
19858da1170aSLeo Liu */
vcn_v4_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)19868da1170aSLeo Liu static int vcn_v4_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
19878da1170aSLeo Liu unsigned type, enum amdgpu_interrupt_state state)
19888da1170aSLeo Liu {
19898da1170aSLeo Liu return 0;
19908da1170aSLeo Liu }
19918da1170aSLeo Liu
19928da1170aSLeo Liu /**
199366a11ecbSHoratio Zhang * vcn_v4_0_set_ras_interrupt_state - set VCN block RAS interrupt state
199466a11ecbSHoratio Zhang *
199566a11ecbSHoratio Zhang * @adev: amdgpu_device pointer
199666a11ecbSHoratio Zhang * @source: interrupt sources
199766a11ecbSHoratio Zhang * @type: interrupt types
199866a11ecbSHoratio Zhang * @state: interrupt states
199966a11ecbSHoratio Zhang *
200066a11ecbSHoratio Zhang * Set VCN block RAS interrupt state
200166a11ecbSHoratio Zhang */
vcn_v4_0_set_ras_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)200266a11ecbSHoratio Zhang static int vcn_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev,
200366a11ecbSHoratio Zhang struct amdgpu_irq_src *source,
200466a11ecbSHoratio Zhang unsigned int type,
200566a11ecbSHoratio Zhang enum amdgpu_interrupt_state state)
200666a11ecbSHoratio Zhang {
200766a11ecbSHoratio Zhang return 0;
200866a11ecbSHoratio Zhang }
200966a11ecbSHoratio Zhang
201066a11ecbSHoratio Zhang /**
20118da1170aSLeo Liu * vcn_v4_0_process_interrupt - process VCN block interrupt
20128da1170aSLeo Liu *
20138da1170aSLeo Liu * @adev: amdgpu_device pointer
20148da1170aSLeo Liu * @source: interrupt sources
20158da1170aSLeo Liu * @entry: interrupt entry from clients and sources
20168da1170aSLeo Liu *
20178da1170aSLeo Liu * Process VCN block interrupt
20188da1170aSLeo Liu */
vcn_v4_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)20198da1170aSLeo Liu static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
20208da1170aSLeo Liu struct amdgpu_iv_entry *entry)
20218da1170aSLeo Liu {
20228da1170aSLeo Liu uint32_t ip_instance;
20238da1170aSLeo Liu
20248da1170aSLeo Liu switch (entry->client_id) {
20258da1170aSLeo Liu case SOC15_IH_CLIENTID_VCN:
20268da1170aSLeo Liu ip_instance = 0;
20278da1170aSLeo Liu break;
20288da1170aSLeo Liu case SOC15_IH_CLIENTID_VCN1:
20298da1170aSLeo Liu ip_instance = 1;
20308da1170aSLeo Liu break;
20318da1170aSLeo Liu default:
20328da1170aSLeo Liu DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
20338da1170aSLeo Liu return 0;
20348da1170aSLeo Liu }
20358da1170aSLeo Liu
20368da1170aSLeo Liu DRM_DEBUG("IH: VCN TRAP\n");
20378da1170aSLeo Liu
20388da1170aSLeo Liu switch (entry->src_id) {
20398da1170aSLeo Liu case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
20408da1170aSLeo Liu amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
20418da1170aSLeo Liu break;
20428da1170aSLeo Liu default:
20438da1170aSLeo Liu DRM_ERROR("Unhandled interrupt: %d %d\n",
20448da1170aSLeo Liu entry->src_id, entry->src_data[0]);
20458da1170aSLeo Liu break;
20468da1170aSLeo Liu }
20478da1170aSLeo Liu
20488da1170aSLeo Liu return 0;
20498da1170aSLeo Liu }
20508da1170aSLeo Liu
20518da1170aSLeo Liu static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = {
20528da1170aSLeo Liu .set = vcn_v4_0_set_interrupt_state,
20538da1170aSLeo Liu .process = vcn_v4_0_process_interrupt,
20548da1170aSLeo Liu };
20558da1170aSLeo Liu
205666a11ecbSHoratio Zhang static const struct amdgpu_irq_src_funcs vcn_v4_0_ras_irq_funcs = {
205766a11ecbSHoratio Zhang .set = vcn_v4_0_set_ras_interrupt_state,
205866a11ecbSHoratio Zhang .process = amdgpu_vcn_process_poison_irq,
205966a11ecbSHoratio Zhang };
206066a11ecbSHoratio Zhang
20618da1170aSLeo Liu /**
20628da1170aSLeo Liu * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions
20638da1170aSLeo Liu *
20648da1170aSLeo Liu * @adev: amdgpu_device pointer
20658da1170aSLeo Liu *
20668da1170aSLeo Liu * Set VCN block interrupt irq functions
20678da1170aSLeo Liu */
vcn_v4_0_set_irq_funcs(struct amdgpu_device * adev)20688da1170aSLeo Liu static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev)
20698da1170aSLeo Liu {
20708da1170aSLeo Liu int i;
20718da1170aSLeo Liu
20728da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
20738da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i))
20748da1170aSLeo Liu continue;
20758da1170aSLeo Liu
20768da1170aSLeo Liu adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
20778da1170aSLeo Liu adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs;
207866a11ecbSHoratio Zhang
207966a11ecbSHoratio Zhang adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1;
208066a11ecbSHoratio Zhang adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs;
20818da1170aSLeo Liu }
20828da1170aSLeo Liu }
20838da1170aSLeo Liu
20848da1170aSLeo Liu static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
20858da1170aSLeo Liu .name = "vcn_v4_0",
20868da1170aSLeo Liu .early_init = vcn_v4_0_early_init,
20878da1170aSLeo Liu .late_init = NULL,
20888da1170aSLeo Liu .sw_init = vcn_v4_0_sw_init,
20898da1170aSLeo Liu .sw_fini = vcn_v4_0_sw_fini,
20908da1170aSLeo Liu .hw_init = vcn_v4_0_hw_init,
20918da1170aSLeo Liu .hw_fini = vcn_v4_0_hw_fini,
20928da1170aSLeo Liu .suspend = vcn_v4_0_suspend,
20938da1170aSLeo Liu .resume = vcn_v4_0_resume,
20948da1170aSLeo Liu .is_idle = vcn_v4_0_is_idle,
20958da1170aSLeo Liu .wait_for_idle = vcn_v4_0_wait_for_idle,
20968da1170aSLeo Liu .check_soft_reset = NULL,
20978da1170aSLeo Liu .pre_soft_reset = NULL,
20988da1170aSLeo Liu .soft_reset = NULL,
20998da1170aSLeo Liu .post_soft_reset = NULL,
21008da1170aSLeo Liu .set_clockgating_state = vcn_v4_0_set_clockgating_state,
21018da1170aSLeo Liu .set_powergating_state = vcn_v4_0_set_powergating_state,
21028da1170aSLeo Liu };
21038da1170aSLeo Liu
2104*2b2b5858SRan Sun const struct amdgpu_ip_block_version vcn_v4_0_ip_block = {
21058da1170aSLeo Liu .type = AMD_IP_BLOCK_TYPE_VCN,
21068da1170aSLeo Liu .major = 4,
21078da1170aSLeo Liu .minor = 0,
21088da1170aSLeo Liu .rev = 0,
21098da1170aSLeo Liu .funcs = &vcn_v4_0_ip_funcs,
21108da1170aSLeo Liu };
2111377d0221STao Zhou
vcn_v4_0_query_poison_by_instance(struct amdgpu_device * adev,uint32_t instance,uint32_t sub_block)2112377d0221STao Zhou static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev,
2113377d0221STao Zhou uint32_t instance, uint32_t sub_block)
2114377d0221STao Zhou {
2115377d0221STao Zhou uint32_t poison_stat = 0, reg_value = 0;
2116377d0221STao Zhou
2117377d0221STao Zhou switch (sub_block) {
2118377d0221STao Zhou case AMDGPU_VCN_V4_0_VCPU_VCODEC:
2119377d0221STao Zhou reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);
2120377d0221STao Zhou poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
2121377d0221STao Zhou break;
2122377d0221STao Zhou default:
2123377d0221STao Zhou break;
2124377d0221STao Zhou }
2125377d0221STao Zhou
2126377d0221STao Zhou if (poison_stat)
2127377d0221STao Zhou dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n",
2128377d0221STao Zhou instance, sub_block);
2129377d0221STao Zhou
2130377d0221STao Zhou return poison_stat;
2131377d0221STao Zhou }
2132377d0221STao Zhou
vcn_v4_0_query_ras_poison_status(struct amdgpu_device * adev)2133377d0221STao Zhou static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev)
2134377d0221STao Zhou {
2135377d0221STao Zhou uint32_t inst, sub;
2136377d0221STao Zhou uint32_t poison_stat = 0;
2137377d0221STao Zhou
2138377d0221STao Zhou for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
2139377d0221STao Zhou for (sub = 0; sub < AMDGPU_VCN_V4_0_MAX_SUB_BLOCK; sub++)
2140377d0221STao Zhou poison_stat +=
2141377d0221STao Zhou vcn_v4_0_query_poison_by_instance(adev, inst, sub);
2142377d0221STao Zhou
2143377d0221STao Zhou return !!poison_stat;
2144377d0221STao Zhou }
2145377d0221STao Zhou
2146377d0221STao Zhou const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = {
2147377d0221STao Zhou .query_poison_status = vcn_v4_0_query_ras_poison_status,
2148377d0221STao Zhou };
2149377d0221STao Zhou
2150377d0221STao Zhou static struct amdgpu_vcn_ras vcn_v4_0_ras = {
2151377d0221STao Zhou .ras_block = {
2152377d0221STao Zhou .hw_ops = &vcn_v4_0_ras_hw_ops,
215366a11ecbSHoratio Zhang .ras_late_init = amdgpu_vcn_ras_late_init,
2154377d0221STao Zhou },
2155377d0221STao Zhou };
2156377d0221STao Zhou
vcn_v4_0_set_ras_funcs(struct amdgpu_device * adev)2157377d0221STao Zhou static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2158377d0221STao Zhou {
2159377d0221STao Zhou switch (adev->ip_versions[VCN_HWIP][0]) {
2160377d0221STao Zhou case IP_VERSION(4, 0, 0):
2161377d0221STao Zhou adev->vcn.ras = &vcn_v4_0_ras;
2162377d0221STao Zhou break;
2163377d0221STao Zhou default:
2164377d0221STao Zhou break;
2165377d0221STao Zhou }
2166377d0221STao Zhou }
2167