18630f839SAlex Deucher /* 28630f839SAlex Deucher * UVD_4_2 Register documentation 38630f839SAlex Deucher * 48630f839SAlex Deucher * Copyright (C) 2014 Advanced Micro Devices, Inc. 58630f839SAlex Deucher * 68630f839SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 78630f839SAlex Deucher * copy of this software and associated documentation files (the "Software"), 88630f839SAlex Deucher * to deal in the Software without restriction, including without limitation 98630f839SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 108630f839SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 118630f839SAlex Deucher * Software is furnished to do so, subject to the following conditions: 128630f839SAlex Deucher * 138630f839SAlex Deucher * The above copyright notice and this permission notice shall be included 148630f839SAlex Deucher * in all copies or substantial portions of the Software. 158630f839SAlex Deucher * 168630f839SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 178630f839SAlex Deucher * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 188630f839SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 198630f839SAlex Deucher * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 208630f839SAlex Deucher * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 218630f839SAlex Deucher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 228630f839SAlex Deucher */ 238630f839SAlex Deucher 248630f839SAlex Deucher #ifndef UVD_4_2_SH_MASK_H 258630f839SAlex Deucher #define UVD_4_2_SH_MASK_H 268630f839SAlex Deucher 278630f839SAlex Deucher #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 288630f839SAlex Deucher #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 298630f839SAlex Deucher #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 308630f839SAlex Deucher #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 318630f839SAlex Deucher #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 328630f839SAlex Deucher #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 338630f839SAlex Deucher #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 348630f839SAlex Deucher #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 358630f839SAlex Deucher #define UVD_SEMA_CMD__MODE_MASK 0x40 368630f839SAlex Deucher #define UVD_SEMA_CMD__MODE__SHIFT 0x6 378630f839SAlex Deucher #define UVD_SEMA_CMD__VMID_EN_MASK 0x80 388630f839SAlex Deucher #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 398630f839SAlex Deucher #define UVD_SEMA_CMD__VMID_MASK 0xf00 408630f839SAlex Deucher #define UVD_SEMA_CMD__VMID__SHIFT 0x8 418630f839SAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 428630f839SAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 438630f839SAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe 448630f839SAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 458630f839SAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000 468630f839SAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 478630f839SAlex Deucher #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff 488630f839SAlex Deucher #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 498630f839SAlex Deucher #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff 508630f839SAlex Deucher #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 518630f839SAlex Deucher #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 528630f839SAlex Deucher #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 538630f839SAlex Deucher #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 548630f839SAlex Deucher #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 558630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7 568630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 578630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 588630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 598630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 608630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 618630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 628630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 638630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 648630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 658630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 668630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 678630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 688630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 698630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 708630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 718630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 728630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 738630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 748630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 758630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 768630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 778630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 788630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 798630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 808630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 818630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 828630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 838630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 848630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 858630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 868630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 878630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 888630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 898630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 908630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 918630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 928630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 938630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 948630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 958630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 968630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 978630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 988630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 998630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 1008630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 1018630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 1028630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 1038630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 1048630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 1058630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 1068630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 1078630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 1088630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 1098630f839SAlex Deucher #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 1108630f839SAlex Deucher #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 1118630f839SAlex Deucher #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2 1128630f839SAlex Deucher #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 1138630f839SAlex Deucher #define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff 1148630f839SAlex Deucher #define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0 1158630f839SAlex Deucher #define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000 1168630f839SAlex Deucher #define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10 1178630f839SAlex Deucher #define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000 1188630f839SAlex Deucher #define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f 1198630f839SAlex Deucher #define UVD_CTX_INDEX__INDEX_MASK 0x1ff 1208630f839SAlex Deucher #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 1218630f839SAlex Deucher #define UVD_CTX_DATA__DATA_MASK 0xffffffff 1228630f839SAlex Deucher #define UVD_CTX_DATA__DATA__SHIFT 0x0 1238630f839SAlex Deucher #define UVD_CGC_GATE__SYS_MASK 0x1 1248630f839SAlex Deucher #define UVD_CGC_GATE__SYS__SHIFT 0x0 1258630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_MASK 0x2 1268630f839SAlex Deucher #define UVD_CGC_GATE__UDEC__SHIFT 0x1 1278630f839SAlex Deucher #define UVD_CGC_GATE__MPEG2_MASK 0x4 1288630f839SAlex Deucher #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 1298630f839SAlex Deucher #define UVD_CGC_GATE__REGS_MASK 0x8 1308630f839SAlex Deucher #define UVD_CGC_GATE__REGS__SHIFT 0x3 1318630f839SAlex Deucher #define UVD_CGC_GATE__RBC_MASK 0x10 1328630f839SAlex Deucher #define UVD_CGC_GATE__RBC__SHIFT 0x4 1338630f839SAlex Deucher #define UVD_CGC_GATE__LMI_MC_MASK 0x20 1348630f839SAlex Deucher #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 1358630f839SAlex Deucher #define UVD_CGC_GATE__LMI_UMC_MASK 0x40 1368630f839SAlex Deucher #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 1378630f839SAlex Deucher #define UVD_CGC_GATE__IDCT_MASK 0x80 1388630f839SAlex Deucher #define UVD_CGC_GATE__IDCT__SHIFT 0x7 1398630f839SAlex Deucher #define UVD_CGC_GATE__MPRD_MASK 0x100 1408630f839SAlex Deucher #define UVD_CGC_GATE__MPRD__SHIFT 0x8 1418630f839SAlex Deucher #define UVD_CGC_GATE__MPC_MASK 0x200 1428630f839SAlex Deucher #define UVD_CGC_GATE__MPC__SHIFT 0x9 1438630f839SAlex Deucher #define UVD_CGC_GATE__LBSI_MASK 0x400 1448630f839SAlex Deucher #define UVD_CGC_GATE__LBSI__SHIFT 0xa 1458630f839SAlex Deucher #define UVD_CGC_GATE__LRBBM_MASK 0x800 1468630f839SAlex Deucher #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 1478630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 1488630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 1498630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_CM_MASK 0x2000 1508630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 1518630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 1528630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 1538630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_DB_MASK 0x8000 1548630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 1558630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 1568630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 1578630f839SAlex Deucher #define UVD_CGC_GATE__WCB_MASK 0x20000 1588630f839SAlex Deucher #define UVD_CGC_GATE__WCB__SHIFT 0x11 1598630f839SAlex Deucher #define UVD_CGC_GATE__VCPU_MASK 0x40000 1608630f839SAlex Deucher #define UVD_CGC_GATE__VCPU__SHIFT 0x12 1618630f839SAlex Deucher #define UVD_CGC_GATE__SCPU_MASK 0x80000 1628630f839SAlex Deucher #define UVD_CGC_GATE__SCPU__SHIFT 0x13 1638630f839SAlex Deucher #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 1648630f839SAlex Deucher #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 1658630f839SAlex Deucher #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2 1668630f839SAlex Deucher #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 1678630f839SAlex Deucher #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4 1688630f839SAlex Deucher #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 1698630f839SAlex Deucher #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8 1708630f839SAlex Deucher #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 1718630f839SAlex Deucher #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10 1728630f839SAlex Deucher #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 1738630f839SAlex Deucher #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20 1748630f839SAlex Deucher #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 1758630f839SAlex Deucher #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40 1768630f839SAlex Deucher #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 1778630f839SAlex Deucher #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80 1788630f839SAlex Deucher #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 1798630f839SAlex Deucher #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100 1808630f839SAlex Deucher #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 1818630f839SAlex Deucher #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200 1828630f839SAlex Deucher #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 1838630f839SAlex Deucher #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400 1848630f839SAlex Deucher #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 1858630f839SAlex Deucher #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800 1868630f839SAlex Deucher #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 1878630f839SAlex Deucher #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000 1888630f839SAlex Deucher #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 1898630f839SAlex Deucher #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000 1908630f839SAlex Deucher #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 1918630f839SAlex Deucher #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000 1928630f839SAlex Deucher #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 1938630f839SAlex Deucher #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000 1948630f839SAlex Deucher #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 1958630f839SAlex Deucher #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000 1968630f839SAlex Deucher #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 1978630f839SAlex Deucher #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000 1988630f839SAlex Deucher #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 1998630f839SAlex Deucher #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000 2008630f839SAlex Deucher #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 2018630f839SAlex Deucher #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 2028630f839SAlex Deucher #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 2038630f839SAlex Deucher #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000 2048630f839SAlex Deucher #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 2058630f839SAlex Deucher #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000 2068630f839SAlex Deucher #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 2078630f839SAlex Deucher #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000 2088630f839SAlex Deucher #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 2098630f839SAlex Deucher #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000 2108630f839SAlex Deucher #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 2118630f839SAlex Deucher #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000 2128630f839SAlex Deucher #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 2138630f839SAlex Deucher #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000 2148630f839SAlex Deucher #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 2158630f839SAlex Deucher #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000 2168630f839SAlex Deucher #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 2178630f839SAlex Deucher #define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000 2188630f839SAlex Deucher #define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b 2198630f839SAlex Deucher #define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000 2208630f839SAlex Deucher #define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c 2218630f839SAlex Deucher #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 2228630f839SAlex Deucher #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 2238630f839SAlex Deucher #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c 2248630f839SAlex Deucher #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 2258630f839SAlex Deucher #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 2268630f839SAlex Deucher #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 2278630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 2288630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 2298630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000 2308630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 2318630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 2328630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 2338630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000 2348630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 2358630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000 2368630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 2378630f839SAlex Deucher #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 2388630f839SAlex Deucher #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 2398630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000 2408630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 2418630f839SAlex Deucher #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000 2428630f839SAlex Deucher #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 2438630f839SAlex Deucher #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 2448630f839SAlex Deucher #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 2458630f839SAlex Deucher #define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 2468630f839SAlex Deucher #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 2478630f839SAlex Deucher #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000 2488630f839SAlex Deucher #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 2498630f839SAlex Deucher #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000 2508630f839SAlex Deucher #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 2518630f839SAlex Deucher #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000 2528630f839SAlex Deucher #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 2538630f839SAlex Deucher #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 2548630f839SAlex Deucher #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 2558630f839SAlex Deucher #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 2568630f839SAlex Deucher #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 2578630f839SAlex Deucher #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000 2588630f839SAlex Deucher #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 2598630f839SAlex Deucher #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000 2608630f839SAlex Deucher #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 2618630f839SAlex Deucher #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 2628630f839SAlex Deucher #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 2638630f839SAlex Deucher #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 2648630f839SAlex Deucher #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 2658630f839SAlex Deucher #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 2668630f839SAlex Deucher #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e 2678630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1 2688630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 2698630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2 2708630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 2718630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4 2728630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 2738630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 2748630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 2758630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 2768630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 2778630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 2788630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 2798630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40 2808630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 2818630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 2828630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 2838630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100 2848630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 2858630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200 2868630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 2878630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400 2888630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 2898630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800 2908630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 2918630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000 2928630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 2938630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000 2948630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 2958630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000 2968630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 2978630f839SAlex Deucher #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1 2988630f839SAlex Deucher #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 2998630f839SAlex Deucher #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2 3008630f839SAlex Deucher #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 3018630f839SAlex Deucher #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4 3028630f839SAlex Deucher #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 3038630f839SAlex Deucher #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8 3048630f839SAlex Deucher #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 3058630f839SAlex Deucher #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70 3068630f839SAlex Deucher #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4 3078630f839SAlex Deucher #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80 3088630f839SAlex Deucher #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 3098630f839SAlex Deucher #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 3108630f839SAlex Deucher #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 3118630f839SAlex Deucher #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600 3128630f839SAlex Deucher #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 3138630f839SAlex Deucher #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800 3148630f839SAlex Deucher #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 3158630f839SAlex Deucher #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000 3168630f839SAlex Deucher #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 3178630f839SAlex Deucher #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000 3188630f839SAlex Deucher #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 3198630f839SAlex Deucher #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000 3208630f839SAlex Deucher #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 3218630f839SAlex Deucher #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000 3228630f839SAlex Deucher #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 3238630f839SAlex Deucher #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000 3248630f839SAlex Deucher #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 3258630f839SAlex Deucher #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1 3268630f839SAlex Deucher #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 3278630f839SAlex Deucher #define UVD_MASTINT_EN__VCPU_EN_MASK 0x2 3288630f839SAlex Deucher #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 3298630f839SAlex Deucher #define UVD_MASTINT_EN__SYS_EN_MASK 0x4 3308630f839SAlex Deucher #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 3318630f839SAlex Deucher #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0 3328630f839SAlex Deucher #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 3338630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf 3348630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0 3358630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0 3368630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4 3378630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00 3388630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8 3398630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000 3408630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc 3418630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000 3428630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10 3438630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000 3448630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14 3458630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000 3468630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18 3478630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000 3488630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c 3498630f839SAlex Deucher #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff 3508630f839SAlex Deucher #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 3518630f839SAlex Deucher #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 3528630f839SAlex Deucher #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 3538630f839SAlex Deucher #define UVD_LMI_CTRL__REQ_MODE_MASK 0x200 3548630f839SAlex Deucher #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 3558630f839SAlex Deucher #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800 3568630f839SAlex Deucher #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 3578630f839SAlex Deucher #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000 3588630f839SAlex Deucher #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 3598630f839SAlex Deucher #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000 3608630f839SAlex Deucher #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 3618630f839SAlex Deucher #define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000 3628630f839SAlex Deucher #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 3638630f839SAlex Deucher #define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000 3648630f839SAlex Deucher #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 3658630f839SAlex Deucher #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000 3668630f839SAlex Deucher #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 3678630f839SAlex Deucher #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 3688630f839SAlex Deucher #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 3698630f839SAlex Deucher #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000 3708630f839SAlex Deucher #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 3718630f839SAlex Deucher #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000 3728630f839SAlex Deucher #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 3738630f839SAlex Deucher #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000 3748630f839SAlex Deucher #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 3758630f839SAlex Deucher #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000 3768630f839SAlex Deucher #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 3778630f839SAlex Deucher #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000 3788630f839SAlex Deucher #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 3798630f839SAlex Deucher #define UVD_LMI_CTRL__RFU_MASK 0xf8000000 3808630f839SAlex Deucher #define UVD_LMI_CTRL__RFU__SHIFT 0x1b 3818630f839SAlex Deucher #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1 3828630f839SAlex Deucher #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 3838630f839SAlex Deucher #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2 3848630f839SAlex Deucher #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 3858630f839SAlex Deucher #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 3868630f839SAlex Deucher #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 3878630f839SAlex Deucher #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8 3888630f839SAlex Deucher #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 3898630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10 3908630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 3918630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20 3928630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 3938630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40 3948630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 3958630f839SAlex Deucher #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80 3968630f839SAlex Deucher #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 3978630f839SAlex Deucher #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100 3988630f839SAlex Deucher #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 3998630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200 4008630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 4018630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400 4028630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 4038630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800 4048630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 4058630f839SAlex Deucher #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000 4068630f839SAlex Deucher #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 4078630f839SAlex Deucher #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000 4088630f839SAlex Deucher #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 4098630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3 4108630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 4118630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc 4128630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 4138630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30 4148630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 4158630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0 4168630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 4178630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300 4188630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 4198630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00 4208630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 4218630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000 4228630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 4238630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000 4248630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 4258630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000 4268630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 4278630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000 4288630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 4298630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000 4308630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 4318630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000 4328630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 4338630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000 4348630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 4358630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000 4368630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 4378630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000 4388630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 4398630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3 4408630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 4418630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc 4428630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 4438630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30 4448630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 4458630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0 4468630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 4478630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300 4488630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 4498630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00 4508630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 4518630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000 4528630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 4538630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000 4548630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 4558630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000 4568630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 4578630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000 4588630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 4598630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000 4608630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 4618630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000 4628630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 4638630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000 4648630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 4658630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000 4668630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 4678630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000 4688630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 4698630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000 4708630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 4718630f839SAlex Deucher #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 4728630f839SAlex Deucher #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 4738630f839SAlex Deucher #define UVD_MPC_CNTL__PERF_RST_MASK 0x40 4748630f839SAlex Deucher #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 4758630f839SAlex Deucher #define UVD_MPC_CNTL__DBG_MUX_MASK 0x700 4768630f839SAlex Deucher #define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8 4778630f839SAlex Deucher #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000 4788630f839SAlex Deucher #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 4798630f839SAlex Deucher #define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000 4808630f839SAlex Deucher #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 4818630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f 4828630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 4838630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0 4848630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 4858630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 4868630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 4878630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 4888630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 4898630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 4908630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 4918630f839SAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f 4928630f839SAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 4938630f839SAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 4948630f839SAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 4958630f839SAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 4968630f839SAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 4978630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f 4988630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 4998630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 5008630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 5018630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000 5028630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 5038630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000 5048630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 5058630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000 5068630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 5078630f839SAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f 5088630f839SAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 5098630f839SAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0 5108630f839SAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 5118630f839SAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 5128630f839SAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 5138630f839SAlex Deucher #define UVD_MPC_SET_MUX__SET_0_MASK 0x7 5148630f839SAlex Deucher #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 5158630f839SAlex Deucher #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 5168630f839SAlex Deucher #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 5178630f839SAlex Deucher #define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 5188630f839SAlex Deucher #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 5198630f839SAlex Deucher #define UVD_MPC_SET_ALU__FUNCT_MASK 0x7 5208630f839SAlex Deucher #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 5218630f839SAlex Deucher #define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0 5228630f839SAlex Deucher #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 5238630f839SAlex Deucher #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff 5248630f839SAlex Deucher #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 5258630f839SAlex Deucher #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff 5268630f839SAlex Deucher #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 5278630f839SAlex Deucher #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff 5288630f839SAlex Deucher #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 5298630f839SAlex Deucher #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff 5308630f839SAlex Deucher #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 5318630f839SAlex Deucher #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff 5328630f839SAlex Deucher #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 5338630f839SAlex Deucher #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff 5348630f839SAlex Deucher #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 5358630f839SAlex Deucher #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf 5368630f839SAlex Deucher #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 5378630f839SAlex Deucher #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10 5388630f839SAlex Deucher #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 5398630f839SAlex Deucher #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20 5408630f839SAlex Deucher #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 5418630f839SAlex Deucher #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40 5428630f839SAlex Deucher #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 5438630f839SAlex Deucher #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80 5448630f839SAlex Deucher #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 5458630f839SAlex Deucher #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100 5468630f839SAlex Deucher #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 5478630f839SAlex Deucher #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 5488630f839SAlex Deucher #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 5498630f839SAlex Deucher #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400 5508630f839SAlex Deucher #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 5518630f839SAlex Deucher #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 5528630f839SAlex Deucher #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 5538630f839SAlex Deucher #define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000 5548630f839SAlex Deucher #define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd 5558630f839SAlex Deucher #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000 5568630f839SAlex Deucher #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 5578630f839SAlex Deucher #define UVD_VCPU_CNTL__CLK_ACTIVE_MASK 0x20000 5588630f839SAlex Deucher #define UVD_VCPU_CNTL__CLK_ACTIVE__SHIFT 0x11 5598630f839SAlex Deucher #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000 5608630f839SAlex Deucher #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 5618630f839SAlex Deucher #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000 5628630f839SAlex Deucher #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 5638630f839SAlex Deucher #define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000 5648630f839SAlex Deucher #define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c 5658630f839SAlex Deucher #define UVD_VCPU_CNTL__ECPU_AM32_EN_MASK 0x20000000 5668630f839SAlex Deucher #define UVD_VCPU_CNTL__ECPU_AM32_EN__SHIFT 0x1d 5678630f839SAlex Deucher #define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000 5688630f839SAlex Deucher #define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e 5698630f839SAlex Deucher #define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000 5708630f839SAlex Deucher #define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f 5718630f839SAlex Deucher #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1 5728630f839SAlex Deucher #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 5738630f839SAlex Deucher #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2 5748630f839SAlex Deucher #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 5758630f839SAlex Deucher #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4 5768630f839SAlex Deucher #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 5778630f839SAlex Deucher #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8 5788630f839SAlex Deucher #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 5798630f839SAlex Deucher #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10 5808630f839SAlex Deucher #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 5818630f839SAlex Deucher #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20 5828630f839SAlex Deucher #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 5838630f839SAlex Deucher #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40 5848630f839SAlex Deucher #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 5858630f839SAlex Deucher #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80 5868630f839SAlex Deucher #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 5878630f839SAlex Deucher #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100 5888630f839SAlex Deucher #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 5898630f839SAlex Deucher #define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK 0x200 5908630f839SAlex Deucher #define UVD_SOFT_RESET__FWV_SOFT_RESET__SHIFT 0x9 5918630f839SAlex Deucher #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400 5928630f839SAlex Deucher #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 5938630f839SAlex Deucher #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800 5948630f839SAlex Deucher #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 5958630f839SAlex Deucher #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000 5968630f839SAlex Deucher #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 5978630f839SAlex Deucher #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000 5988630f839SAlex Deucher #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 5998630f839SAlex Deucher #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000 6008630f839SAlex Deucher #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 6018630f839SAlex Deucher #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000 6028630f839SAlex Deucher #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 6038630f839SAlex Deucher #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000 6048630f839SAlex Deucher #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 6058630f839SAlex Deucher #define UVD_RBC_IB_BASE__IB_BASE_MASK 0xffffffc0 6068630f839SAlex Deucher #define UVD_RBC_IB_BASE__IB_BASE__SHIFT 0x6 6078630f839SAlex Deucher #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0 6088630f839SAlex Deucher #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 6098630f839SAlex Deucher #define UVD_RBC_RB_BASE__RB_BASE_MASK 0xffffffc0 6108630f839SAlex Deucher #define UVD_RBC_RB_BASE__RB_BASE__SHIFT 0x6 6118630f839SAlex Deucher #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0 6128630f839SAlex Deucher #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 6138630f839SAlex Deucher #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0 6148630f839SAlex Deucher #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 6158630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f 6168630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 6178630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00 6188630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 6198630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 6208630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 6218630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000 6228630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 6238630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000 6248630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 6258630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 6268630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 6278630f839SAlex Deucher #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff 6288630f839SAlex Deucher #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 6298630f839SAlex Deucher #define UVD_STATUS__RBC_BUSY_MASK 0x1 6308630f839SAlex Deucher #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 6318630f839SAlex Deucher #define UVD_STATUS__VCPU_REPORT_MASK 0xfe 6328630f839SAlex Deucher #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 6338630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1 6348630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 6358630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2 6368630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 6378630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4 6388630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 6398630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8 6408630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 6418630f839SAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1 6428630f839SAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 6438630f839SAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe 6448630f839SAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 6458630f839SAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 6468630f839SAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 6478630f839SAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1 6488630f839SAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 6498630f839SAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe 6508630f839SAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 6518630f839SAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 6528630f839SAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 6538630f839SAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1 6548630f839SAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 6558630f839SAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe 6568630f839SAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 6578630f839SAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 6588630f839SAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 6598630f839SAlex Deucher #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff 6608630f839SAlex Deucher #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 6618630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1 6628630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0 6638630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2 6648630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1 6658630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4 6668630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2 6678630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8 6688630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3 6698630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10 6708630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4 6718630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20 6728630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5 6738630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3 6748630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 6758630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc 6768630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 6778630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf 6788630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0 6798630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0 6808630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4 6818630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00 6828630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8 6838630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000 6848630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc 6858630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1 6868630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 6878630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2 6888630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 6898630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4 6908630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 6918630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8 6928630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 6938630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10 6948630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 6958630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20 6968630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 6978630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40 6988630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 6998630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80 7008630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 7018630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100 7028630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 7038630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200 7048630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 7058630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400 7068630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 7078630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800 7088630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb 7098630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000 7108630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 7118630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000 7128630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 7138630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000 7148630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 7158630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000 7168630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 7178630f839SAlex Deucher #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1 7188630f839SAlex Deucher #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 7198630f839SAlex Deucher #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2 7208630f839SAlex Deucher #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 7218630f839SAlex Deucher #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c 7228630f839SAlex Deucher #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 7238630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff 7248630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0 7258630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100 7268630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8 7278630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200 7288630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9 7298630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400 7308630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa 7318630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800 7328630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb 7338630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000 7348630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc 7358630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000 7368630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd 7378630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000 7388630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c 7398630f839SAlex Deucher #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff 7408630f839SAlex Deucher #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0 7418630f839SAlex Deucher #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff 7428630f839SAlex Deucher #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0 7438630f839SAlex Deucher #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x1 7448630f839SAlex Deucher #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 7458630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 7468630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 7478630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 7488630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 7498630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 7508630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 7518630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 7528630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 7538630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 7548630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 7558630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 7568630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 7578630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 7588630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 7598630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 7608630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 7618630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 7628630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 7638630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 7648630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 7658630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 7668630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 7678630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 7688630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 7698630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 7708630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 7718630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 7728630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 7738630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 7748630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 7758630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 7768630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 7778630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 7788630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 7798630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 7808630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 7818630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7 7828630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 7838630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 7848630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 7858630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 7868630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 7878630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 7888630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 7898630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 7908630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 7918630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 7928630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 7938630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 7948630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 7958630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 7968630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 7978630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 7988630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 7998630f839SAlex Deucher 8008630f839SAlex Deucher #endif /* UVD_4_2_SH_MASK_H */ 801