13b1e08cbSAlex Deucher /* 23b1e08cbSAlex Deucher * UVD_6_0 Register documentation 33b1e08cbSAlex Deucher * 43b1e08cbSAlex Deucher * Copyright (C) 2014 Advanced Micro Devices, Inc. 53b1e08cbSAlex Deucher * 63b1e08cbSAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 73b1e08cbSAlex Deucher * copy of this software and associated documentation files (the "Software"), 83b1e08cbSAlex Deucher * to deal in the Software without restriction, including without limitation 93b1e08cbSAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 103b1e08cbSAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 113b1e08cbSAlex Deucher * Software is furnished to do so, subject to the following conditions: 123b1e08cbSAlex Deucher * 133b1e08cbSAlex Deucher * The above copyright notice and this permission notice shall be included 143b1e08cbSAlex Deucher * in all copies or substantial portions of the Software. 153b1e08cbSAlex Deucher * 163b1e08cbSAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 173b1e08cbSAlex Deucher * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 183b1e08cbSAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 193b1e08cbSAlex Deucher * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 203b1e08cbSAlex Deucher * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 213b1e08cbSAlex Deucher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 223b1e08cbSAlex Deucher */ 233b1e08cbSAlex Deucher 243b1e08cbSAlex Deucher #ifndef UVD_6_0_SH_MASK_H 253b1e08cbSAlex Deucher #define UVD_6_0_SH_MASK_H 263b1e08cbSAlex Deucher 273b1e08cbSAlex Deucher #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 283b1e08cbSAlex Deucher #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 293b1e08cbSAlex Deucher #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 303b1e08cbSAlex Deucher #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 313b1e08cbSAlex Deucher #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 323b1e08cbSAlex Deucher #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 333b1e08cbSAlex Deucher #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 343b1e08cbSAlex Deucher #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 353b1e08cbSAlex Deucher #define UVD_SEMA_CMD__MODE_MASK 0x40 363b1e08cbSAlex Deucher #define UVD_SEMA_CMD__MODE__SHIFT 0x6 373b1e08cbSAlex Deucher #define UVD_SEMA_CMD__VMID_EN_MASK 0x80 383b1e08cbSAlex Deucher #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 393b1e08cbSAlex Deucher #define UVD_SEMA_CMD__VMID_MASK 0xf00 403b1e08cbSAlex Deucher #define UVD_SEMA_CMD__VMID__SHIFT 0x8 413b1e08cbSAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 423b1e08cbSAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 433b1e08cbSAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe 443b1e08cbSAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 453b1e08cbSAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000 463b1e08cbSAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 473b1e08cbSAlex Deucher #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff 483b1e08cbSAlex Deucher #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 493b1e08cbSAlex Deucher #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff 503b1e08cbSAlex Deucher #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 513b1e08cbSAlex Deucher #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 523b1e08cbSAlex Deucher #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 533b1e08cbSAlex Deucher #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 543b1e08cbSAlex Deucher #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 553b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7 563b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 573b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 583b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 593b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 603b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 613b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 623b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 633b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 643b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 653b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 663b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 673b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 683b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 693b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 703b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 713b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 723b1e08cbSAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 733b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 743b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 753b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 763b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 773b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 783b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 793b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 803b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 813b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 823b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 833b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 843b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 853b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 863b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 873b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 883b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 893b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 903b1e08cbSAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 913b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 923b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 933b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 943b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 953b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 963b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 973b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 983b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 993b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 1003b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 1013b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 1023b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 1033b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 1043b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 1053b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 1063b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 1073b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 1083b1e08cbSAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 1093b1e08cbSAlex Deucher #define UVD_POWER_STATUS_U__UVD_POWER_STATUS_MASK 0x3 1103b1e08cbSAlex Deucher #define UVD_POWER_STATUS_U__UVD_POWER_STATUS__SHIFT 0x0 1113b1e08cbSAlex Deucher #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 1123b1e08cbSAlex Deucher #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1133b1e08cbSAlex Deucher #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 1143b1e08cbSAlex Deucher #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1153b1e08cbSAlex Deucher #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 1163b1e08cbSAlex Deucher #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1173b1e08cbSAlex Deucher #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 1183b1e08cbSAlex Deucher #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1193b1e08cbSAlex Deucher #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 1203b1e08cbSAlex Deucher #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1213b1e08cbSAlex Deucher #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 1223b1e08cbSAlex Deucher #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1233b1e08cbSAlex Deucher #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 1243b1e08cbSAlex Deucher #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 1253b1e08cbSAlex Deucher #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2 1263b1e08cbSAlex Deucher #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 1273b1e08cbSAlex Deucher #define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff 1283b1e08cbSAlex Deucher #define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0 1293b1e08cbSAlex Deucher #define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000 1303b1e08cbSAlex Deucher #define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10 1313b1e08cbSAlex Deucher #define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000 1323b1e08cbSAlex Deucher #define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f 1333b1e08cbSAlex Deucher #define UVD_CTX_INDEX__INDEX_MASK 0x1ff 1343b1e08cbSAlex Deucher #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 1353b1e08cbSAlex Deucher #define UVD_CTX_DATA__DATA_MASK 0xffffffff 1363b1e08cbSAlex Deucher #define UVD_CTX_DATA__DATA__SHIFT 0x0 1373b1e08cbSAlex Deucher #define UVD_CGC_GATE__SYS_MASK 0x1 1383b1e08cbSAlex Deucher #define UVD_CGC_GATE__SYS__SHIFT 0x0 1393b1e08cbSAlex Deucher #define UVD_CGC_GATE__UDEC_MASK 0x2 1403b1e08cbSAlex Deucher #define UVD_CGC_GATE__UDEC__SHIFT 0x1 1413b1e08cbSAlex Deucher #define UVD_CGC_GATE__MPEG2_MASK 0x4 1423b1e08cbSAlex Deucher #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 1433b1e08cbSAlex Deucher #define UVD_CGC_GATE__REGS_MASK 0x8 1443b1e08cbSAlex Deucher #define UVD_CGC_GATE__REGS__SHIFT 0x3 1453b1e08cbSAlex Deucher #define UVD_CGC_GATE__RBC_MASK 0x10 1463b1e08cbSAlex Deucher #define UVD_CGC_GATE__RBC__SHIFT 0x4 1473b1e08cbSAlex Deucher #define UVD_CGC_GATE__LMI_MC_MASK 0x20 1483b1e08cbSAlex Deucher #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 1493b1e08cbSAlex Deucher #define UVD_CGC_GATE__LMI_UMC_MASK 0x40 1503b1e08cbSAlex Deucher #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 1513b1e08cbSAlex Deucher #define UVD_CGC_GATE__IDCT_MASK 0x80 1523b1e08cbSAlex Deucher #define UVD_CGC_GATE__IDCT__SHIFT 0x7 1533b1e08cbSAlex Deucher #define UVD_CGC_GATE__MPRD_MASK 0x100 1543b1e08cbSAlex Deucher #define UVD_CGC_GATE__MPRD__SHIFT 0x8 1553b1e08cbSAlex Deucher #define UVD_CGC_GATE__MPC_MASK 0x200 1563b1e08cbSAlex Deucher #define UVD_CGC_GATE__MPC__SHIFT 0x9 1573b1e08cbSAlex Deucher #define UVD_CGC_GATE__LBSI_MASK 0x400 1583b1e08cbSAlex Deucher #define UVD_CGC_GATE__LBSI__SHIFT 0xa 1593b1e08cbSAlex Deucher #define UVD_CGC_GATE__LRBBM_MASK 0x800 1603b1e08cbSAlex Deucher #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 1613b1e08cbSAlex Deucher #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 1623b1e08cbSAlex Deucher #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 1633b1e08cbSAlex Deucher #define UVD_CGC_GATE__UDEC_CM_MASK 0x2000 1643b1e08cbSAlex Deucher #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 1653b1e08cbSAlex Deucher #define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 1663b1e08cbSAlex Deucher #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 1673b1e08cbSAlex Deucher #define UVD_CGC_GATE__UDEC_DB_MASK 0x8000 1683b1e08cbSAlex Deucher #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 1693b1e08cbSAlex Deucher #define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 1703b1e08cbSAlex Deucher #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 1713b1e08cbSAlex Deucher #define UVD_CGC_GATE__WCB_MASK 0x20000 1723b1e08cbSAlex Deucher #define UVD_CGC_GATE__WCB__SHIFT 0x11 1733b1e08cbSAlex Deucher #define UVD_CGC_GATE__VCPU_MASK 0x40000 1743b1e08cbSAlex Deucher #define UVD_CGC_GATE__VCPU__SHIFT 0x12 1753b1e08cbSAlex Deucher #define UVD_CGC_GATE__SCPU_MASK 0x80000 1763b1e08cbSAlex Deucher #define UVD_CGC_GATE__SCPU__SHIFT 0x13 1773b1e08cbSAlex Deucher #define UVD_CGC_GATE__JPEG_MASK 0x100000 1783b1e08cbSAlex Deucher #define UVD_CGC_GATE__JPEG__SHIFT 0x14 1793b1e08cbSAlex Deucher #define UVD_CGC_GATE__JPEG2_MASK 0x200000 1803b1e08cbSAlex Deucher #define UVD_CGC_GATE__JPEG2__SHIFT 0x15 1813b1e08cbSAlex Deucher #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 1823b1e08cbSAlex Deucher #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 1833b1e08cbSAlex Deucher #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2 1843b1e08cbSAlex Deucher #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 1853b1e08cbSAlex Deucher #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4 1863b1e08cbSAlex Deucher #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 1873b1e08cbSAlex Deucher #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8 1883b1e08cbSAlex Deucher #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 1893b1e08cbSAlex Deucher #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10 1903b1e08cbSAlex Deucher #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 1913b1e08cbSAlex Deucher #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20 1923b1e08cbSAlex Deucher #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 1933b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40 1943b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 1953b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80 1963b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 1973b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100 1983b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 1993b1e08cbSAlex Deucher #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200 2003b1e08cbSAlex Deucher #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 2013b1e08cbSAlex Deucher #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400 2023b1e08cbSAlex Deucher #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 2033b1e08cbSAlex Deucher #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800 2043b1e08cbSAlex Deucher #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 2053b1e08cbSAlex Deucher #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000 2063b1e08cbSAlex Deucher #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 2073b1e08cbSAlex Deucher #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000 2083b1e08cbSAlex Deucher #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 2093b1e08cbSAlex Deucher #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000 2103b1e08cbSAlex Deucher #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 2113b1e08cbSAlex Deucher #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000 2123b1e08cbSAlex Deucher #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 2133b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000 2143b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 2153b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000 2163b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 2173b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000 2183b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 2193b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 2203b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 2213b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000 2223b1e08cbSAlex Deucher #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 2233b1e08cbSAlex Deucher #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000 2243b1e08cbSAlex Deucher #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 2253b1e08cbSAlex Deucher #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000 2263b1e08cbSAlex Deucher #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 2273b1e08cbSAlex Deucher #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000 2283b1e08cbSAlex Deucher #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 2293b1e08cbSAlex Deucher #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000 2303b1e08cbSAlex Deucher #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 2313b1e08cbSAlex Deucher #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000 2323b1e08cbSAlex Deucher #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 2333b1e08cbSAlex Deucher #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000 2343b1e08cbSAlex Deucher #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 2353b1e08cbSAlex Deucher #define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000 2363b1e08cbSAlex Deucher #define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b 2373b1e08cbSAlex Deucher #define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000 2383b1e08cbSAlex Deucher #define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c 2393b1e08cbSAlex Deucher #define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000 2403b1e08cbSAlex Deucher #define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e 2413b1e08cbSAlex Deucher #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000 2423b1e08cbSAlex Deucher #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 2433b1e08cbSAlex Deucher #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 2443b1e08cbSAlex Deucher #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 2453b1e08cbSAlex Deucher #define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2 2463b1e08cbSAlex Deucher #define UVD_CGC_CTRL__JPEG2_MODE__SHIFT 0x1 2473b1e08cbSAlex Deucher #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c 2483b1e08cbSAlex Deucher #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 2493b1e08cbSAlex Deucher #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 2503b1e08cbSAlex Deucher #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 2513b1e08cbSAlex Deucher #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 2523b1e08cbSAlex Deucher #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 2533b1e08cbSAlex Deucher #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000 2543b1e08cbSAlex Deucher #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 2553b1e08cbSAlex Deucher #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 2563b1e08cbSAlex Deucher #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 2573b1e08cbSAlex Deucher #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000 2583b1e08cbSAlex Deucher #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 2593b1e08cbSAlex Deucher #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000 2603b1e08cbSAlex Deucher #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 2613b1e08cbSAlex Deucher #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 2623b1e08cbSAlex Deucher #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 2633b1e08cbSAlex Deucher #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000 2643b1e08cbSAlex Deucher #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 2653b1e08cbSAlex Deucher #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000 2663b1e08cbSAlex Deucher #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 2673b1e08cbSAlex Deucher #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 2683b1e08cbSAlex Deucher #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 2693b1e08cbSAlex Deucher #define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 2703b1e08cbSAlex Deucher #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 2713b1e08cbSAlex Deucher #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000 2723b1e08cbSAlex Deucher #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 2733b1e08cbSAlex Deucher #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000 2743b1e08cbSAlex Deucher #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 2753b1e08cbSAlex Deucher #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000 2763b1e08cbSAlex Deucher #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 2773b1e08cbSAlex Deucher #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 2783b1e08cbSAlex Deucher #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 2793b1e08cbSAlex Deucher #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 2803b1e08cbSAlex Deucher #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 2813b1e08cbSAlex Deucher #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000 2823b1e08cbSAlex Deucher #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 2833b1e08cbSAlex Deucher #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000 2843b1e08cbSAlex Deucher #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 2853b1e08cbSAlex Deucher #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 2863b1e08cbSAlex Deucher #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 2873b1e08cbSAlex Deucher #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 2883b1e08cbSAlex Deucher #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 2893b1e08cbSAlex Deucher #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 2903b1e08cbSAlex Deucher #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e 2913b1e08cbSAlex Deucher #define UVD_CGC_CTRL__JPEG_MODE_MASK 0x80000000 2923b1e08cbSAlex Deucher #define UVD_CGC_CTRL__JPEG_MODE__SHIFT 0x1f 2933b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1 2943b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 2953b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2 2963b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 2973b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4 2983b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 2993b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 3003b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 3013b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 3023b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 3033b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 3043b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 3053b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40 3063b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 3073b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 3083b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 3093b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100 3103b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 3113b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200 3123b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 3133b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400 3143b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 3153b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800 3163b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 3173b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000 3183b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 3193b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000 3203b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 3213b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000 3223b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 3233b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__JPEG_VCLK_MASK 0x8000 3243b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__JPEG_VCLK__SHIFT 0xf 3253b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__JPEG_SCLK_MASK 0x10000 3263b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__JPEG_SCLK__SHIFT 0x10 3273b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__JPEG2_VCLK_MASK 0x20000 3283b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__JPEG2_VCLK__SHIFT 0x11 3293b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__JPEG2_SCLK_MASK 0x40000 3303b1e08cbSAlex Deucher #define UVD_CGC_UDEC_STATUS__JPEG2_SCLK__SHIFT 0x12 3313b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1 3323b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 3333b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2 3343b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 3353b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4 3363b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 3373b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8 3383b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 3393b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70 3403b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4 3413b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80 3423b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 3433b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 3443b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 3453b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600 3463b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 3473b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800 3483b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 3493b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000 3503b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 3513b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000 3523b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 3533b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000 3543b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 3553b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000 3563b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 3573b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000 3583b1e08cbSAlex Deucher #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 3593b1e08cbSAlex Deucher #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1 3603b1e08cbSAlex Deucher #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 3613b1e08cbSAlex Deucher #define UVD_MASTINT_EN__VCPU_EN_MASK 0x2 3623b1e08cbSAlex Deucher #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 3633b1e08cbSAlex Deucher #define UVD_MASTINT_EN__SYS_EN_MASK 0x4 3643b1e08cbSAlex Deucher #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 3653b1e08cbSAlex Deucher #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0 3663b1e08cbSAlex Deucher #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 3673b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf 3683b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0 3693b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0 3703b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4 3713b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00 3723b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8 3733b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000 3743b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc 3753b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000 3763b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10 3773b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000 3783b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14 3793b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000 3803b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18 3813b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000 3823b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c 3833b1e08cbSAlex Deucher #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff 3843b1e08cbSAlex Deucher #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 3853b1e08cbSAlex Deucher #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 3863b1e08cbSAlex Deucher #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 3873b1e08cbSAlex Deucher #define UVD_LMI_CTRL__REQ_MODE_MASK 0x200 3883b1e08cbSAlex Deucher #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 3893b1e08cbSAlex Deucher #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800 3903b1e08cbSAlex Deucher #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 3913b1e08cbSAlex Deucher #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000 3923b1e08cbSAlex Deucher #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 3933b1e08cbSAlex Deucher #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000 3943b1e08cbSAlex Deucher #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 3953b1e08cbSAlex Deucher #define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000 3963b1e08cbSAlex Deucher #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 3973b1e08cbSAlex Deucher #define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000 3983b1e08cbSAlex Deucher #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 3993b1e08cbSAlex Deucher #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000 4003b1e08cbSAlex Deucher #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 4013b1e08cbSAlex Deucher #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 4023b1e08cbSAlex Deucher #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 4033b1e08cbSAlex Deucher #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000 4043b1e08cbSAlex Deucher #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 4053b1e08cbSAlex Deucher #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000 4063b1e08cbSAlex Deucher #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 4073b1e08cbSAlex Deucher #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000 4083b1e08cbSAlex Deucher #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 4093b1e08cbSAlex Deucher #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000 4103b1e08cbSAlex Deucher #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 4113b1e08cbSAlex Deucher #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000 4123b1e08cbSAlex Deucher #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 4133b1e08cbSAlex Deucher #define UVD_LMI_CTRL__RFU_MASK 0xf8000000 4143b1e08cbSAlex Deucher #define UVD_LMI_CTRL__RFU__SHIFT 0x1b 4153b1e08cbSAlex Deucher #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1 4163b1e08cbSAlex Deucher #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 4173b1e08cbSAlex Deucher #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2 4183b1e08cbSAlex Deucher #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 4193b1e08cbSAlex Deucher #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 4203b1e08cbSAlex Deucher #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 4213b1e08cbSAlex Deucher #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8 4223b1e08cbSAlex Deucher #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 4233b1e08cbSAlex Deucher #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10 4243b1e08cbSAlex Deucher #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 4253b1e08cbSAlex Deucher #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20 4263b1e08cbSAlex Deucher #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 4273b1e08cbSAlex Deucher #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40 4283b1e08cbSAlex Deucher #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 4293b1e08cbSAlex Deucher #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80 4303b1e08cbSAlex Deucher #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 4313b1e08cbSAlex Deucher #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100 4323b1e08cbSAlex Deucher #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 4333b1e08cbSAlex Deucher #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200 4343b1e08cbSAlex Deucher #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 4353b1e08cbSAlex Deucher #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400 4363b1e08cbSAlex Deucher #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 4373b1e08cbSAlex Deucher #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800 4383b1e08cbSAlex Deucher #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 4393b1e08cbSAlex Deucher #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000 4403b1e08cbSAlex Deucher #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 4413b1e08cbSAlex Deucher #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000 4423b1e08cbSAlex Deucher #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 4433b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3 4443b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 4453b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc 4463b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 4473b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30 4483b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 4493b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0 4503b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 4513b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300 4523b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 4533b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00 4543b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 4553b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000 4563b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 4573b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000 4583b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 4593b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000 4603b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 4613b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000 4623b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 4633b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000 4643b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 4653b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000 4663b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 4673b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000 4683b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 4693b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000 4703b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 4713b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000 4723b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 4733b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3 4743b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 4753b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc 4763b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 4773b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30 4783b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 4793b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0 4803b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 4813b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300 4823b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 4833b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00 4843b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 4853b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000 4863b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 4873b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000 4883b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 4893b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000 4903b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 4913b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000 4923b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 4933b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000 4943b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 4953b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000 4963b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 4973b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000 4983b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 4993b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000 5003b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 5013b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000 5023b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 5033b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000 5043b1e08cbSAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 5053b1e08cbSAlex Deucher #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 5063b1e08cbSAlex Deucher #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 5073b1e08cbSAlex Deucher #define UVD_MPC_CNTL__PERF_RST_MASK 0x40 5083b1e08cbSAlex Deucher #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 5093b1e08cbSAlex Deucher #define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00 5103b1e08cbSAlex Deucher #define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8 5113b1e08cbSAlex Deucher #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000 5123b1e08cbSAlex Deucher #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 5133b1e08cbSAlex Deucher #define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000 5143b1e08cbSAlex Deucher #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 5153b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f 5163b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 5173b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0 5183b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 5193b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 5203b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 5213b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 5223b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 5233b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 5243b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 5253b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f 5263b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 5273b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 5283b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 5293b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 5303b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 5313b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f 5323b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 5333b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 5343b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 5353b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000 5363b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 5373b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000 5383b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 5393b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000 5403b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 5413b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f 5423b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 5433b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0 5443b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 5453b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 5463b1e08cbSAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 5473b1e08cbSAlex Deucher #define UVD_MPC_SET_MUX__SET_0_MASK 0x7 5483b1e08cbSAlex Deucher #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 5493b1e08cbSAlex Deucher #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 5503b1e08cbSAlex Deucher #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 5513b1e08cbSAlex Deucher #define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 5523b1e08cbSAlex Deucher #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 5533b1e08cbSAlex Deucher #define UVD_MPC_SET_ALU__FUNCT_MASK 0x7 5543b1e08cbSAlex Deucher #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 5553b1e08cbSAlex Deucher #define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0 5563b1e08cbSAlex Deucher #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 5573b1e08cbSAlex Deucher #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff 5583b1e08cbSAlex Deucher #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 5593b1e08cbSAlex Deucher #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff 5603b1e08cbSAlex Deucher #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 5613b1e08cbSAlex Deucher #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff 5623b1e08cbSAlex Deucher #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 5633b1e08cbSAlex Deucher #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff 5643b1e08cbSAlex Deucher #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 5653b1e08cbSAlex Deucher #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff 5663b1e08cbSAlex Deucher #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 5673b1e08cbSAlex Deucher #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff 5683b1e08cbSAlex Deucher #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 5693b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf 5703b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 5713b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10 5723b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 5733b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20 5743b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 5753b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40 5763b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 5773b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80 5783b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 5793b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100 5803b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 5813b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 5823b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 5833b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400 5843b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 5853b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 5863b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 5873b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000 5883b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd 5893b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000 5903b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 5913b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000 5923b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 5933b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000 5943b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 5953b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__SUVD_EN_MASK 0x80000 5963b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13 5973b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000 5983b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 5993b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000 6003b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c 6013b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000 6023b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e 6033b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000 6043b1e08cbSAlex Deucher #define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f 6053b1e08cbSAlex Deucher #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1 6063b1e08cbSAlex Deucher #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 6073b1e08cbSAlex Deucher #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2 6083b1e08cbSAlex Deucher #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 6093b1e08cbSAlex Deucher #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4 6103b1e08cbSAlex Deucher #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 6113b1e08cbSAlex Deucher #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8 6123b1e08cbSAlex Deucher #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 6133b1e08cbSAlex Deucher #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10 6143b1e08cbSAlex Deucher #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 6153b1e08cbSAlex Deucher #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20 6163b1e08cbSAlex Deucher #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 6173b1e08cbSAlex Deucher #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40 6183b1e08cbSAlex Deucher #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 6193b1e08cbSAlex Deucher #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80 6203b1e08cbSAlex Deucher #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 6213b1e08cbSAlex Deucher #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100 6223b1e08cbSAlex Deucher #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 6233b1e08cbSAlex Deucher #define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200 6243b1e08cbSAlex Deucher #define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS__SHIFT 0x9 6253b1e08cbSAlex Deucher #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400 6263b1e08cbSAlex Deucher #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 6273b1e08cbSAlex Deucher #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800 6283b1e08cbSAlex Deucher #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 6293b1e08cbSAlex Deucher #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000 6303b1e08cbSAlex Deucher #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 6313b1e08cbSAlex Deucher #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000 6323b1e08cbSAlex Deucher #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 6333b1e08cbSAlex Deucher #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000 6343b1e08cbSAlex Deucher #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 6353b1e08cbSAlex Deucher #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000 6363b1e08cbSAlex Deucher #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 6373b1e08cbSAlex Deucher #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000 6383b1e08cbSAlex Deucher #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 6393b1e08cbSAlex Deucher #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x20000 6403b1e08cbSAlex Deucher #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 6413b1e08cbSAlex Deucher #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x40000 6423b1e08cbSAlex Deucher #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 6433b1e08cbSAlex Deucher #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x80000 6443b1e08cbSAlex Deucher #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 6453b1e08cbSAlex Deucher #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x100000 6463b1e08cbSAlex Deucher #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 6473b1e08cbSAlex Deucher #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x200000 6483b1e08cbSAlex Deucher #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 6493b1e08cbSAlex Deucher #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x400000 6503b1e08cbSAlex Deucher #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 6513b1e08cbSAlex Deucher #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x800000 6523b1e08cbSAlex Deucher #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 6533b1e08cbSAlex Deucher #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x1000000 6543b1e08cbSAlex Deucher #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 6553b1e08cbSAlex Deucher #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x2000000 6563b1e08cbSAlex Deucher #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 6573b1e08cbSAlex Deucher #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x4000000 6583b1e08cbSAlex Deucher #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 6593b1e08cbSAlex Deucher #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x8000000 6603b1e08cbSAlex Deucher #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 6613b1e08cbSAlex Deucher #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000 6623b1e08cbSAlex Deucher #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 6633b1e08cbSAlex Deucher #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000 6643b1e08cbSAlex Deucher #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 6653b1e08cbSAlex Deucher #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000 6663b1e08cbSAlex Deucher #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 6673b1e08cbSAlex Deucher #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000 6683b1e08cbSAlex Deucher #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 6693b1e08cbSAlex Deucher #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0xf 6703b1e08cbSAlex Deucher #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 6713b1e08cbSAlex Deucher #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0 6723b1e08cbSAlex Deucher #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 6733b1e08cbSAlex Deucher #define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0xf 6743b1e08cbSAlex Deucher #define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 6753b1e08cbSAlex Deucher #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0 6763b1e08cbSAlex Deucher #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 6773b1e08cbSAlex Deucher #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0 6783b1e08cbSAlex Deucher #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 6793b1e08cbSAlex Deucher #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f 6803b1e08cbSAlex Deucher #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 6813b1e08cbSAlex Deucher #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00 6823b1e08cbSAlex Deucher #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 6833b1e08cbSAlex Deucher #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 6843b1e08cbSAlex Deucher #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 6853b1e08cbSAlex Deucher #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000 6863b1e08cbSAlex Deucher #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 6873b1e08cbSAlex Deucher #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000 6883b1e08cbSAlex Deucher #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 6893b1e08cbSAlex Deucher #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 6903b1e08cbSAlex Deucher #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 6913b1e08cbSAlex Deucher #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff 6923b1e08cbSAlex Deucher #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 6933b1e08cbSAlex Deucher #define UVD_STATUS__RBC_BUSY_MASK 0x1 6943b1e08cbSAlex Deucher #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 6953b1e08cbSAlex Deucher #define UVD_STATUS__VCPU_REPORT_MASK 0xfe 6963b1e08cbSAlex Deucher #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 6973b1e08cbSAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1 6983b1e08cbSAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 6993b1e08cbSAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2 7003b1e08cbSAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 7013b1e08cbSAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4 7023b1e08cbSAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 7033b1e08cbSAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8 7043b1e08cbSAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 7053b1e08cbSAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1 7063b1e08cbSAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 7073b1e08cbSAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe 7083b1e08cbSAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 7093b1e08cbSAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 7103b1e08cbSAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 7113b1e08cbSAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1 7123b1e08cbSAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 7133b1e08cbSAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe 7143b1e08cbSAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 7153b1e08cbSAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 7163b1e08cbSAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 7173b1e08cbSAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1 7183b1e08cbSAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 7193b1e08cbSAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe 7203b1e08cbSAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 7213b1e08cbSAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 7223b1e08cbSAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 7233b1e08cbSAlex Deucher #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff 7243b1e08cbSAlex Deucher #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 7253b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SRE_MASK 0x1 7263b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 7273b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SIT_MASK 0x2 7283b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 7293b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SMP_MASK 0x4 7303b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 7313b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SCM_MASK 0x8 7323b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 7333b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SDB_MASK 0x10 7343b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 7353b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20 7363b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 7373b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40 7383b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 7393b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80 7403b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 7413b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100 7423b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 7433b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200 7443b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 7453b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400 7463b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 7473b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800 7483b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 7493b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 7503b1e08cbSAlex Deucher #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 7513b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1 7523b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 7533b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2 7543b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 7553b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4 7563b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 7573b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8 7583b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 7593b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10 7603b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 7613b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20 7623b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 7633b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40 7643b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 7653b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80 7663b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 7673b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100 7683b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 7693b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200 7703b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 7713b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x400 7723b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 7733b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800 7743b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 7753b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x1000 7763b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 7773b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000 7783b1e08cbSAlex Deucher #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 7793b1e08cbSAlex Deucher #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1 7803b1e08cbSAlex Deucher #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 7813b1e08cbSAlex Deucher #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2 7823b1e08cbSAlex Deucher #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 7833b1e08cbSAlex Deucher #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4 7843b1e08cbSAlex Deucher #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 7853b1e08cbSAlex Deucher #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8 7863b1e08cbSAlex Deucher #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 7873b1e08cbSAlex Deucher #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10 7883b1e08cbSAlex Deucher #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 7893b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID_MASK 0xf 7903b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT 0x0 7913b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID_MASK 0xf0 7923b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT 0x4 7933b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__DPB_VMID_MASK 0xf00 7943b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT 0x8 7953b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__DBW_VMID_MASK 0xf000 7963b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT 0xc 7973b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__LBSI_VMID_MASK 0xf0000 7983b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT 0x10 7993b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__IDCT_VMID_MASK 0xf00000 8003b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT 0x14 8013b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__JPEG_VMID_MASK 0xf000000 8023b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__JPEG_VMID__SHIFT 0x18 8033b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__JPEG2_VMID_MASK 0xf0000000 8043b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL__JPEG2_VMID__SHIFT 0x1c 8053b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID_MASK 0xf 8063b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT 0x0 8073b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID_MASK 0xf0 8083b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT 0x4 8093b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID_MASK 0xf00 8103b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT 0x8 8113b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID_MASK 0xf000 8123b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT 0xc 8133b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID_MASK 0xf0000 8143b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT 0x10 8153b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID_MASK 0xf00000 8163b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID__SHIFT 0x14 8173b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID_MASK 0xf000000 8183b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID__SHIFT 0x18 8193b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__VDMA_VMID_MASK 0xf0000000 8203b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL2__VDMA_VMID__SHIFT 0x1c 8213b1e08cbSAlex Deucher #define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1 8223b1e08cbSAlex Deucher #define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0 8233b1e08cbSAlex Deucher #define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2 8243b1e08cbSAlex Deucher #define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1 8253b1e08cbSAlex Deucher #define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4 8263b1e08cbSAlex Deucher #define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2 8273b1e08cbSAlex Deucher #define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8 8283b1e08cbSAlex Deucher #define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3 8293b1e08cbSAlex Deucher #define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10 8303b1e08cbSAlex Deucher #define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4 8313b1e08cbSAlex Deucher #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20 8323b1e08cbSAlex Deucher #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5 8333b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3 8343b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 8353b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc 8363b1e08cbSAlex Deucher #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 8373b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf 8383b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0 8393b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0 8403b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4 8413b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00 8423b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8 8433b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000 8443b1e08cbSAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc 8453b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1 8463b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 8473b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2 8483b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 8493b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4 8503b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 8513b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8 8523b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 8533b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10 8543b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 8553b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20 8563b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 8573b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40 8583b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 8593b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80 8603b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 8613b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100 8623b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 8633b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200 8643b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 8653b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400 8663b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 8673b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800 8683b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb 8693b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000 8703b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 8713b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000 8723b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 8733b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__JPEG_LS_EN_MASK 0x4000 8743b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT 0xe 8753b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__JPEG2_LS_EN_MASK 0x8000 8763b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__JPEG2_LS_EN__SHIFT 0xf 8773b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000 8783b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 8793b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000 8803b1e08cbSAlex Deucher #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 8813b1e08cbSAlex Deucher #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1 8823b1e08cbSAlex Deucher #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 8833b1e08cbSAlex Deucher #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2 8843b1e08cbSAlex Deucher #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 8853b1e08cbSAlex Deucher #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c 8863b1e08cbSAlex Deucher #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 8873b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID_MASK 0xf 8883b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT 0x0 8893b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID_MASK 0xf0 8903b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT 0x4 8913b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID_MASK 0xf00 8923b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT 0x8 8933b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID_MASK 0xf000 8943b1e08cbSAlex Deucher #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT 0xc 8953b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff 8963b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0 8973b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100 8983b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8 8993b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200 9003b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9 9013b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400 9023b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa 9033b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800 9043b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb 9053b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000 9063b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc 9073b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000 9083b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd 9093b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000 9103b1e08cbSAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c 9113b1e08cbSAlex Deucher #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff 9123b1e08cbSAlex Deucher #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0 9133b1e08cbSAlex Deucher #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff 9143b1e08cbSAlex Deucher #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0 9153b1e08cbSAlex Deucher #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3 9163b1e08cbSAlex Deucher #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 9173b1e08cbSAlex Deucher #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 9183b1e08cbSAlex Deucher #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 9193b1e08cbSAlex Deucher #define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x8 9203b1e08cbSAlex Deucher #define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3 9213b1e08cbSAlex Deucher #define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x10 9223b1e08cbSAlex Deucher #define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4 9233b1e08cbSAlex Deucher #define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x20 9243b1e08cbSAlex Deucher #define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5 9253b1e08cbSAlex Deucher #define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0xc0 9263b1e08cbSAlex Deucher #define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6 9273b1e08cbSAlex Deucher #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100 9283b1e08cbSAlex Deucher #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 9293b1e08cbSAlex Deucher #define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x200 9303b1e08cbSAlex Deucher #define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9 9313b1e08cbSAlex Deucher #define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x400 9323b1e08cbSAlex Deucher #define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa 9333b1e08cbSAlex Deucher #define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE_MASK 0xffffff 9343b1e08cbSAlex Deucher #define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE__SHIFT 0x0 9353b1e08cbSAlex Deucher #define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE_MASK 0xffffff 9363b1e08cbSAlex Deucher #define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE__SHIFT 0x0 9373b1e08cbSAlex Deucher #define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE_MASK 0xffffff 9383b1e08cbSAlex Deucher #define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE__SHIFT 0x0 9393b1e08cbSAlex Deucher #define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE_MASK 0xffffff 9403b1e08cbSAlex Deucher #define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE__SHIFT 0x0 9413b1e08cbSAlex Deucher #define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE_MASK 0xffffff 9423b1e08cbSAlex Deucher #define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE__SHIFT 0x0 9433b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 9443b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 9453b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 9463b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 9473b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 9483b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 9493b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 9503b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 9513b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 9523b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 9533b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 9543b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 9553b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 9563b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 9573b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 9583b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 9593b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 9603b1e08cbSAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 9613b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 9623b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 9633b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 9643b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 9653b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 9663b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 9673b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 9683b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 9693b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 9703b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 9713b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 9723b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 9733b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 9743b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 9753b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 9763b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 9773b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 9783b1e08cbSAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 9793b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7 9803b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 9813b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 9823b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 9833b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 9843b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 9853b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 9863b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 9873b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 9883b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 9893b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 9903b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 9913b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 9923b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 9933b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 9943b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 9953b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 9963b1e08cbSAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 9973b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 9983b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 9993b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 10003b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 10013b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 10023b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 10033b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 10043b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 10053b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 10063b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 10073b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 10083b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 10093b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 10103b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 10113b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 10123b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 10133b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 10143b1e08cbSAlex Deucher #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 10153b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x7 10163b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 10173b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 10183b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 10193b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 10203b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 10213b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 10223b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 10233b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 10243b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 10253b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 10263b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 10273b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 10283b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 10293b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 10303b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 10313b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 10323b1e08cbSAlex Deucher #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 10333b1e08cbSAlex Deucher 10343b1e08cbSAlex Deucher #endif /* UVD_6_0_SH_MASK_H */ 1035