1a5a25977SLeo Liu /* 2a5a25977SLeo Liu * Copyright (C) 2019 Advanced Micro Devices, Inc. 3a5a25977SLeo Liu * 4a5a25977SLeo Liu * Permission is hereby granted, free of charge, to any person obtaining a 5a5a25977SLeo Liu * copy of this software and associated documentation files (the "Software"), 6a5a25977SLeo Liu * to deal in the Software without restriction, including without limitation 7a5a25977SLeo Liu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a5a25977SLeo Liu * and/or sell copies of the Software, and to permit persons to whom the 9a5a25977SLeo Liu * Software is furnished to do so, subject to the following conditions: 10a5a25977SLeo Liu * 11a5a25977SLeo Liu * The above copyright notice and this permission notice shall be included 12a5a25977SLeo Liu * in all copies or substantial portions of the Software. 13a5a25977SLeo Liu * 14a5a25977SLeo Liu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15a5a25977SLeo Liu * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a5a25977SLeo Liu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a5a25977SLeo Liu * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18a5a25977SLeo Liu * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19a5a25977SLeo Liu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20a5a25977SLeo Liu */ 21a5a25977SLeo Liu 22a5a25977SLeo Liu #ifndef _vcn_3_0_0_SH_MASK_HEADER 23a5a25977SLeo Liu #define _vcn_3_0_0_SH_MASK_HEADER 24a5a25977SLeo Liu 25a5a25977SLeo Liu // addressBlock: uvd0_mmsch_dec 26a5a25977SLeo Liu //MMSCH_UCODE_ADDR 27a5a25977SLeo Liu #define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT 0x2 28a5a25977SLeo Liu #define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT 0x1f 29a5a25977SLeo Liu #define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFCL 30a5a25977SLeo Liu #define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK 0x80000000L 31a5a25977SLeo Liu //MMSCH_UCODE_DATA 32a5a25977SLeo Liu #define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT 0x0 33a5a25977SLeo Liu #define MMSCH_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 34a5a25977SLeo Liu //MMSCH_SRAM_ADDR 35a5a25977SLeo Liu #define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT 0x2 36a5a25977SLeo Liu #define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT 0x1f 37a5a25977SLeo Liu #define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK 0x00001FFCL 38a5a25977SLeo Liu #define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK 0x80000000L 39a5a25977SLeo Liu //MMSCH_SRAM_DATA 40a5a25977SLeo Liu #define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT 0x0 41a5a25977SLeo Liu #define MMSCH_SRAM_DATA__SRAM_DATA_MASK 0xFFFFFFFFL 42a5a25977SLeo Liu //MMSCH_VF_SRAM_OFFSET 43a5a25977SLeo Liu #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT 0x2 44a5a25977SLeo Liu #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT 0x10 45a5a25977SLeo Liu #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK 0x00001FFCL 46a5a25977SLeo Liu #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK 0x00FF0000L 47a5a25977SLeo Liu //MMSCH_DB_SRAM_OFFSET 48a5a25977SLeo Liu #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT 0x2 49a5a25977SLeo Liu #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT 0x10 50a5a25977SLeo Liu #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT 0x18 51a5a25977SLeo Liu #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK 0x00001FFCL 52a5a25977SLeo Liu #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK 0x00FF0000L 53a5a25977SLeo Liu #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK 0xFF000000L 54a5a25977SLeo Liu //MMSCH_CTX_SRAM_OFFSET 55a5a25977SLeo Liu #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT 0x2 56a5a25977SLeo Liu #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT 0x10 57a5a25977SLeo Liu #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK 0x00001FFCL 58a5a25977SLeo Liu #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK 0xFFFF0000L 59a5a25977SLeo Liu //MMSCH_CTL 60a5a25977SLeo Liu #define MMSCH_CTL__P_RUNSTALL__SHIFT 0x0 61a5a25977SLeo Liu #define MMSCH_CTL__P_RESET__SHIFT 0x1 62a5a25977SLeo Liu #define MMSCH_CTL__VFID_FIFO_EN__SHIFT 0x4 63a5a25977SLeo Liu #define MMSCH_CTL__P_LOCK__SHIFT 0x1f 64a5a25977SLeo Liu #define MMSCH_CTL__P_RUNSTALL_MASK 0x00000001L 65a5a25977SLeo Liu #define MMSCH_CTL__P_RESET_MASK 0x00000002L 66a5a25977SLeo Liu #define MMSCH_CTL__VFID_FIFO_EN_MASK 0x00000010L 67a5a25977SLeo Liu #define MMSCH_CTL__P_LOCK_MASK 0x80000000L 68a5a25977SLeo Liu //MMSCH_INTR 69a5a25977SLeo Liu #define MMSCH_INTR__INTR__SHIFT 0x0 70a5a25977SLeo Liu #define MMSCH_INTR__INTR_MASK 0x00001FFFL 71a5a25977SLeo Liu //MMSCH_INTR_ACK 72a5a25977SLeo Liu #define MMSCH_INTR_ACK__INTR__SHIFT 0x0 73a5a25977SLeo Liu #define MMSCH_INTR_ACK__INTR_MASK 0x00001FFFL 74a5a25977SLeo Liu //MMSCH_INTR_STATUS 75a5a25977SLeo Liu #define MMSCH_INTR_STATUS__INTR__SHIFT 0x0 76a5a25977SLeo Liu #define MMSCH_INTR_STATUS__INTR_MASK 0x00001FFFL 77a5a25977SLeo Liu //MMSCH_VF_VMID 78a5a25977SLeo Liu #define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0 79a5a25977SLeo Liu #define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5 80a5a25977SLeo Liu #define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL 81a5a25977SLeo Liu #define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L 82a5a25977SLeo Liu //MMSCH_VF_CTX_ADDR_LO 83a5a25977SLeo Liu #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6 84a5a25977SLeo Liu #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L 85a5a25977SLeo Liu //MMSCH_VF_CTX_ADDR_HI 86a5a25977SLeo Liu #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0 87a5a25977SLeo Liu #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL 88a5a25977SLeo Liu //MMSCH_VF_CTX_SIZE 89a5a25977SLeo Liu #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0 90a5a25977SLeo Liu #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL 91a5a25977SLeo Liu //MMSCH_VF_GPCOM_ADDR_LO 92a5a25977SLeo Liu #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6 93a5a25977SLeo Liu #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L 94a5a25977SLeo Liu //MMSCH_VF_GPCOM_ADDR_HI 95a5a25977SLeo Liu #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0 96a5a25977SLeo Liu #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL 97a5a25977SLeo Liu //MMSCH_VF_GPCOM_SIZE 98a5a25977SLeo Liu #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0 99a5a25977SLeo Liu #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL 100a5a25977SLeo Liu //MMSCH_VF_MAILBOX_HOST 101a5a25977SLeo Liu #define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0 102a5a25977SLeo Liu #define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL 103a5a25977SLeo Liu //MMSCH_VF_MAILBOX_RESP 104a5a25977SLeo Liu #define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0 105a5a25977SLeo Liu #define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 106a5a25977SLeo Liu //MMSCH_VF_MAILBOX_0 107a5a25977SLeo Liu #define MMSCH_VF_MAILBOX_0__DATA__SHIFT 0x0 108a5a25977SLeo Liu #define MMSCH_VF_MAILBOX_0__DATA_MASK 0xFFFFFFFFL 109a5a25977SLeo Liu //MMSCH_VF_MAILBOX_0_RESP 110a5a25977SLeo Liu #define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT 0x0 111a5a25977SLeo Liu #define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK 0xFFFFFFFFL 112a5a25977SLeo Liu //MMSCH_VF_MAILBOX_1 113a5a25977SLeo Liu #define MMSCH_VF_MAILBOX_1__DATA__SHIFT 0x0 114a5a25977SLeo Liu #define MMSCH_VF_MAILBOX_1__DATA_MASK 0xFFFFFFFFL 115a5a25977SLeo Liu //MMSCH_VF_MAILBOX_1_RESP 116a5a25977SLeo Liu #define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT 0x0 117a5a25977SLeo Liu #define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK 0xFFFFFFFFL 118a5a25977SLeo Liu //MMSCH_CNTL 119a5a25977SLeo Liu #define MMSCH_CNTL__CLK_EN__SHIFT 0x0 120a5a25977SLeo Liu #define MMSCH_CNTL__ED_ENABLE__SHIFT 0x1 121a5a25977SLeo Liu #define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5 122a5a25977SLeo Liu #define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT 0x9 123a5a25977SLeo Liu #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa 124a5a25977SLeo Liu #define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 125a5a25977SLeo Liu #define MMSCH_CNTL__TIMEOUT_DIS__SHIFT 0x1c 126a5a25977SLeo Liu #define MMSCH_CNTL__CLK_EN_MASK 0x00000001L 127a5a25977SLeo Liu #define MMSCH_CNTL__ED_ENABLE_MASK 0x00000002L 128a5a25977SLeo Liu #define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK 0x000001E0L 129a5a25977SLeo Liu #define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK 0x00000200L 130a5a25977SLeo Liu #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK 0x00000400L 131a5a25977SLeo Liu #define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 132a5a25977SLeo Liu #define MMSCH_CNTL__TIMEOUT_DIS_MASK 0x10000000L 133a5a25977SLeo Liu //MMSCH_NONCACHE_OFFSET0 134a5a25977SLeo Liu #define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT 0x0 135a5a25977SLeo Liu #define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL 136a5a25977SLeo Liu //MMSCH_NONCACHE_SIZE0 137a5a25977SLeo Liu #define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT 0x0 138a5a25977SLeo Liu #define MMSCH_NONCACHE_SIZE0__SIZE_MASK 0x00FFFFFFL 139a5a25977SLeo Liu //MMSCH_NONCACHE_OFFSET1 140a5a25977SLeo Liu #define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT 0x0 141a5a25977SLeo Liu #define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL 142a5a25977SLeo Liu //MMSCH_NONCACHE_SIZE1 143a5a25977SLeo Liu #define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT 0x0 144a5a25977SLeo Liu #define MMSCH_NONCACHE_SIZE1__SIZE_MASK 0x00FFFFFFL 145a5a25977SLeo Liu //MMSCH_PROC_STATE1 146a5a25977SLeo Liu #define MMSCH_PROC_STATE1__PC__SHIFT 0x0 147a5a25977SLeo Liu #define MMSCH_PROC_STATE1__PC_MASK 0xFFFFFFFFL 148a5a25977SLeo Liu //MMSCH_LAST_MC_ADDR 149a5a25977SLeo Liu #define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT 0x0 150a5a25977SLeo Liu #define MMSCH_LAST_MC_ADDR__RW__SHIFT 0x1f 151a5a25977SLeo Liu #define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK 0x0FFFFFFFL 152a5a25977SLeo Liu #define MMSCH_LAST_MC_ADDR__RW_MASK 0x80000000L 153a5a25977SLeo Liu //MMSCH_LAST_MEM_ACCESS_HI 154a5a25977SLeo Liu #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT 0x0 155a5a25977SLeo Liu #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT 0x8 156a5a25977SLeo Liu #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT 0xc 157a5a25977SLeo Liu #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK 0x00000007L 158a5a25977SLeo Liu #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK 0x00000700L 159a5a25977SLeo Liu #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK 0x00007000L 160a5a25977SLeo Liu //MMSCH_LAST_MEM_ACCESS_LO 161a5a25977SLeo Liu #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT 0x0 162a5a25977SLeo Liu #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK 0xFFFFFFFFL 163a5a25977SLeo Liu //MMSCH_IOV_ACTIVE_FCN_ID 164a5a25977SLeo Liu #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID__SHIFT 0x0 165a5a25977SLeo Liu #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF__SHIFT 0x1f 166a5a25977SLeo Liu #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID_MASK 0x0000001FL 167a5a25977SLeo Liu #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF_MASK 0x80000000L 168a5a25977SLeo Liu //MMSCH_SCRATCH_0 169a5a25977SLeo Liu #define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT 0x0 170a5a25977SLeo Liu #define MMSCH_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL 171a5a25977SLeo Liu //MMSCH_SCRATCH_1 172a5a25977SLeo Liu #define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT 0x0 173a5a25977SLeo Liu #define MMSCH_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL 174a5a25977SLeo Liu //MMSCH_GPUIOV_SCH_BLOCK_0 175a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT 0x0 176a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT 0x4 177a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT 0x8 178a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK 0x0000000FL 179a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK 0x000000F0L 180a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK 0x0000FF00L 181a5a25977SLeo Liu //MMSCH_GPUIOV_CMD_CONTROL_0 182a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT 0x0 183a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT 0x4 184a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5 185a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT 0x6 186a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT 0x8 187a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT 0x10 188a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK 0x0000000FL 189a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK 0x00000010L 190a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 191a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK 0x00000040L 192a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK 0x0000FF00L 193a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 194a5a25977SLeo Liu //MMSCH_GPUIOV_CMD_STATUS_0 195a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT 0x0 196a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK 0x0000000FL 197a5a25977SLeo Liu //MMSCH_GPUIOV_VM_BUSY_STATUS_0 198a5a25977SLeo Liu #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 199a5a25977SLeo Liu #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 200a5a25977SLeo Liu //MMSCH_GPUIOV_ACTIVE_FCNS_0 201a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT 0x0 202a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK 0xFFFFFFFFL 203a5a25977SLeo Liu //MMSCH_GPUIOV_ACTIVE_FCN_ID_0 204a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT 0x0 205a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT 0x8 206a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK 0x000000FFL 207a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK 0x00000F00L 208a5a25977SLeo Liu //MMSCH_GPUIOV_DW6_0 209a5a25977SLeo Liu #define MMSCH_GPUIOV_DW6_0__DATA__SHIFT 0x0 210a5a25977SLeo Liu #define MMSCH_GPUIOV_DW6_0__DATA_MASK 0xFFFFFFFFL 211a5a25977SLeo Liu //MMSCH_GPUIOV_DW7_0 212a5a25977SLeo Liu #define MMSCH_GPUIOV_DW7_0__DATA__SHIFT 0x0 213a5a25977SLeo Liu #define MMSCH_GPUIOV_DW7_0__DATA_MASK 0xFFFFFFFFL 214a5a25977SLeo Liu //MMSCH_GPUIOV_DW8_0 215a5a25977SLeo Liu #define MMSCH_GPUIOV_DW8_0__DATA__SHIFT 0x0 216a5a25977SLeo Liu #define MMSCH_GPUIOV_DW8_0__DATA_MASK 0xFFFFFFFFL 217a5a25977SLeo Liu //MMSCH_GPUIOV_SCH_BLOCK_1 218a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT 0x0 219a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT 0x4 220a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT 0x8 221a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK 0x0000000FL 222a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK 0x000000F0L 223a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK 0x0000FF00L 224a5a25977SLeo Liu //MMSCH_GPUIOV_CMD_CONTROL_1 225a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT 0x0 226a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT 0x4 227a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 228a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT 0x6 229a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT 0x8 230a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT 0x10 231a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK 0x0000000FL 232a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK 0x00000010L 233a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 234a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK 0x00000040L 235a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK 0x0000FF00L 236a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 237a5a25977SLeo Liu //MMSCH_GPUIOV_CMD_STATUS_1 238a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT 0x0 239a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK 0x0000000FL 240a5a25977SLeo Liu //MMSCH_GPUIOV_VM_BUSY_STATUS_1 241a5a25977SLeo Liu #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 242a5a25977SLeo Liu #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 243a5a25977SLeo Liu //MMSCH_GPUIOV_ACTIVE_FCNS_1 244a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT 0x0 245a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK 0xFFFFFFFFL 246a5a25977SLeo Liu //MMSCH_GPUIOV_ACTIVE_FCN_ID_1 247a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT 0x0 248a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT 0x8 249a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK 0x000000FFL 250a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK 0x00000F00L 251a5a25977SLeo Liu //MMSCH_GPUIOV_DW6_1 252a5a25977SLeo Liu #define MMSCH_GPUIOV_DW6_1__DATA__SHIFT 0x0 253a5a25977SLeo Liu #define MMSCH_GPUIOV_DW6_1__DATA_MASK 0xFFFFFFFFL 254a5a25977SLeo Liu //MMSCH_GPUIOV_DW7_1 255a5a25977SLeo Liu #define MMSCH_GPUIOV_DW7_1__DATA__SHIFT 0x0 256a5a25977SLeo Liu #define MMSCH_GPUIOV_DW7_1__DATA_MASK 0xFFFFFFFFL 257a5a25977SLeo Liu //MMSCH_GPUIOV_DW8_1 258a5a25977SLeo Liu #define MMSCH_GPUIOV_DW8_1__DATA__SHIFT 0x0 259a5a25977SLeo Liu #define MMSCH_GPUIOV_DW8_1__DATA_MASK 0xFFFFFFFFL 260a5a25977SLeo Liu //MMSCH_GPUIOV_CNTXT 261a5a25977SLeo Liu #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT 0x0 262a5a25977SLeo Liu #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT 0x7 263a5a25977SLeo Liu #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa 264a5a25977SLeo Liu #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK 0x0000007FL 265a5a25977SLeo Liu #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK 0x00000080L 266a5a25977SLeo Liu #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK 0xFFFFFC00L 267a5a25977SLeo Liu //MMSCH_SCRATCH_2 268a5a25977SLeo Liu #define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT 0x0 269a5a25977SLeo Liu #define MMSCH_SCRATCH_2__SCRATCH_2_MASK 0xFFFFFFFFL 270a5a25977SLeo Liu //MMSCH_SCRATCH_3 271a5a25977SLeo Liu #define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT 0x0 272a5a25977SLeo Liu #define MMSCH_SCRATCH_3__SCRATCH_3_MASK 0xFFFFFFFFL 273a5a25977SLeo Liu //MMSCH_SCRATCH_4 274a5a25977SLeo Liu #define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT 0x0 275a5a25977SLeo Liu #define MMSCH_SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL 276a5a25977SLeo Liu //MMSCH_SCRATCH_5 277a5a25977SLeo Liu #define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT 0x0 278a5a25977SLeo Liu #define MMSCH_SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL 279a5a25977SLeo Liu //MMSCH_SCRATCH_6 280a5a25977SLeo Liu #define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT 0x0 281a5a25977SLeo Liu #define MMSCH_SCRATCH_6__SCRATCH_6_MASK 0xFFFFFFFFL 282a5a25977SLeo Liu //MMSCH_SCRATCH_7 283a5a25977SLeo Liu #define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT 0x0 284a5a25977SLeo Liu #define MMSCH_SCRATCH_7__SCRATCH_7_MASK 0xFFFFFFFFL 285a5a25977SLeo Liu //MMSCH_VFID_FIFO_HEAD_0 286a5a25977SLeo Liu #define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT 0x0 287a5a25977SLeo Liu #define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK 0x0000003FL 288a5a25977SLeo Liu //MMSCH_VFID_FIFO_TAIL_0 289a5a25977SLeo Liu #define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT 0x0 290a5a25977SLeo Liu #define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK 0x0000003FL 291a5a25977SLeo Liu //MMSCH_VFID_FIFO_HEAD_1 292a5a25977SLeo Liu #define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT 0x0 293a5a25977SLeo Liu #define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK 0x0000003FL 294a5a25977SLeo Liu //MMSCH_VFID_FIFO_TAIL_1 295a5a25977SLeo Liu #define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT 0x0 296a5a25977SLeo Liu #define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK 0x0000003FL 297a5a25977SLeo Liu //MMSCH_NACK_STATUS 298a5a25977SLeo Liu #define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT 0x0 299a5a25977SLeo Liu #define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT 0x2 300a5a25977SLeo Liu #define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK 0x00000003L 301a5a25977SLeo Liu #define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK 0x0000000CL 302a5a25977SLeo Liu //MMSCH_VF_MAILBOX0_DATA 303a5a25977SLeo Liu #define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT 0x0 304a5a25977SLeo Liu #define MMSCH_VF_MAILBOX0_DATA__DATA_MASK 0xFFFFFFFFL 305a5a25977SLeo Liu //MMSCH_VF_MAILBOX1_DATA 306a5a25977SLeo Liu #define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT 0x0 307a5a25977SLeo Liu #define MMSCH_VF_MAILBOX1_DATA__DATA_MASK 0xFFFFFFFFL 308a5a25977SLeo Liu //MMSCH_GPUIOV_SCH_BLOCK_IP_0 309a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT 0x0 310a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT 0x4 311a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT 0x8 312a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK 0x0000000FL 313a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK 0x000000F0L 314a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK 0x0000FF00L 315a5a25977SLeo Liu //MMSCH_GPUIOV_CMD_STATUS_IP_0 316a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT 0x0 317a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK 0x0000000FL 318a5a25977SLeo Liu //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 319a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT 0x0 320a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT 0x8 321a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK 0x000000FFL 322a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK 0x00000F00L 323a5a25977SLeo Liu //MMSCH_GPUIOV_SCH_BLOCK_IP_1 324a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT 0x0 325a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT 0x4 326a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT 0x8 327a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK 0x0000000FL 328a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK 0x000000F0L 329a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK 0x0000FF00L 330a5a25977SLeo Liu //MMSCH_GPUIOV_CMD_STATUS_IP_1 331a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT 0x0 332a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK 0x0000000FL 333a5a25977SLeo Liu //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 334a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT 0x0 335a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT 0x8 336a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK 0x000000FFL 337a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK 0x00000F00L 338a5a25977SLeo Liu //MMSCH_GPUIOV_CNTXT_IP 339a5a25977SLeo Liu #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT 0x0 340a5a25977SLeo Liu #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT 0x7 341a5a25977SLeo Liu #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK 0x0000007FL 342a5a25977SLeo Liu #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK 0x00000080L 343a5a25977SLeo Liu //MMSCH_GPUIOV_SCH_BLOCK_2 344a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT 0x0 345a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT 0x4 346a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT 0x8 347a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK 0x0000000FL 348a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK 0x000000F0L 349a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK 0x0000FF00L 350a5a25977SLeo Liu //MMSCH_GPUIOV_CMD_CONTROL_2 351a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT 0x0 352a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT 0x4 353a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5 354a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT 0x6 355a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT 0x8 356a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT 0x10 357a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK 0x0000000FL 358a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK 0x00000010L 359a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 360a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK 0x00000040L 361a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK 0x0000FF00L 362a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 363a5a25977SLeo Liu //MMSCH_GPUIOV_CMD_STATUS_2 364a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT 0x0 365a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK 0x0000000FL 366a5a25977SLeo Liu //MMSCH_GPUIOV_VM_BUSY_STATUS_2 367a5a25977SLeo Liu #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 368a5a25977SLeo Liu #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 369a5a25977SLeo Liu //MMSCH_GPUIOV_ACTIVE_FCNS_2 370a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT 0x0 371a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK 0xFFFFFFFFL 372a5a25977SLeo Liu //MMSCH_GPUIOV_ACTIVE_FCN_ID_2 373a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT 0x0 374a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT 0x8 375a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK 0x000000FFL 376a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK 0x00000F00L 377a5a25977SLeo Liu //MMSCH_GPUIOV_DW6_2 378a5a25977SLeo Liu #define MMSCH_GPUIOV_DW6_2__DATA__SHIFT 0x0 379a5a25977SLeo Liu #define MMSCH_GPUIOV_DW6_2__DATA_MASK 0xFFFFFFFFL 380a5a25977SLeo Liu //MMSCH_GPUIOV_DW7_2 381a5a25977SLeo Liu #define MMSCH_GPUIOV_DW7_2__DATA__SHIFT 0x0 382a5a25977SLeo Liu #define MMSCH_GPUIOV_DW7_2__DATA_MASK 0xFFFFFFFFL 383a5a25977SLeo Liu //MMSCH_GPUIOV_DW8_2 384a5a25977SLeo Liu #define MMSCH_GPUIOV_DW8_2__DATA__SHIFT 0x0 385a5a25977SLeo Liu #define MMSCH_GPUIOV_DW8_2__DATA_MASK 0xFFFFFFFFL 386a5a25977SLeo Liu //MMSCH_GPUIOV_SCH_BLOCK_IP_2 387a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT 0x0 388a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT 0x4 389a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT 0x8 390a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK 0x0000000FL 391a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK 0x000000F0L 392a5a25977SLeo Liu #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK 0x0000FF00L 393a5a25977SLeo Liu //MMSCH_GPUIOV_CMD_STATUS_IP_2 394a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT 0x0 395a5a25977SLeo Liu #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK 0x0000000FL 396a5a25977SLeo Liu //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 397a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT 0x0 398a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT 0x8 399a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK 0x000000FFL 400a5a25977SLeo Liu #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK 0x00000F00L 401a5a25977SLeo Liu //MMSCH_VFID_FIFO_HEAD_2 402a5a25977SLeo Liu #define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT 0x0 403a5a25977SLeo Liu #define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK 0x0000003FL 404a5a25977SLeo Liu //MMSCH_VFID_FIFO_TAIL_2 405a5a25977SLeo Liu #define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT 0x0 406a5a25977SLeo Liu #define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK 0x0000003FL 407a5a25977SLeo Liu //MMSCH_VM_BUSY_STATUS_0 408a5a25977SLeo Liu #define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 409a5a25977SLeo Liu #define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 410a5a25977SLeo Liu //MMSCH_VM_BUSY_STATUS_1 411a5a25977SLeo Liu #define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 412a5a25977SLeo Liu #define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 413a5a25977SLeo Liu //MMSCH_VM_BUSY_STATUS_2 414a5a25977SLeo Liu #define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 415a5a25977SLeo Liu #define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 416a5a25977SLeo Liu 417a5a25977SLeo Liu 418a5a25977SLeo Liu // addressBlock: uvd0_jpegnpdec 419a5a25977SLeo Liu //UVD_JPEG_CNTL 420a5a25977SLeo Liu #define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 421a5a25977SLeo Liu #define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 422a5a25977SLeo Liu #define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3 423a5a25977SLeo Liu #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4 424a5a25977SLeo Liu #define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L 425a5a25977SLeo Liu #define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L 426a5a25977SLeo Liu #define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L 427a5a25977SLeo Liu #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L 428a5a25977SLeo Liu //UVD_JPEG_RB_BASE 429a5a25977SLeo Liu #define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 430a5a25977SLeo Liu #define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 431a5a25977SLeo Liu #define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL 432a5a25977SLeo Liu #define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L 433a5a25977SLeo Liu //UVD_JPEG_RB_WPTR 434a5a25977SLeo Liu #define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 435a5a25977SLeo Liu #define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L 436a5a25977SLeo Liu //UVD_JPEG_RB_RPTR 437a5a25977SLeo Liu #define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 438a5a25977SLeo Liu #define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L 439a5a25977SLeo Liu //UVD_JPEG_RB_SIZE 440a5a25977SLeo Liu #define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 441a5a25977SLeo Liu #define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L 442a5a25977SLeo Liu //UVD_JPEG_DEC_CNT 443a5a25977SLeo Liu #define UVD_JPEG_DEC_CNT__DECODE_COUNT__SHIFT 0x0 444a5a25977SLeo Liu #define UVD_JPEG_DEC_CNT__DECODE_COUNT_MASK 0xFFFFFFFFL 445a5a25977SLeo Liu //UVD_JPEG_SPS_INFO 446a5a25977SLeo Liu #define UVD_JPEG_SPS_INFO__PIC_WIDTH__SHIFT 0x0 447a5a25977SLeo Liu #define UVD_JPEG_SPS_INFO__PIC_HEIGHT__SHIFT 0x10 448a5a25977SLeo Liu #define UVD_JPEG_SPS_INFO__PIC_WIDTH_MASK 0x0000FFFFL 449a5a25977SLeo Liu #define UVD_JPEG_SPS_INFO__PIC_HEIGHT_MASK 0xFFFF0000L 450a5a25977SLeo Liu //UVD_JPEG_SPS1_INFO 451a5a25977SLeo Liu #define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC__SHIFT 0x0 452a5a25977SLeo Liu #define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT__SHIFT 0x3 453a5a25977SLeo Liu #define UVD_JPEG_SPS1_INFO__OUT_FMT_422__SHIFT 0x4 454a5a25977SLeo Liu #define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC_MASK 0x00000007L 455a5a25977SLeo Liu #define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT_MASK 0x00000008L 456a5a25977SLeo Liu #define UVD_JPEG_SPS1_INFO__OUT_FMT_422_MASK 0x00000010L 457a5a25977SLeo Liu //UVD_JPEG_RE_TIMER 458a5a25977SLeo Liu #define UVD_JPEG_RE_TIMER__TIMER_OUT__SHIFT 0x0 459a5a25977SLeo Liu #define UVD_JPEG_RE_TIMER__TIMER_OUT_EN__SHIFT 0x10 460a5a25977SLeo Liu #define UVD_JPEG_RE_TIMER__TIMER_OUT_MASK 0x000000FFL 461a5a25977SLeo Liu #define UVD_JPEG_RE_TIMER__TIMER_OUT_EN_MASK 0x00010000L 462a5a25977SLeo Liu //UVD_JPEG_DEC_SCRATCH0 463a5a25977SLeo Liu #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0 464a5a25977SLeo Liu #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 465a5a25977SLeo Liu //UVD_JPEG_INT_EN 466a5a25977SLeo Liu #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0 467a5a25977SLeo Liu #define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1 468a5a25977SLeo Liu #define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2 469a5a25977SLeo Liu #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6 470a5a25977SLeo Liu #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7 471a5a25977SLeo Liu #define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8 472a5a25977SLeo Liu #define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9 473a5a25977SLeo Liu #define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa 474a5a25977SLeo Liu #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb 475a5a25977SLeo Liu #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc 476a5a25977SLeo Liu #define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd 477a5a25977SLeo Liu #define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe 478a5a25977SLeo Liu #define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf 479a5a25977SLeo Liu #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L 480a5a25977SLeo Liu #define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L 481a5a25977SLeo Liu #define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L 482a5a25977SLeo Liu #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L 483a5a25977SLeo Liu #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L 484a5a25977SLeo Liu #define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L 485a5a25977SLeo Liu #define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L 486a5a25977SLeo Liu #define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L 487a5a25977SLeo Liu #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L 488a5a25977SLeo Liu #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L 489a5a25977SLeo Liu #define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L 490a5a25977SLeo Liu #define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L 491a5a25977SLeo Liu #define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L 492a5a25977SLeo Liu //UVD_JPEG_INT_STAT 493a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0 494a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1 495a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2 496a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6 497a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7 498a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8 499a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9 500a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa 501a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb 502a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc 503a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd 504a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe 505a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf 506a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L 507a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L 508a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L 509a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L 510a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L 511a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L 512a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L 513a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L 514a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L 515a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L 516a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L 517a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L 518a5a25977SLeo Liu #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L 519a5a25977SLeo Liu //UVD_JPEG_TIER_CNTL0 520a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__TIER_SEL__SHIFT 0x0 521a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__Y_COMP_ID__SHIFT 0x2 522a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__U_COMP_ID__SHIFT 0x4 523a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__V_COMP_ID__SHIFT 0x6 524a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC__SHIFT 0x8 525a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC__SHIFT 0xb 526a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC__SHIFT 0xe 527a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC__SHIFT 0x11 528a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC__SHIFT 0x14 529a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC__SHIFT 0x17 530a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__Y_TQ__SHIFT 0x1a 531a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__U_TQ__SHIFT 0x1c 532a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__V_TQ__SHIFT 0x1e 533a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__TIER_SEL_MASK 0x00000003L 534a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__Y_COMP_ID_MASK 0x0000000CL 535a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__U_COMP_ID_MASK 0x00000030L 536a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__V_COMP_ID_MASK 0x000000C0L 537a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC_MASK 0x00000700L 538a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC_MASK 0x00003800L 539a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC_MASK 0x0001C000L 540a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC_MASK 0x000E0000L 541a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC_MASK 0x00700000L 542a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC_MASK 0x03800000L 543a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__Y_TQ_MASK 0x0C000000L 544a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__U_TQ_MASK 0x30000000L 545a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL0__V_TQ_MASK 0xC0000000L 546a5a25977SLeo Liu //UVD_JPEG_TIER_CNTL1 547a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL1__SRC_WIDTH__SHIFT 0x0 548a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT__SHIFT 0x10 549a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL1__SRC_WIDTH_MASK 0x0000FFFFL 550a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT_MASK 0xFFFF0000L 551a5a25977SLeo Liu //UVD_JPEG_TIER_CNTL2 552a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL__SHIFT 0x0 553a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TBL_TYPE__SHIFT 0x1 554a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TQ__SHIFT 0x2 555a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TH__SHIFT 0x4 556a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TC__SHIFT 0x6 557a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TD__SHIFT 0x7 558a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TA__SHIFT 0xa 559a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN__SHIFT 0xe 560a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__DRI_VAL__SHIFT 0x10 561a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL_MASK 0x00000001L 562a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TBL_TYPE_MASK 0x00000002L 563a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TQ_MASK 0x0000000CL 564a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TH_MASK 0x00000030L 565a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TC_MASK 0x00000040L 566a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TD_MASK 0x00000380L 567a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TA_MASK 0x00001C00L 568a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN_MASK 0x00004000L 569a5a25977SLeo Liu #define UVD_JPEG_TIER_CNTL2__DRI_VAL_MASK 0xFFFF0000L 570a5a25977SLeo Liu //UVD_JPEG_TIER_STATUS 571a5a25977SLeo Liu #define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE__SHIFT 0x0 572a5a25977SLeo Liu #define UVD_JPEG_TIER_STATUS__DECODE_DONE__SHIFT 0x1 573a5a25977SLeo Liu #define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE_MASK 0x00000001L 574a5a25977SLeo Liu #define UVD_JPEG_TIER_STATUS__DECODE_DONE_MASK 0x00000002L 575a5a25977SLeo Liu //UVD_JPEG_OUTBUF_CNTL 576a5a25977SLeo Liu #define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT__SHIFT 0x0 577a5a25977SLeo Liu #define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN__SHIFT 0x2 578a5a25977SLeo Liu #define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX__SHIFT 0x6 579a5a25977SLeo Liu #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT__SHIFT 0x7 580a5a25977SLeo Liu #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER__SHIFT 0x9 581a5a25977SLeo Liu #define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT_MASK 0x00000003L 582a5a25977SLeo Liu #define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN_MASK 0x00000004L 583a5a25977SLeo Liu #define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX_MASK 0x00000040L 584a5a25977SLeo Liu #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT_MASK 0x00000180L 585a5a25977SLeo Liu #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER_MASK 0x00001E00L 586a5a25977SLeo Liu //UVD_JPEG_OUTBUF_WPTR 587a5a25977SLeo Liu #define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR__SHIFT 0x0 588a5a25977SLeo Liu #define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR_MASK 0xFFFFFFFFL 589a5a25977SLeo Liu //UVD_JPEG_OUTBUF_RPTR 590a5a25977SLeo Liu #define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR__SHIFT 0x0 591a5a25977SLeo Liu #define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR_MASK 0xFFFFFFFFL 592a5a25977SLeo Liu //UVD_JPEG_PITCH 593a5a25977SLeo Liu #define UVD_JPEG_PITCH__PITCH__SHIFT 0x0 594a5a25977SLeo Liu #define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL 595a5a25977SLeo Liu //UVD_JPEG_UV_PITCH 596a5a25977SLeo Liu #define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0 597a5a25977SLeo Liu #define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL 598a5a25977SLeo Liu //JPEG_DEC_Y_GFX10_TILING_SURFACE 599a5a25977SLeo Liu #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 600a5a25977SLeo Liu #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 601a5a25977SLeo Liu //JPEG_DEC_UV_GFX10_TILING_SURFACE 602a5a25977SLeo Liu #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 603a5a25977SLeo Liu #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 604a5a25977SLeo Liu //JPEG_DEC_GFX10_ADDR_CONFIG 605a5a25977SLeo Liu #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 606a5a25977SLeo Liu #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 607a5a25977SLeo Liu #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 608a5a25977SLeo Liu #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 609a5a25977SLeo Liu #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 610a5a25977SLeo Liu #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 611a5a25977SLeo Liu #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 612a5a25977SLeo Liu #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 613a5a25977SLeo Liu #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 614a5a25977SLeo Liu #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 615a5a25977SLeo Liu //JPEG_DEC_ADDR_MODE 616a5a25977SLeo Liu #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 617a5a25977SLeo Liu #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 618a5a25977SLeo Liu #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 619a5a25977SLeo Liu #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 620a5a25977SLeo Liu #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 621a5a25977SLeo Liu #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 622a5a25977SLeo Liu //UVD_JPEG_OUTPUT_XY 623a5a25977SLeo Liu #define UVD_JPEG_OUTPUT_XY__OUTPUT_X__SHIFT 0x0 624a5a25977SLeo Liu #define UVD_JPEG_OUTPUT_XY__OUTPUT_Y__SHIFT 0x10 625a5a25977SLeo Liu #define UVD_JPEG_OUTPUT_XY__OUTPUT_X_MASK 0x00003FFFL 626a5a25977SLeo Liu #define UVD_JPEG_OUTPUT_XY__OUTPUT_Y_MASK 0x3FFF0000L 627a5a25977SLeo Liu //UVD_JPEG_GPCOM_CMD 628a5a25977SLeo Liu #define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 629a5a25977SLeo Liu #define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL 630a5a25977SLeo Liu //UVD_JPEG_GPCOM_DATA0 631a5a25977SLeo Liu #define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 632a5a25977SLeo Liu #define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 633a5a25977SLeo Liu //UVD_JPEG_GPCOM_DATA1 634a5a25977SLeo Liu #define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 635a5a25977SLeo Liu #define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 636a5a25977SLeo Liu //UVD_JPEG_INDEX 637a5a25977SLeo Liu #define UVD_JPEG_INDEX__INDEX__SHIFT 0x0 638a5a25977SLeo Liu #define UVD_JPEG_INDEX__INDEX_MASK 0x000001FFL 639a5a25977SLeo Liu //UVD_JPEG_DATA 640a5a25977SLeo Liu #define UVD_JPEG_DATA__DATA__SHIFT 0x0 641a5a25977SLeo Liu #define UVD_JPEG_DATA__DATA_MASK 0xFFFFFFFFL 642a5a25977SLeo Liu //UVD_JPEG_SCRATCH1 643a5a25977SLeo Liu #define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0 644a5a25977SLeo Liu #define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 645a5a25977SLeo Liu //UVD_JPEG_DEC_SOFT_RST 646a5a25977SLeo Liu #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0 647a5a25977SLeo Liu #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10 648a5a25977SLeo Liu #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L 649a5a25977SLeo Liu #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 650a5a25977SLeo Liu 651a5a25977SLeo Liu 652a5a25977SLeo Liu // addressBlock: uvd0_uvd_jpeg_enc_dec 653a5a25977SLeo Liu //UVD_JPEG_ENC_ECS_VALID_BYTES 654a5a25977SLeo Liu #define UVD_JPEG_ENC_ECS_VALID_BYTES__TOTAL_NUM_BYTES__SHIFT 0x0 655a5a25977SLeo Liu #define UVD_JPEG_ENC_ECS_VALID_BYTES__TOTAL_NUM_BYTES_MASK 0xFFFFFFFFL 656a5a25977SLeo Liu //UVD_JPEG_ENC_INT_EN 657a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT 0x0 658a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT 0x1 659a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT 0x2 660a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT 0x3 661a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT 0x4 662a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT 0x5 663a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT 0x6 664a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK 0x00000001L 665a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK 0x00000002L 666a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK 0x00000004L 667a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK 0x00000008L 668a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK 0x00000010L 669a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK 0x00000020L 670a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK 0x00000040L 671a5a25977SLeo Liu //UVD_JPEG_ENC_INT_STATUS 672a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT 0x0 673a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT 0x1 674a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT 0x2 675a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT 0x3 676a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT 0x4 677a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT 0x5 678a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT 0x6 679a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK 0x00000001L 680a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK 0x00000002L 681a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK 0x00000004L 682a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK 0x00000008L 683a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK 0x00000010L 684a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK 0x00000020L 685a5a25977SLeo Liu #define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK 0x00000040L 686a5a25977SLeo Liu //UVD_JPEG_ENC_PEL_CNTL 687a5a25977SLeo Liu #define UVD_JPEG_ENC_PEL_CNTL__LUMA_PAD_DATA__SHIFT 0x0 688a5a25977SLeo Liu #define UVD_JPEG_ENC_PEL_CNTL__CHROMAU_PAD_DATA__SHIFT 0x8 689a5a25977SLeo Liu #define UVD_JPEG_ENC_PEL_CNTL__CHROMAV_PAD_DATA__SHIFT 0x10 690a5a25977SLeo Liu #define UVD_JPEG_ENC_PEL_CNTL__USER_MODE_SEL__SHIFT 0x18 691a5a25977SLeo Liu #define UVD_JPEG_ENC_PEL_CNTL__LUMA_PAD_DATA_MASK 0x000000FFL 692a5a25977SLeo Liu #define UVD_JPEG_ENC_PEL_CNTL__CHROMAU_PAD_DATA_MASK 0x0000FF00L 693a5a25977SLeo Liu #define UVD_JPEG_ENC_PEL_CNTL__CHROMAV_PAD_DATA_MASK 0x00FF0000L 694a5a25977SLeo Liu #define UVD_JPEG_ENC_PEL_CNTL__USER_MODE_SEL_MASK 0x03000000L 695a5a25977SLeo Liu //UVD_JPEG_ENC_RESTART_MARKER_CNTL 696a5a25977SLeo Liu #define UVD_JPEG_ENC_RESTART_MARKER_CNTL__RESTART_INTERVAL__SHIFT 0x0 697a5a25977SLeo Liu #define UVD_JPEG_ENC_RESTART_MARKER_CNTL__RESTART_MARKER_ENABLE__SHIFT 0x10 698a5a25977SLeo Liu #define UVD_JPEG_ENC_RESTART_MARKER_CNTL__RESTART_INTERVAL_MASK 0x0000FFFFL 699a5a25977SLeo Liu #define UVD_JPEG_ENC_RESTART_MARKER_CNTL__RESTART_MARKER_ENABLE_MASK 0x00010000L 700a5a25977SLeo Liu //UVD_JPEG_ENC_ENGINE_CNTL 701a5a25977SLeo Liu #define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT 0x0 702a5a25977SLeo Liu #define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT 0x1 703a5a25977SLeo Liu #define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT 0x2 704a5a25977SLeo Liu #define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT 0x3 705a5a25977SLeo Liu #define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT 0x4 706a5a25977SLeo Liu #define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT 0x9 707a5a25977SLeo Liu #define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK 0x00000001L 708a5a25977SLeo Liu #define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK 0x00000002L 709a5a25977SLeo Liu #define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK 0x00000004L 710a5a25977SLeo Liu #define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK 0x00000008L 711a5a25977SLeo Liu #define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK 0x00000010L 712a5a25977SLeo Liu #define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK 0x00000200L 713a5a25977SLeo Liu //UVD_JPEG_ENC_SCALAR_DST_IMG_INFO 714a5a25977SLeo Liu #define UVD_JPEG_ENC_SCALAR_DST_IMG_INFO__DST_WIDTH__SHIFT 0x0 715a5a25977SLeo Liu #define UVD_JPEG_ENC_SCALAR_DST_IMG_INFO__DST_HEIGHT__SHIFT 0x9 716a5a25977SLeo Liu #define UVD_JPEG_ENC_SCALAR_DST_IMG_INFO__DST_WIDTH_MASK 0x000001FFL 717a5a25977SLeo Liu #define UVD_JPEG_ENC_SCALAR_DST_IMG_INFO__DST_HEIGHT_MASK 0x0003FE00L 718a5a25977SLeo Liu //UVD_JPEG_ENC_HUFF_TBL 719a5a25977SLeo Liu #define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_DATA__SHIFT 0x0 720a5a25977SLeo Liu #define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_ADDR__SHIFT 0x14 721a5a25977SLeo Liu #define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_WRITE__SHIFT 0x1f 722a5a25977SLeo Liu #define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_DATA_MASK 0x000FFFFFL 723a5a25977SLeo Liu #define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_ADDR_MASK 0x1FF00000L 724a5a25977SLeo Liu #define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_WRITE_MASK 0x80000000L 725a5a25977SLeo Liu //UVD_JPEG_ENC_HUFF_TBL_RDATA 726a5a25977SLeo Liu #define UVD_JPEG_ENC_HUFF_TBL_RDATA__HUFF_TBL_RDATA__SHIFT 0x0 727a5a25977SLeo Liu #define UVD_JPEG_ENC_HUFF_TBL_RDATA__HUFF_TBL_RDATA_MASK 0x000FFFFFL 728a5a25977SLeo Liu //UVD_JPEG_ENC_QUANT_TBL 729a5a25977SLeo Liu #define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_READ__SHIFT 0x0 730a5a25977SLeo Liu #define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_ADDR__SHIFT 0x1 731a5a25977SLeo Liu #define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_IDX__SHIFT 0x7 732a5a25977SLeo Liu #define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_READ_MASK 0x00000001L 733a5a25977SLeo Liu #define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_ADDR_MASK 0x0000007EL 734a5a25977SLeo Liu #define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_IDX_MASK 0x00000180L 735a5a25977SLeo Liu //UVD_JPEG_ENC_QUANT_TBL_RDATA 736a5a25977SLeo Liu #define UVD_JPEG_ENC_QUANT_TBL_RDATA__QUANT_TBL_RDATA__SHIFT 0x0 737a5a25977SLeo Liu #define UVD_JPEG_ENC_QUANT_TBL_RDATA__QUANT_TBL_RDATA_MASK 0x0000FFFFL 738a5a25977SLeo Liu //UVD_JPEG_ENC_SCLR_CHROMAU_OFFSET 739a5a25977SLeo Liu #define UVD_JPEG_ENC_SCLR_CHROMAU_OFFSET__SCLR_CHROMAU_OFFSET__SHIFT 0x0 740a5a25977SLeo Liu #define UVD_JPEG_ENC_SCLR_CHROMAU_OFFSET__SCLR_CHROMAU_OFFSET_MASK 0x003FFFFFL 741a5a25977SLeo Liu //UVD_JPEG_ENC_SCLR_CHROMAV_OFFSET 742a5a25977SLeo Liu #define UVD_JPEG_ENC_SCLR_CHROMAV_OFFSET__SCLR_CHROMAV_OFFSET__SHIFT 0x0 743a5a25977SLeo Liu #define UVD_JPEG_ENC_SCLR_CHROMAV_OFFSET__SCLR_CHROMAV_OFFSET_MASK 0x003FFFFFL 744a5a25977SLeo Liu //UVD_JPEG_ENC_SCLR_PITCH 745a5a25977SLeo Liu #define UVD_JPEG_ENC_SCLR_PITCH__PITCH__SHIFT 0x0 746a5a25977SLeo Liu #define UVD_JPEG_ENC_SCLR_PITCH__PITCH_MASK 0x0000003FL 747a5a25977SLeo Liu //UVD_JPEG_ENC_SCRATCH1 748a5a25977SLeo Liu #define UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT 0x0 749a5a25977SLeo Liu #define UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 750a5a25977SLeo Liu 751a5a25977SLeo Liu 752a5a25977SLeo Liu // addressBlock: uvd0_uvd_jpeg_enc_sclk_dec 753a5a25977SLeo Liu //UVD_JPEG_ENC_SPS_INFO 754a5a25977SLeo Liu #define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT__SHIFT 0x0 755a5a25977SLeo Liu #define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT__SHIFT 0x3 756a5a25977SLeo Liu #define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422__SHIFT 0x4 757a5a25977SLeo Liu #define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT_MASK 0x00000007L 758a5a25977SLeo Liu #define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT_MASK 0x00000008L 759a5a25977SLeo Liu #define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422_MASK 0x00000010L 760a5a25977SLeo Liu //UVD_JPEG_ENC_SPS_INFO1 761a5a25977SLeo Liu #define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH__SHIFT 0x0 762a5a25977SLeo Liu #define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT__SHIFT 0x10 763a5a25977SLeo Liu #define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH_MASK 0x0000FFFFL 764a5a25977SLeo Liu #define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT_MASK 0xFFFF0000L 765a5a25977SLeo Liu //UVD_JPEG_ENC_TBL_SIZE 766a5a25977SLeo Liu #define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE__SHIFT 0x6 767a5a25977SLeo Liu #define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE_MASK 0x00000FC0L 768a5a25977SLeo Liu //UVD_JPEG_ENC_TBL_CNTL 769a5a25977SLeo Liu #define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL__SHIFT 0x0 770a5a25977SLeo Liu #define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE__SHIFT 0x1 771a5a25977SLeo Liu #define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE__SHIFT 0x2 772a5a25977SLeo Liu #define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN__SHIFT 0x4 773a5a25977SLeo Liu #define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL_MASK 0x00000001L 774a5a25977SLeo Liu #define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE_MASK 0x00000002L 775a5a25977SLeo Liu #define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE_MASK 0x0000000CL 776a5a25977SLeo Liu #define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN_MASK 0x00000010L 777a5a25977SLeo Liu //UVD_JPEG_ENC_MC_REQ_CNTL 778a5a25977SLeo Liu #define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK__SHIFT 0x0 779a5a25977SLeo Liu #define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK_MASK 0x0000003FL 780a5a25977SLeo Liu //UVD_JPEG_ENC_STATUS 781a5a25977SLeo Liu #define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT 0x0 782a5a25977SLeo Liu #define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT 0x1 783a5a25977SLeo Liu #define UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT 0x2 784a5a25977SLeo Liu #define UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT 0x3 785a5a25977SLeo Liu #define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK 0x00000001L 786a5a25977SLeo Liu #define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK 0x00000002L 787a5a25977SLeo Liu #define UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK 0x00000004L 788a5a25977SLeo Liu #define UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK 0x00000008L 789a5a25977SLeo Liu //UVD_JPEG_ENC_PITCH 790a5a25977SLeo Liu #define UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT 0x0 791a5a25977SLeo Liu #define UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT 0x10 792a5a25977SLeo Liu #define UVD_JPEG_ENC_PITCH__PITCH_Y_MASK 0x00000FFFL 793a5a25977SLeo Liu #define UVD_JPEG_ENC_PITCH__PITCH_UV_MASK 0x0FFF0000L 794a5a25977SLeo Liu //UVD_JPEG_ENC_LUMA_BASE 795a5a25977SLeo Liu #define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT 0x0 796a5a25977SLeo Liu #define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK 0xFFFFFFFFL 797a5a25977SLeo Liu //UVD_JPEG_ENC_CHROMAU_BASE 798a5a25977SLeo Liu #define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT 0x0 799a5a25977SLeo Liu #define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK 0xFFFFFFFFL 800a5a25977SLeo Liu //UVD_JPEG_ENC_CHROMAV_BASE 801a5a25977SLeo Liu #define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT 0x0 802a5a25977SLeo Liu #define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK 0xFFFFFFFFL 803a5a25977SLeo Liu //JPEG_ENC_Y_GFX10_TILING_SURFACE 804a5a25977SLeo Liu #define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 805a5a25977SLeo Liu #define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 806a5a25977SLeo Liu //JPEG_ENC_UV_GFX10_TILING_SURFACE 807a5a25977SLeo Liu #define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 808a5a25977SLeo Liu #define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 809a5a25977SLeo Liu //JPEG_ENC_GFX10_ADDR_CONFIG 810a5a25977SLeo Liu #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 811a5a25977SLeo Liu #define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 812a5a25977SLeo Liu #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 813a5a25977SLeo Liu #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 814a5a25977SLeo Liu #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 815a5a25977SLeo Liu #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 816a5a25977SLeo Liu #define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 817a5a25977SLeo Liu #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 818a5a25977SLeo Liu #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 819a5a25977SLeo Liu #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 820a5a25977SLeo Liu //JPEG_ENC_ADDR_MODE 821a5a25977SLeo Liu #define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 822a5a25977SLeo Liu #define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 823a5a25977SLeo Liu #define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 824a5a25977SLeo Liu #define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 825a5a25977SLeo Liu #define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 826a5a25977SLeo Liu #define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 827a5a25977SLeo Liu //UVD_JPEG_ENC_GPCOM_CMD 828a5a25977SLeo Liu #define UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT 0x1 829a5a25977SLeo Liu #define UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK 0x0000000EL 830a5a25977SLeo Liu //UVD_JPEG_ENC_GPCOM_DATA0 831a5a25977SLeo Liu #define UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT 0x0 832a5a25977SLeo Liu #define UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 833a5a25977SLeo Liu //UVD_JPEG_ENC_GPCOM_DATA1 834a5a25977SLeo Liu #define UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT 0x0 835a5a25977SLeo Liu #define UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 836a5a25977SLeo Liu //UVD_JPEG_TBL_DAT0 837a5a25977SLeo Liu #define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0__SHIFT 0x0 838a5a25977SLeo Liu #define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0_MASK 0xFFFFFFFFL 839a5a25977SLeo Liu //UVD_JPEG_TBL_DAT1 840a5a25977SLeo Liu #define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32__SHIFT 0x0 841a5a25977SLeo Liu #define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32_MASK 0xFFFFFFFFL 842a5a25977SLeo Liu //UVD_JPEG_TBL_IDX 843a5a25977SLeo Liu #define UVD_JPEG_TBL_IDX__TBL_IDX__SHIFT 0x0 844a5a25977SLeo Liu #define UVD_JPEG_TBL_IDX__TBL_IDX_MASK 0x000000FFL 845a5a25977SLeo Liu //UVD_JPEG_ENC_CGC_CNTL 846a5a25977SLeo Liu #define UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT 0x0 847a5a25977SLeo Liu #define UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK 0x00000001L 848a5a25977SLeo Liu //UVD_JPEG_ENC_SCRATCH0 849a5a25977SLeo Liu #define UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 850a5a25977SLeo Liu #define UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 851a5a25977SLeo Liu //UVD_JPEG_ENC_SOFT_RST 852a5a25977SLeo Liu #define UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT 0x0 853a5a25977SLeo Liu #define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT 0x10 854a5a25977SLeo Liu #define UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK 0x00000001L 855a5a25977SLeo Liu #define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 856a5a25977SLeo Liu 857a5a25977SLeo Liu 858a5a25977SLeo Liu // addressBlock: uvd0_uvd_jrbc_dec 859a5a25977SLeo Liu //UVD_JRBC_RB_WPTR 860a5a25977SLeo Liu #define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 861a5a25977SLeo Liu #define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 862a5a25977SLeo Liu //UVD_JRBC_RB_CNTL 863a5a25977SLeo Liu #define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 864a5a25977SLeo Liu #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 865a5a25977SLeo Liu #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 866a5a25977SLeo Liu #define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 867a5a25977SLeo Liu #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 868a5a25977SLeo Liu #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 869a5a25977SLeo Liu //UVD_JRBC_IB_SIZE 870a5a25977SLeo Liu #define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 871a5a25977SLeo Liu #define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 872a5a25977SLeo Liu //UVD_JRBC_URGENT_CNTL 873a5a25977SLeo Liu #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 874a5a25977SLeo Liu #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 875a5a25977SLeo Liu //UVD_JRBC_RB_REF_DATA 876a5a25977SLeo Liu #define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 877a5a25977SLeo Liu #define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 878a5a25977SLeo Liu //UVD_JRBC_RB_COND_RD_TIMER 879a5a25977SLeo Liu #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 880a5a25977SLeo Liu #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 881a5a25977SLeo Liu #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 882a5a25977SLeo Liu #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 883a5a25977SLeo Liu #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 884a5a25977SLeo Liu #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 885a5a25977SLeo Liu #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 886a5a25977SLeo Liu #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 887a5a25977SLeo Liu //UVD_JRBC_SOFT_RESET 888a5a25977SLeo Liu #define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 889a5a25977SLeo Liu #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 890a5a25977SLeo Liu #define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 891a5a25977SLeo Liu #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 892a5a25977SLeo Liu //UVD_JRBC_STATUS 893a5a25977SLeo Liu #define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 894a5a25977SLeo Liu #define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 895a5a25977SLeo Liu #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 896a5a25977SLeo Liu #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 897a5a25977SLeo Liu #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 898a5a25977SLeo Liu #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 899a5a25977SLeo Liu #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 900a5a25977SLeo Liu #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 901a5a25977SLeo Liu #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 902a5a25977SLeo Liu #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 903a5a25977SLeo Liu #define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 904a5a25977SLeo Liu #define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 905a5a25977SLeo Liu #define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 906a5a25977SLeo Liu #define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 907a5a25977SLeo Liu #define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 908a5a25977SLeo Liu #define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 909a5a25977SLeo Liu #define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 910a5a25977SLeo Liu #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 911a5a25977SLeo Liu #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 912a5a25977SLeo Liu #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 913a5a25977SLeo Liu #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 914a5a25977SLeo Liu #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 915a5a25977SLeo Liu #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 916a5a25977SLeo Liu #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 917a5a25977SLeo Liu #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 918a5a25977SLeo Liu #define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 919a5a25977SLeo Liu #define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 920a5a25977SLeo Liu #define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 921a5a25977SLeo Liu #define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 922a5a25977SLeo Liu #define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 923a5a25977SLeo Liu //UVD_JRBC_RB_RPTR 924a5a25977SLeo Liu #define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 925a5a25977SLeo Liu #define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 926a5a25977SLeo Liu //UVD_JRBC_RB_BUF_STATUS 927a5a25977SLeo Liu #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 928a5a25977SLeo Liu #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 929a5a25977SLeo Liu #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 930a5a25977SLeo Liu #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 931a5a25977SLeo Liu #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 932a5a25977SLeo Liu #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 933a5a25977SLeo Liu //UVD_JRBC_IB_BUF_STATUS 934a5a25977SLeo Liu #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 935a5a25977SLeo Liu #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 936a5a25977SLeo Liu #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 937a5a25977SLeo Liu #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 938a5a25977SLeo Liu #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 939a5a25977SLeo Liu #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 940a5a25977SLeo Liu //UVD_JRBC_IB_SIZE_UPDATE 941a5a25977SLeo Liu #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 942a5a25977SLeo Liu #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 943a5a25977SLeo Liu //UVD_JRBC_IB_COND_RD_TIMER 944a5a25977SLeo Liu #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 945a5a25977SLeo Liu #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 946a5a25977SLeo Liu #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 947a5a25977SLeo Liu #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 948a5a25977SLeo Liu #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 949a5a25977SLeo Liu #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 950a5a25977SLeo Liu #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 951a5a25977SLeo Liu #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 952a5a25977SLeo Liu //UVD_JRBC_IB_REF_DATA 953a5a25977SLeo Liu #define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 954a5a25977SLeo Liu #define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 955a5a25977SLeo Liu //UVD_JPEG_PREEMPT_CMD 956a5a25977SLeo Liu #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 957a5a25977SLeo Liu #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 958a5a25977SLeo Liu #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 959a5a25977SLeo Liu #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 960a5a25977SLeo Liu #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 961a5a25977SLeo Liu #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 962a5a25977SLeo Liu //UVD_JPEG_PREEMPT_FENCE_DATA0 963a5a25977SLeo Liu #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 964a5a25977SLeo Liu #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 965a5a25977SLeo Liu //UVD_JPEG_PREEMPT_FENCE_DATA1 966a5a25977SLeo Liu #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 967a5a25977SLeo Liu #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 968a5a25977SLeo Liu //UVD_JRBC_RB_SIZE 969a5a25977SLeo Liu #define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 970a5a25977SLeo Liu #define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 971a5a25977SLeo Liu //UVD_JRBC_SCRATCH0 972a5a25977SLeo Liu #define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 973a5a25977SLeo Liu #define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 974a5a25977SLeo Liu 975a5a25977SLeo Liu 976a5a25977SLeo Liu // addressBlock: uvd0_uvd_jrbc_enc_dec 977a5a25977SLeo Liu //UVD_JRBC_ENC_RB_WPTR 978a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT 0x4 979a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 980a5a25977SLeo Liu //UVD_JRBC_ENC_RB_CNTL 981a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 982a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 983a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 984a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 985a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 986a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 987a5a25977SLeo Liu //UVD_JRBC_ENC_IB_SIZE 988a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT 0x4 989a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 990a5a25977SLeo Liu //UVD_JRBC_ENC_URGENT_CNTL 991a5a25977SLeo Liu #define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 992a5a25977SLeo Liu #define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 993a5a25977SLeo Liu //UVD_JRBC_ENC_RB_REF_DATA 994a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT 0x0 995a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 996a5a25977SLeo Liu //UVD_JRBC_ENC_RB_COND_RD_TIMER 997a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 998a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 999a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 1000a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 1001a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 1002a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 1003a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 1004a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 1005a5a25977SLeo Liu //UVD_JRBC_ENC_SOFT_RESET 1006a5a25977SLeo Liu #define UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT 0x0 1007a5a25977SLeo Liu #define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 1008a5a25977SLeo Liu #define UVD_JRBC_ENC_SOFT_RESET__RESET_MASK 0x00000001L 1009a5a25977SLeo Liu #define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 1010a5a25977SLeo Liu //UVD_JRBC_ENC_STATUS 1011a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT 0x0 1012a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT 0x1 1013a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 1014a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 1015a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 1016a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 1017a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 1018a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 1019a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 1020a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 1021a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 1022a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT 0xb 1023a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 1024a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__INT_EN__SHIFT 0x10 1025a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT 0x11 1026a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK 0x00000001L 1027a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK 0x00000002L 1028a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 1029a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 1030a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 1031a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 1032a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 1033a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 1034a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 1035a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 1036a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 1037a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 1038a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 1039a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__INT_EN_MASK 0x00010000L 1040a5a25977SLeo Liu #define UVD_JRBC_ENC_STATUS__INT_ACK_MASK 0x00020000L 1041a5a25977SLeo Liu //UVD_JRBC_ENC_RB_RPTR 1042a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT 0x4 1043a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 1044a5a25977SLeo Liu //UVD_JRBC_ENC_RB_BUF_STATUS 1045a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 1046a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 1047a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 1048a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 1049a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 1050a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 1051a5a25977SLeo Liu //UVD_JRBC_ENC_IB_BUF_STATUS 1052a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 1053a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 1054a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 1055a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 1056a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 1057a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 1058a5a25977SLeo Liu //UVD_JRBC_ENC_IB_SIZE_UPDATE 1059a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 1060a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 1061a5a25977SLeo Liu //UVD_JRBC_ENC_IB_COND_RD_TIMER 1062a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 1063a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 1064a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 1065a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 1066a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 1067a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 1068a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 1069a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 1070a5a25977SLeo Liu //UVD_JRBC_ENC_IB_REF_DATA 1071a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT 0x0 1072a5a25977SLeo Liu #define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 1073a5a25977SLeo Liu //UVD_JPEG_ENC_PREEMPT_CMD 1074a5a25977SLeo Liu #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 1075a5a25977SLeo Liu #define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 1076a5a25977SLeo Liu #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 1077a5a25977SLeo Liu #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 1078a5a25977SLeo Liu #define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 1079a5a25977SLeo Liu #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 1080a5a25977SLeo Liu //UVD_JPEG_ENC_PREEMPT_FENCE_DATA0 1081a5a25977SLeo Liu #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 1082a5a25977SLeo Liu #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 1083a5a25977SLeo Liu //UVD_JPEG_ENC_PREEMPT_FENCE_DATA1 1084a5a25977SLeo Liu #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 1085a5a25977SLeo Liu #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 1086a5a25977SLeo Liu //UVD_JRBC_ENC_RB_SIZE 1087a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT 0x4 1088a5a25977SLeo Liu #define UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 1089a5a25977SLeo Liu //UVD_JRBC_ENC_SCRATCH0 1090a5a25977SLeo Liu #define UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 1091a5a25977SLeo Liu #define UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 1092a5a25977SLeo Liu 1093a5a25977SLeo Liu 1094a5a25977SLeo Liu // addressBlock: uvd0_uvd_jmi_dec 1095a5a25977SLeo Liu //UVD_JADP_MCIF_URGENT_CTRL 1096a5a25977SLeo Liu #define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK__SHIFT 0x0 1097a5a25977SLeo Liu #define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK__SHIFT 0x6 1098a5a25977SLeo Liu #define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER__SHIFT 0xb 1099a5a25977SLeo Liu #define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP__SHIFT 0x11 1100a5a25977SLeo Liu #define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP__SHIFT 0x15 1101a5a25977SLeo Liu #define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN__SHIFT 0x19 1102a5a25977SLeo Liu #define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN__SHIFT 0x1a 1103a5a25977SLeo Liu #define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK_MASK 0x0000003FL 1104a5a25977SLeo Liu #define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK_MASK 0x000007C0L 1105a5a25977SLeo Liu #define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER_MASK 0x0001F800L 1106a5a25977SLeo Liu #define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP_MASK 0x001E0000L 1107a5a25977SLeo Liu #define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP_MASK 0x01E00000L 1108a5a25977SLeo Liu #define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN_MASK 0x02000000L 1109a5a25977SLeo Liu #define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN_MASK 0x04000000L 1110a5a25977SLeo Liu //UVD_JMI_URGENT_CTRL 1111a5a25977SLeo Liu #define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 1112a5a25977SLeo Liu #define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x4 1113a5a25977SLeo Liu #define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x10 1114a5a25977SLeo Liu #define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0x14 1115a5a25977SLeo Liu #define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 1116a5a25977SLeo Liu #define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x000000F0L 1117a5a25977SLeo Liu #define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00010000L 1118a5a25977SLeo Liu #define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00F00000L 1119a5a25977SLeo Liu //UVD_JPEG_DEC_PF_CTRL 1120a5a25977SLeo Liu #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 1121a5a25977SLeo Liu #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 1122a5a25977SLeo Liu #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L 1123a5a25977SLeo Liu #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L 1124a5a25977SLeo Liu //UVD_JPEG_ENC_PF_CTRL 1125a5a25977SLeo Liu #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS__SHIFT 0x0 1126a5a25977SLeo Liu #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING__SHIFT 0x1 1127a5a25977SLeo Liu #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS_MASK 0x00000001L 1128a5a25977SLeo Liu #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING_MASK 0x00000002L 1129a5a25977SLeo Liu //UVD_JMI_CTRL 1130a5a25977SLeo Liu #define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0 1131a5a25977SLeo Liu #define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1 1132a5a25977SLeo Liu #define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2 1133a5a25977SLeo Liu #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8 1134a5a25977SLeo Liu #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10 1135a5a25977SLeo Liu #define UVD_JMI_CTRL__CRC_RESET__SHIFT 0x18 1136a5a25977SLeo Liu #define UVD_JMI_CTRL__CRC_SEL__SHIFT 0x19 1137a5a25977SLeo Liu #define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L 1138a5a25977SLeo Liu #define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L 1139a5a25977SLeo Liu #define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L 1140a5a25977SLeo Liu #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L 1141a5a25977SLeo Liu #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L 1142a5a25977SLeo Liu #define UVD_JMI_CTRL__CRC_RESET_MASK 0x01000000L 1143a5a25977SLeo Liu #define UVD_JMI_CTRL__CRC_SEL_MASK 0x1E000000L 1144a5a25977SLeo Liu //UVD_LMI_JRBC_CTRL 1145a5a25977SLeo Liu #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1146a5a25977SLeo Liu #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1147a5a25977SLeo Liu #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 1148a5a25977SLeo Liu #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 1149a5a25977SLeo Liu #define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 1150a5a25977SLeo Liu #define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 1151a5a25977SLeo Liu #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1152a5a25977SLeo Liu #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1153a5a25977SLeo Liu #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1154a5a25977SLeo Liu #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1155a5a25977SLeo Liu #define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 1156a5a25977SLeo Liu #define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 1157a5a25977SLeo Liu //UVD_LMI_JPEG_CTRL 1158a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1159a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1160a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 1161a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 1162a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 1163a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 1164a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1165a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1166a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1167a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1168a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 1169a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 1170a5a25977SLeo Liu //UVD_JMI_EJRBC_CTRL 1171a5a25977SLeo Liu #define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1172a5a25977SLeo Liu #define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1173a5a25977SLeo Liu #define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 1174a5a25977SLeo Liu #define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 1175a5a25977SLeo Liu #define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT 0x14 1176a5a25977SLeo Liu #define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT 0x16 1177a5a25977SLeo Liu #define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1178a5a25977SLeo Liu #define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1179a5a25977SLeo Liu #define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1180a5a25977SLeo Liu #define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1181a5a25977SLeo Liu #define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK 0x00300000L 1182a5a25977SLeo Liu #define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK 0x00C00000L 1183a5a25977SLeo Liu //UVD_LMI_EJPEG_CTRL 1184a5a25977SLeo Liu #define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1185a5a25977SLeo Liu #define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1186a5a25977SLeo Liu #define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 1187a5a25977SLeo Liu #define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 1188a5a25977SLeo Liu #define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT 0x14 1189a5a25977SLeo Liu #define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT 0x16 1190a5a25977SLeo Liu #define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1191a5a25977SLeo Liu #define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1192a5a25977SLeo Liu #define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1193a5a25977SLeo Liu #define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1194a5a25977SLeo Liu #define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK 0x00300000L 1195a5a25977SLeo Liu #define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK 0x00C00000L 1196a5a25977SLeo Liu //UVD_JMI_SCALER_CTRL 1197a5a25977SLeo Liu #define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1198a5a25977SLeo Liu #define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1199a5a25977SLeo Liu #define UVD_JMI_SCALER_CTRL__RD_MAX_BURST__SHIFT 0x4 1200a5a25977SLeo Liu #define UVD_JMI_SCALER_CTRL__WR_MAX_BURST__SHIFT 0x8 1201a5a25977SLeo Liu #define UVD_JMI_SCALER_CTRL__RD_SWAP__SHIFT 0x14 1202a5a25977SLeo Liu #define UVD_JMI_SCALER_CTRL__WR_SWAP__SHIFT 0x16 1203a5a25977SLeo Liu #define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1204a5a25977SLeo Liu #define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1205a5a25977SLeo Liu #define UVD_JMI_SCALER_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1206a5a25977SLeo Liu #define UVD_JMI_SCALER_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1207a5a25977SLeo Liu #define UVD_JMI_SCALER_CTRL__RD_SWAP_MASK 0x00300000L 1208a5a25977SLeo Liu #define UVD_JMI_SCALER_CTRL__WR_SWAP_MASK 0x00C00000L 1209a5a25977SLeo Liu //JPEG_LMI_DROP 1210a5a25977SLeo Liu #define JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 1211a5a25977SLeo Liu #define JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 1212a5a25977SLeo Liu #define JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 1213a5a25977SLeo Liu #define JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 1214a5a25977SLeo Liu #define JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L 1215a5a25977SLeo Liu #define JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L 1216a5a25977SLeo Liu #define JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L 1217a5a25977SLeo Liu #define JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L 1218a5a25977SLeo Liu //UVD_JMI_EJPEG_DROP 1219a5a25977SLeo Liu #define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP__SHIFT 0x0 1220a5a25977SLeo Liu #define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP__SHIFT 0x1 1221a5a25977SLeo Liu #define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP__SHIFT 0x2 1222a5a25977SLeo Liu #define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP__SHIFT 0x3 1223a5a25977SLeo Liu #define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP__SHIFT 0x4 1224a5a25977SLeo Liu #define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP__SHIFT 0x5 1225a5a25977SLeo Liu #define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP_MASK 0x00000001L 1226a5a25977SLeo Liu #define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP_MASK 0x00000002L 1227a5a25977SLeo Liu #define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP_MASK 0x00000004L 1228a5a25977SLeo Liu #define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP_MASK 0x00000008L 1229a5a25977SLeo Liu #define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP_MASK 0x00000010L 1230a5a25977SLeo Liu #define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP_MASK 0x00000020L 1231a5a25977SLeo Liu //JPEG_MEMCHECK_CLAMPING 1232a5a25977SLeo Liu #define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0xd 1233a5a25977SLeo Liu #define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN__SHIFT 0xe 1234a5a25977SLeo Liu #define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x16 1235a5a25977SLeo Liu #define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN__SHIFT 0x17 1236a5a25977SLeo Liu #define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x19 1237a5a25977SLeo Liu #define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1a 1238a5a25977SLeo Liu #define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f 1239a5a25977SLeo Liu #define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00002000L 1240a5a25977SLeo Liu #define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN_MASK 0x00004000L 1241a5a25977SLeo Liu #define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00400000L 1242a5a25977SLeo Liu #define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN_MASK 0x00800000L 1243a5a25977SLeo Liu #define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x02000000L 1244a5a25977SLeo Liu #define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x04000000L 1245a5a25977SLeo Liu #define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L 1246a5a25977SLeo Liu //UVD_JMI_EJPEG_MEMCHECK_CLAMPING 1247a5a25977SLeo Liu #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x0 1248a5a25977SLeo Liu #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1 1249a5a25977SLeo Liu #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x2 1250a5a25977SLeo Liu #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0x3 1251a5a25977SLeo Liu #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN__SHIFT 0x4 1252a5a25977SLeo Liu #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN__SHIFT 0x5 1253a5a25977SLeo Liu #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f 1254a5a25977SLeo Liu #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x00000001L 1255a5a25977SLeo Liu #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x00000002L 1256a5a25977SLeo Liu #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00000004L 1257a5a25977SLeo Liu #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00000008L 1258a5a25977SLeo Liu #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN_MASK 0x00000010L 1259a5a25977SLeo Liu #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN_MASK 0x00000020L 1260a5a25977SLeo Liu #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L 1261a5a25977SLeo Liu //UVD_LMI_JRBC_IB_VMID 1262a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1263a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1264a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1265a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1266a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1267a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1268a5a25977SLeo Liu //UVD_LMI_JRBC_RB_VMID 1269a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1270a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1271a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1272a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1273a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1274a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1275a5a25977SLeo Liu //UVD_LMI_JPEG_VMID 1276a5a25977SLeo Liu #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 1277a5a25977SLeo Liu #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 1278a5a25977SLeo Liu #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 1279a5a25977SLeo Liu #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 1280a5a25977SLeo Liu #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 1281a5a25977SLeo Liu #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 1282a5a25977SLeo Liu //UVD_JMI_ENC_JRBC_IB_VMID 1283a5a25977SLeo Liu #define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1284a5a25977SLeo Liu #define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1285a5a25977SLeo Liu #define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1286a5a25977SLeo Liu #define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1287a5a25977SLeo Liu #define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1288a5a25977SLeo Liu #define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1289a5a25977SLeo Liu //UVD_JMI_ENC_JRBC_RB_VMID 1290a5a25977SLeo Liu #define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1291a5a25977SLeo Liu #define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1292a5a25977SLeo Liu #define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1293a5a25977SLeo Liu #define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1294a5a25977SLeo Liu #define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1295a5a25977SLeo Liu #define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1296a5a25977SLeo Liu //UVD_JMI_ENC_JPEG_VMID 1297a5a25977SLeo Liu #define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT 0x0 1298a5a25977SLeo Liu #define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5 1299a5a25977SLeo Liu #define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa 1300a5a25977SLeo Liu #define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT 0xf 1301a5a25977SLeo Liu #define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT 0x13 1302a5a25977SLeo Liu #define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT 0x17 1303a5a25977SLeo Liu #define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK 0x0000000FL 1304a5a25977SLeo Liu #define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK 0x000001E0L 1305a5a25977SLeo Liu #define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK 0x00003C00L 1306a5a25977SLeo Liu #define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK 0x00078000L 1307a5a25977SLeo Liu #define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK 0x00780000L 1308a5a25977SLeo Liu #define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK 0x07800000L 1309a5a25977SLeo Liu //JPEG_MEMCHECK_SAFE_ADDR 1310a5a25977SLeo Liu #define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR__SHIFT 0x0 1311a5a25977SLeo Liu #define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR_MASK 0xFFFFFFFFL 1312a5a25977SLeo Liu //JPEG_MEMCHECK_SAFE_ADDR_64BIT 1313a5a25977SLeo Liu #define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT__SHIFT 0x0 1314a5a25977SLeo Liu #define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT_MASK 0xFFFFFFFFL 1315a5a25977SLeo Liu //UVD_JMI_LAT_CTRL 1316a5a25977SLeo Liu #define UVD_JMI_LAT_CTRL__SCALE__SHIFT 0x0 1317a5a25977SLeo Liu #define UVD_JMI_LAT_CTRL__MAX_START__SHIFT 0x8 1318a5a25977SLeo Liu #define UVD_JMI_LAT_CTRL__MIN_START__SHIFT 0x9 1319a5a25977SLeo Liu #define UVD_JMI_LAT_CTRL__AVG_START__SHIFT 0xa 1320a5a25977SLeo Liu #define UVD_JMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 1321a5a25977SLeo Liu #define UVD_JMI_LAT_CTRL__SKIP__SHIFT 0x10 1322a5a25977SLeo Liu #define UVD_JMI_LAT_CTRL__SCALE_MASK 0x000000FFL 1323a5a25977SLeo Liu #define UVD_JMI_LAT_CTRL__MAX_START_MASK 0x00000100L 1324a5a25977SLeo Liu #define UVD_JMI_LAT_CTRL__MIN_START_MASK 0x00000200L 1325a5a25977SLeo Liu #define UVD_JMI_LAT_CTRL__AVG_START_MASK 0x00000400L 1326a5a25977SLeo Liu #define UVD_JMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 1327a5a25977SLeo Liu #define UVD_JMI_LAT_CTRL__SKIP_MASK 0x000F0000L 1328a5a25977SLeo Liu //UVD_JMI_LAT_CNTR 1329a5a25977SLeo Liu #define UVD_JMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 1330a5a25977SLeo Liu #define UVD_JMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 1331a5a25977SLeo Liu #define UVD_JMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 1332a5a25977SLeo Liu #define UVD_JMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 1333a5a25977SLeo Liu //UVD_JMI_AVG_LAT_CNTR 1334a5a25977SLeo Liu #define UVD_JMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 1335a5a25977SLeo Liu #define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 1336a5a25977SLeo Liu #define UVD_JMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 1337a5a25977SLeo Liu #define UVD_JMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 1338a5a25977SLeo Liu #define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 1339a5a25977SLeo Liu #define UVD_JMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 1340a5a25977SLeo Liu //UVD_JMI_PERFMON_CTRL 1341a5a25977SLeo Liu #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 1342a5a25977SLeo Liu #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 1343a5a25977SLeo Liu #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 1344a5a25977SLeo Liu #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00000F00L 1345a5a25977SLeo Liu //UVD_JMI_PERFMON_COUNT_LO 1346a5a25977SLeo Liu #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 1347a5a25977SLeo Liu #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 1348a5a25977SLeo Liu //UVD_JMI_PERFMON_COUNT_HI 1349a5a25977SLeo Liu #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 1350a5a25977SLeo Liu #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 1351a5a25977SLeo Liu //UVD_JMI_CLEAN_STATUS 1352a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN__SHIFT 0x0 1353a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW__SHIFT 0x1 1354a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN__SHIFT 0x2 1355a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW__SHIFT 0x3 1356a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN__SHIFT 0x4 1357a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN__SHIFT 0x5 1358a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN__SHIFT 0x6 1359a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN__SHIFT 0x7 1360a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN__SHIFT 0x8 1361a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN__SHIFT 0x9 1362a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN__SHIFT 0xa 1363a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN__SHIFT 0xb 1364a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN__SHIFT 0xc 1365a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN__SHIFT 0xd 1366a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING__SHIFT 0xe 1367a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN__SHIFT 0xf 1368a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN__SHIFT 0x10 1369a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_MASK 0x00000001L 1370a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW_MASK 0x00000002L 1371a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_MASK 0x00000004L 1372a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW_MASK 0x00000008L 1373a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN_MASK 0x00000010L 1374a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN_MASK 0x00000020L 1375a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN_MASK 0x00000040L 1376a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN_MASK 0x00000080L 1377a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN_MASK 0x00000100L 1378a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN_MASK 0x00000200L 1379a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN_MASK 0x00000400L 1380a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN_MASK 0x00000800L 1381a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN_MASK 0x00001000L 1382a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN_MASK 0x00002000L 1383a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING_MASK 0x00004000L 1384a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN_MASK 0x00008000L 1385a5a25977SLeo Liu #define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN_MASK 0x00010000L 1386a5a25977SLeo Liu //UVD_LMI_JPEG_READ_64BIT_BAR_LOW 1387a5a25977SLeo Liu #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1388a5a25977SLeo Liu #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1389a5a25977SLeo Liu //UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 1390a5a25977SLeo Liu #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1391a5a25977SLeo Liu #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1392a5a25977SLeo Liu //UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 1393a5a25977SLeo Liu #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1394a5a25977SLeo Liu #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1395a5a25977SLeo Liu //UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 1396a5a25977SLeo Liu #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1397a5a25977SLeo Liu #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1398a5a25977SLeo Liu //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1399a5a25977SLeo Liu #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1400a5a25977SLeo Liu #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1401a5a25977SLeo Liu //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1402a5a25977SLeo Liu #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1403a5a25977SLeo Liu #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1404a5a25977SLeo Liu //UVD_LMI_JRBC_RB_64BIT_BAR_LOW 1405a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1406a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1407a5a25977SLeo Liu //UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 1408a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1409a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1410a5a25977SLeo Liu //UVD_LMI_JRBC_IB_64BIT_BAR_LOW 1411a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1412a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1413a5a25977SLeo Liu //UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 1414a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1415a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1416a5a25977SLeo Liu //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 1417a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1418a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1419a5a25977SLeo Liu //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 1420a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1421a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1422a5a25977SLeo Liu //UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 1423a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1424a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1425a5a25977SLeo Liu //UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 1426a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1427a5a25977SLeo Liu #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1428a5a25977SLeo Liu //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 1429a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1430a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1431a5a25977SLeo Liu //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 1432a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1433a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1434a5a25977SLeo Liu //UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 1435a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1436a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1437a5a25977SLeo Liu //UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 1438a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1439a5a25977SLeo Liu #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1440a5a25977SLeo Liu //UVD_JMI_PEL_RD_64BIT_BAR_LOW 1441a5a25977SLeo Liu #define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1442a5a25977SLeo Liu #define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1443a5a25977SLeo Liu //UVD_JMI_PEL_RD_64BIT_BAR_HIGH 1444a5a25977SLeo Liu #define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1445a5a25977SLeo Liu #define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1446a5a25977SLeo Liu //UVD_JMI_BS_WR_64BIT_BAR_LOW 1447a5a25977SLeo Liu #define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1448a5a25977SLeo Liu #define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1449a5a25977SLeo Liu //UVD_JMI_BS_WR_64BIT_BAR_HIGH 1450a5a25977SLeo Liu #define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1451a5a25977SLeo Liu #define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1452a5a25977SLeo Liu //UVD_JMI_SCALAR_RD_64BIT_BAR_LOW 1453a5a25977SLeo Liu #define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1454a5a25977SLeo Liu #define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1455a5a25977SLeo Liu //UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH 1456a5a25977SLeo Liu #define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1457a5a25977SLeo Liu #define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1458a5a25977SLeo Liu //UVD_JMI_SCALAR_WR_64BIT_BAR_LOW 1459a5a25977SLeo Liu #define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1460a5a25977SLeo Liu #define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1461a5a25977SLeo Liu //UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH 1462a5a25977SLeo Liu #define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1463a5a25977SLeo Liu #define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1464a5a25977SLeo Liu //UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1465a5a25977SLeo Liu #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1466a5a25977SLeo Liu #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1467a5a25977SLeo Liu //UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1468a5a25977SLeo Liu #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1469a5a25977SLeo Liu #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1470a5a25977SLeo Liu //UVD_LMI_EJRBC_RB_64BIT_BAR_LOW 1471a5a25977SLeo Liu #define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1472a5a25977SLeo Liu #define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1473a5a25977SLeo Liu //UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 1474a5a25977SLeo Liu #define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1475a5a25977SLeo Liu #define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1476a5a25977SLeo Liu //UVD_LMI_EJRBC_IB_64BIT_BAR_LOW 1477a5a25977SLeo Liu #define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1478a5a25977SLeo Liu #define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1479a5a25977SLeo Liu //UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 1480a5a25977SLeo Liu #define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1481a5a25977SLeo Liu #define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1482a5a25977SLeo Liu //UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 1483a5a25977SLeo Liu #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1484a5a25977SLeo Liu #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1485a5a25977SLeo Liu //UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 1486a5a25977SLeo Liu #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1487a5a25977SLeo Liu #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1488a5a25977SLeo Liu //UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 1489a5a25977SLeo Liu #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1490a5a25977SLeo Liu #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1491a5a25977SLeo Liu //UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 1492a5a25977SLeo Liu #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1493a5a25977SLeo Liu #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1494a5a25977SLeo Liu //UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 1495a5a25977SLeo Liu #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1496a5a25977SLeo Liu #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1497a5a25977SLeo Liu //UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 1498a5a25977SLeo Liu #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1499a5a25977SLeo Liu #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1500a5a25977SLeo Liu //UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 1501a5a25977SLeo Liu #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1502a5a25977SLeo Liu #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1503a5a25977SLeo Liu //UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 1504a5a25977SLeo Liu #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1505a5a25977SLeo Liu #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1506a5a25977SLeo Liu //UVD_LMI_JPEG_PREEMPT_VMID 1507a5a25977SLeo Liu #define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1508a5a25977SLeo Liu #define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1509a5a25977SLeo Liu //UVD_LMI_ENC_JPEG_PREEMPT_VMID 1510a5a25977SLeo Liu #define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1511a5a25977SLeo Liu #define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1512a5a25977SLeo Liu //UVD_LMI_JPEG2_VMID 1513a5a25977SLeo Liu #define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT 0x0 1514a5a25977SLeo Liu #define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT 0x4 1515a5a25977SLeo Liu #define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK 0x0000000FL 1516a5a25977SLeo Liu #define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK 0x000000F0L 1517a5a25977SLeo Liu //UVD_LMI_JPEG2_READ_64BIT_BAR_LOW 1518a5a25977SLeo Liu #define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1519a5a25977SLeo Liu #define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1520a5a25977SLeo Liu //UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 1521a5a25977SLeo Liu #define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1522a5a25977SLeo Liu #define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1523a5a25977SLeo Liu //UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 1524a5a25977SLeo Liu #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1525a5a25977SLeo Liu #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1526a5a25977SLeo Liu //UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 1527a5a25977SLeo Liu #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1528a5a25977SLeo Liu #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1529a5a25977SLeo Liu //UVD_LMI_JPEG_CTRL2 1530a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT 0x0 1531a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT 0x1 1532a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT 0x4 1533a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT 0x8 1534a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT 0x14 1535a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT 0x16 1536a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK 0x00000001L 1537a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK 0x00000002L 1538a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK 0x000000F0L 1539a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK 0x00000F00L 1540a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK 0x00300000L 1541a5a25977SLeo Liu #define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK 0x00C00000L 1542a5a25977SLeo Liu //UVD_JMI_DEC_SWAP_CNTL 1543a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1544a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1545a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1546a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1547a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1548a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1549a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1550a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 1551a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 1552a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1553a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1554a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1555a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1556a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1557a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1558a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1559a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 1560a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 1561a5a25977SLeo Liu //UVD_JMI_ENC_SWAP_CNTL 1562a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1563a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1564a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1565a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1566a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1567a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1568a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1569a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT 0xe 1570a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT 0x10 1571a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT 0x12 1572a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT 0x14 1573a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT 0x16 1574a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1575a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1576a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1577a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1578a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1579a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1580a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1581a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK 0x0000C000L 1582a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK 0x00030000L 1583a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK 0x000C0000L 1584a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK 0x00300000L 1585a5a25977SLeo Liu #define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK 0x00C00000L 1586a5a25977SLeo Liu //UVD_JMI_CNTL 1587a5a25977SLeo Liu #define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0 1588a5a25977SLeo Liu #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8 1589a5a25977SLeo Liu #define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L 1590a5a25977SLeo Liu #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L 1591a5a25977SLeo Liu //UVD_JMI_ATOMIC_CNTL 1592a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 1593a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 1594a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 1595a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 1596a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 1597a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb 1598a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L 1599a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL 1600a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L 1601a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L 1602a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L 1603a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L 1604a5a25977SLeo Liu //UVD_JMI_ATOMIC_CNTL2 1605a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 1606a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 1607a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L 1608a5a25977SLeo Liu #define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L 1609a5a25977SLeo Liu //UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 1610a5a25977SLeo Liu #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1611a5a25977SLeo Liu #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1612a5a25977SLeo Liu //UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 1613a5a25977SLeo Liu #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1614a5a25977SLeo Liu #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1615a5a25977SLeo Liu //UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW 1616a5a25977SLeo Liu #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1617a5a25977SLeo Liu #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1618a5a25977SLeo Liu //UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH 1619a5a25977SLeo Liu #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1620a5a25977SLeo Liu #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1621a5a25977SLeo Liu //JPEG2_LMI_DROP 1622a5a25977SLeo Liu #define JPEG2_LMI_DROP__JPEG2_WR_DROP__SHIFT 0x0 1623a5a25977SLeo Liu #define JPEG2_LMI_DROP__JPEG2_RD_DROP__SHIFT 0x1 1624a5a25977SLeo Liu #define JPEG2_LMI_DROP__JPEG2_WR_DROP_MASK 0x00000001L 1625a5a25977SLeo Liu #define JPEG2_LMI_DROP__JPEG2_RD_DROP_MASK 0x00000002L 1626a5a25977SLeo Liu //UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 1627a5a25977SLeo Liu #define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1628a5a25977SLeo Liu #define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1629a5a25977SLeo Liu //UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 1630a5a25977SLeo Liu #define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1631a5a25977SLeo Liu #define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1632a5a25977SLeo Liu //UVD_JMI_DEC_SWAP_CNTL2 1633a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT 0x0 1634a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT 0x2 1635a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK 0x00000003L 1636a5a25977SLeo Liu #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK 0x0000000CL 1637a5a25977SLeo Liu //UVD_JPEG_DEC2_PF_CTRL 1638a5a25977SLeo Liu #define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_HANDLING_DIS__SHIFT 0x0 1639a5a25977SLeo Liu #define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_SW_GATING__SHIFT 0x1 1640a5a25977SLeo Liu #define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_HANDLING_DIS_MASK 0x00000001L 1641a5a25977SLeo Liu #define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_SW_GATING_MASK 0x00000002L 1642a5a25977SLeo Liu 1643a5a25977SLeo Liu 1644a5a25977SLeo Liu // addressBlock: uvd0_uvd_jpeg_common_dec 1645a5a25977SLeo Liu //JPEG_SOFT_RESET_STATUS 1646a5a25977SLeo Liu #define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT 0x0 1647a5a25977SLeo Liu #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x1 1648a5a25977SLeo Liu #define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT 0x2 1649a5a25977SLeo Liu #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x3 1650a5a25977SLeo Liu #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x4 1651a5a25977SLeo Liu #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5 1652a5a25977SLeo Liu #define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK 0x00000001L 1653a5a25977SLeo Liu #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000002L 1654a5a25977SLeo Liu #define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK 0x00000004L 1655a5a25977SLeo Liu #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00000008L 1656a5a25977SLeo Liu #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00000010L 1657a5a25977SLeo Liu #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x00000020L 1658a5a25977SLeo Liu //JPEG_SYS_INT_EN 1659a5a25977SLeo Liu #define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT 0x0 1660a5a25977SLeo Liu #define JPEG_SYS_INT_EN__DJRBC__SHIFT 0x1 1661a5a25977SLeo Liu #define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT 0x2 1662a5a25977SLeo Liu #define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT 0x3 1663a5a25977SLeo Liu #define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT 0x4 1664a5a25977SLeo Liu #define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5 1665a5a25977SLeo Liu #define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT 0x6 1666a5a25977SLeo Liu #define JPEG_SYS_INT_EN__DJPEG2_PF_RPT__SHIFT 0x7 1667a5a25977SLeo Liu #define JPEG_SYS_INT_EN__DJPEG_CORE_MASK 0x00000001L 1668a5a25977SLeo Liu #define JPEG_SYS_INT_EN__DJRBC_MASK 0x00000002L 1669a5a25977SLeo Liu #define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK 0x00000004L 1670a5a25977SLeo Liu #define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK 0x00000008L 1671a5a25977SLeo Liu #define JPEG_SYS_INT_EN__EJPEG_CORE_MASK 0x00000010L 1672a5a25977SLeo Liu #define JPEG_SYS_INT_EN__EJRBC_MASK 0x00000020L 1673a5a25977SLeo Liu #define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK 0x00000040L 1674a5a25977SLeo Liu #define JPEG_SYS_INT_EN__DJPEG2_PF_RPT_MASK 0x00000080L 1675a5a25977SLeo Liu //JPEG_SYS_INT_STATUS 1676a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT 0x0 1677a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__DJRBC__SHIFT 0x1 1678a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT 0x2 1679a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT 0x3 1680a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT 0x4 1681a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5 1682a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT 0x6 1683a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__DJPEG2_PF_RPT__SHIFT 0x7 1684a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK 0x00000001L 1685a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__DJRBC_MASK 0x00000002L 1686a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK 0x00000004L 1687a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK 0x00000008L 1688a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK 0x00000010L 1689a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__EJRBC_MASK 0x00000020L 1690a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK 0x00000040L 1691a5a25977SLeo Liu #define JPEG_SYS_INT_STATUS__DJPEG2_PF_RPT_MASK 0x00000080L 1692a5a25977SLeo Liu //JPEG_SYS_INT_ACK 1693a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT 0x0 1694a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__DJRBC__SHIFT 0x1 1695a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT 0x2 1696a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT 0x3 1697a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT 0x4 1698a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5 1699a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT 0x6 1700a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__DJPEG2_PF_RPT__SHIFT 0x7 1701a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK 0x00000001L 1702a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__DJRBC_MASK 0x00000002L 1703a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK 0x00000004L 1704a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK 0x00000008L 1705a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK 0x00000010L 1706a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__EJRBC_MASK 0x00000020L 1707a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK 0x00000040L 1708a5a25977SLeo Liu #define JPEG_SYS_INT_ACK__DJPEG2_PF_RPT_MASK 0x00000080L 1709a5a25977SLeo Liu //JPEG_MEMCHECK_SYS_INT_EN 1710a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN__SHIFT 0x0 1711a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN__SHIFT 0x1 1712a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN__SHIFT 0x2 1713a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN__SHIFT 0x3 1714a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN__SHIFT 0x4 1715a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN__SHIFT 0x5 1716a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN__SHIFT 0x6 1717a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN__SHIFT 0x7 1718a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN__SHIFT 0x8 1719a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN__SHIFT 0x9 1720a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN__SHIFT 0xa 1721a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN__SHIFT 0xb 1722a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN_MASK 0x00000001L 1723a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN_MASK 0x00000002L 1724a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN_MASK 0x00000004L 1725a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN_MASK 0x00000008L 1726a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN_MASK 0x00000010L 1727a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN_MASK 0x00000020L 1728a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN_MASK 0x00000040L 1729a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN_MASK 0x00000080L 1730a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN_MASK 0x00000100L 1731a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN_MASK 0x00000200L 1732a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN_MASK 0x00000400L 1733a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN_MASK 0x00000800L 1734a5a25977SLeo Liu //JPEG_MEMCHECK_SYS_INT_STAT 1735a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR__SHIFT 0x0 1736a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR__SHIFT 0x1 1737a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR__SHIFT 0x2 1738a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR__SHIFT 0x3 1739a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR__SHIFT 0x4 1740a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR__SHIFT 0x5 1741a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR__SHIFT 0x6 1742a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR__SHIFT 0x7 1743a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR__SHIFT 0x8 1744a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR__SHIFT 0x9 1745a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR__SHIFT 0xa 1746a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR__SHIFT 0xb 1747a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR__SHIFT 0xc 1748a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR__SHIFT 0xd 1749a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR__SHIFT 0xe 1750a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR__SHIFT 0xf 1751a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR__SHIFT 0x10 1752a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR__SHIFT 0x11 1753a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR__SHIFT 0x12 1754a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR__SHIFT 0x13 1755a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR__SHIFT 0x14 1756a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR__SHIFT 0x15 1757a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR__SHIFT 0x16 1758a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR__SHIFT 0x17 1759a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR_MASK 0x00000001L 1760a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR_MASK 0x00000002L 1761a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR_MASK 0x00000004L 1762a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR_MASK 0x00000008L 1763a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR_MASK 0x00000010L 1764a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR_MASK 0x00000020L 1765a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR_MASK 0x00000040L 1766a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR_MASK 0x00000080L 1767a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR_MASK 0x00000100L 1768a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR_MASK 0x00000200L 1769a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR_MASK 0x00000400L 1770a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR_MASK 0x00000800L 1771a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR_MASK 0x00001000L 1772a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR_MASK 0x00002000L 1773a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR_MASK 0x00004000L 1774a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR_MASK 0x00008000L 1775a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR_MASK 0x00010000L 1776a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR_MASK 0x00020000L 1777a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR_MASK 0x00040000L 1778a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR_MASK 0x00080000L 1779a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR_MASK 0x00100000L 1780a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR_MASK 0x00200000L 1781a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR_MASK 0x00400000L 1782a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR_MASK 0x00800000L 1783a5a25977SLeo Liu //JPEG_MEMCHECK_SYS_INT_ACK 1784a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR__SHIFT 0x0 1785a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR__SHIFT 0x1 1786a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR__SHIFT 0x2 1787a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR__SHIFT 0x3 1788a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR__SHIFT 0x4 1789a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR__SHIFT 0x5 1790a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR__SHIFT 0x6 1791a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR__SHIFT 0x7 1792a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR__SHIFT 0x8 1793a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR__SHIFT 0x9 1794a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR__SHIFT 0xa 1795a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR__SHIFT 0xb 1796a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR__SHIFT 0xc 1797a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR__SHIFT 0xd 1798a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR__SHIFT 0xe 1799a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR__SHIFT 0xf 1800a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR__SHIFT 0x10 1801a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR__SHIFT 0x11 1802a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR__SHIFT 0x12 1803a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR__SHIFT 0x13 1804a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR__SHIFT 0x14 1805a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR__SHIFT 0x15 1806a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR__SHIFT 0x16 1807a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR__SHIFT 0x17 1808a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR_MASK 0x00000001L 1809a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR_MASK 0x00000002L 1810a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR_MASK 0x00000004L 1811a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR_MASK 0x00000008L 1812a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR_MASK 0x00000010L 1813a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR_MASK 0x00000020L 1814a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR_MASK 0x00000040L 1815a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR_MASK 0x00000080L 1816a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR_MASK 0x00000100L 1817a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR_MASK 0x00000200L 1818a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR_MASK 0x00000400L 1819a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR_MASK 0x00000800L 1820a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR_MASK 0x00001000L 1821a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR_MASK 0x00002000L 1822a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR_MASK 0x00004000L 1823a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR_MASK 0x00008000L 1824a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR_MASK 0x00010000L 1825a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR_MASK 0x00020000L 1826a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR_MASK 0x00040000L 1827a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR_MASK 0x00080000L 1828a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR_MASK 0x00100000L 1829a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR_MASK 0x00200000L 1830a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR_MASK 0x00400000L 1831a5a25977SLeo Liu #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR_MASK 0x00800000L 1832a5a25977SLeo Liu //UVD_JPEG_IOV_ACTIVE_FCN_ID 1833a5a25977SLeo Liu #define UVD_JPEG_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 1834a5a25977SLeo Liu #define UVD_JPEG_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 1835a5a25977SLeo Liu #define UVD_JPEG_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000003FL 1836a5a25977SLeo Liu #define UVD_JPEG_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L 1837a5a25977SLeo Liu //JPEG_MASTINT_EN 1838a5a25977SLeo Liu #define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 1839a5a25977SLeo Liu #define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 1840a5a25977SLeo Liu #define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 1841a5a25977SLeo Liu #define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 1842a5a25977SLeo Liu //JPEG_IH_CTRL 1843a5a25977SLeo Liu #define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 1844a5a25977SLeo Liu #define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1 1845a5a25977SLeo Liu #define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 1846a5a25977SLeo Liu #define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3 1847a5a25977SLeo Liu #define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7 1848a5a25977SLeo Liu #define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13 1849a5a25977SLeo Liu #define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L 1850a5a25977SLeo Liu #define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L 1851a5a25977SLeo Liu #define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 1852a5a25977SLeo Liu #define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L 1853a5a25977SLeo Liu #define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L 1854a5a25977SLeo Liu #define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L 1855a5a25977SLeo Liu //JRBBM_ARB_CTRL 1856a5a25977SLeo Liu #define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT 0x0 1857a5a25977SLeo Liu #define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1 1858a5a25977SLeo Liu #define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x2 1859a5a25977SLeo Liu #define JRBBM_ARB_CTRL__DJRBC_DROP_MASK 0x00000001L 1860a5a25977SLeo Liu #define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L 1861a5a25977SLeo Liu #define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000004L 1862a5a25977SLeo Liu 1863a5a25977SLeo Liu 1864a5a25977SLeo Liu // addressBlock: uvd0_uvd_jpeg_common_sclk_dec 1865a5a25977SLeo Liu //JPEG_CGC_GATE 1866a5a25977SLeo Liu #define JPEG_CGC_GATE__JPEG_DEC__SHIFT 0x0 1867a5a25977SLeo Liu #define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x1 1868a5a25977SLeo Liu #define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x2 1869a5a25977SLeo Liu #define JPEG_CGC_GATE__JMCIF__SHIFT 0x3 1870a5a25977SLeo Liu #define JPEG_CGC_GATE__JRBBM__SHIFT 0x4 1871a5a25977SLeo Liu #define JPEG_CGC_GATE__JPEG_DEC_MASK 0x00000001L 1872a5a25977SLeo Liu #define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000002L 1873a5a25977SLeo Liu #define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000004L 1874a5a25977SLeo Liu #define JPEG_CGC_GATE__JMCIF_MASK 0x00000008L 1875a5a25977SLeo Liu #define JPEG_CGC_GATE__JRBBM_MASK 0x00000010L 1876a5a25977SLeo Liu //JPEG_CGC_CTRL 1877a5a25977SLeo Liu #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 1878a5a25977SLeo Liu #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1 1879a5a25977SLeo Liu #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5 1880a5a25977SLeo Liu #define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN__SHIFT 0xa 1881a5a25977SLeo Liu #define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN__SHIFT 0xb 1882a5a25977SLeo Liu #define JPEG_CGC_CTRL__GATER_DIV_ID__SHIFT 0xc 1883a5a25977SLeo Liu #define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT 0x10 1884a5a25977SLeo Liu #define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x11 1885a5a25977SLeo Liu #define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x12 1886a5a25977SLeo Liu #define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x13 1887a5a25977SLeo Liu #define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x14 1888a5a25977SLeo Liu #define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 1889a5a25977SLeo Liu #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL 1890a5a25977SLeo Liu #define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000003E0L 1891a5a25977SLeo Liu #define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN_MASK 0x00000400L 1892a5a25977SLeo Liu #define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN_MASK 0x00000800L 1893a5a25977SLeo Liu #define JPEG_CGC_CTRL__GATER_DIV_ID_MASK 0x00007000L 1894a5a25977SLeo Liu #define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 0x00010000L 1895a5a25977SLeo Liu #define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00020000L 1896a5a25977SLeo Liu #define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x00040000L 1897a5a25977SLeo Liu #define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x00080000L 1898a5a25977SLeo Liu #define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x00100000L 1899a5a25977SLeo Liu //JPEG_CGC_STATUS 1900a5a25977SLeo Liu #define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT 0x0 1901a5a25977SLeo Liu #define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT 0x1 1902a5a25977SLeo Liu #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x2 1903a5a25977SLeo Liu #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x3 1904a5a25977SLeo Liu #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x4 1905a5a25977SLeo Liu #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5 1906a5a25977SLeo Liu #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x6 1907a5a25977SLeo Liu #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x7 1908a5a25977SLeo Liu #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x8 1909a5a25977SLeo Liu #define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK 0x00000001L 1910a5a25977SLeo Liu #define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK 0x00000002L 1911a5a25977SLeo Liu #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000004L 1912a5a25977SLeo Liu #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000008L 1913a5a25977SLeo Liu #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00000010L 1914a5a25977SLeo Liu #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00000020L 1915a5a25977SLeo Liu #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00000040L 1916a5a25977SLeo Liu #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00000080L 1917a5a25977SLeo Liu #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00000100L 1918a5a25977SLeo Liu //JPEG_COMN_CGC_MEM_CTRL 1919a5a25977SLeo Liu #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0 1920a5a25977SLeo Liu #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1 1921a5a25977SLeo Liu #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2 1922a5a25977SLeo Liu #define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 1923a5a25977SLeo Liu #define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 1924a5a25977SLeo Liu #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L 1925a5a25977SLeo Liu #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L 1926a5a25977SLeo Liu #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L 1927a5a25977SLeo Liu #define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L 1928a5a25977SLeo Liu #define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L 1929a5a25977SLeo Liu //JPEG_DEC_CGC_MEM_CTRL 1930a5a25977SLeo Liu #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT 0x0 1931a5a25977SLeo Liu #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT 0x1 1932a5a25977SLeo Liu #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT 0x2 1933a5a25977SLeo Liu #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK 0x00000001L 1934a5a25977SLeo Liu #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK 0x00000002L 1935a5a25977SLeo Liu #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK 0x00000004L 1936a5a25977SLeo Liu //JPEG2_DEC_CGC_MEM_CTRL 1937a5a25977SLeo Liu #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x0 1938a5a25977SLeo Liu #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x1 1939a5a25977SLeo Liu #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0x2 1940a5a25977SLeo Liu #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000001L 1941a5a25977SLeo Liu #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000002L 1942a5a25977SLeo Liu #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000004L 1943a5a25977SLeo Liu //JPEG_ENC_CGC_MEM_CTRL 1944a5a25977SLeo Liu #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0 1945a5a25977SLeo Liu #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1 1946a5a25977SLeo Liu #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2 1947a5a25977SLeo Liu #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L 1948a5a25977SLeo Liu #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L 1949a5a25977SLeo Liu #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L 1950a5a25977SLeo Liu //JPEG_SOFT_RESET2 1951a5a25977SLeo Liu #define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 1952a5a25977SLeo Liu #define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 1953a5a25977SLeo Liu //JPEG_PERF_BANK_CONF 1954a5a25977SLeo Liu #define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0 1955a5a25977SLeo Liu #define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8 1956a5a25977SLeo Liu #define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10 1957a5a25977SLeo Liu #define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL 1958a5a25977SLeo Liu #define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L 1959a5a25977SLeo Liu #define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L 1960a5a25977SLeo Liu //JPEG_PERF_BANK_EVENT_SEL 1961a5a25977SLeo Liu #define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0 1962a5a25977SLeo Liu #define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8 1963a5a25977SLeo Liu #define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10 1964a5a25977SLeo Liu #define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18 1965a5a25977SLeo Liu #define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL 1966a5a25977SLeo Liu #define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L 1967a5a25977SLeo Liu #define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L 1968a5a25977SLeo Liu #define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L 1969a5a25977SLeo Liu //JPEG_PERF_BANK_COUNT0 1970a5a25977SLeo Liu #define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0 1971a5a25977SLeo Liu #define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL 1972a5a25977SLeo Liu //JPEG_PERF_BANK_COUNT1 1973a5a25977SLeo Liu #define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0 1974a5a25977SLeo Liu #define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL 1975a5a25977SLeo Liu //JPEG_PERF_BANK_COUNT2 1976a5a25977SLeo Liu #define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0 1977a5a25977SLeo Liu #define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL 1978a5a25977SLeo Liu //JPEG_PERF_BANK_COUNT3 1979a5a25977SLeo Liu #define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0 1980a5a25977SLeo Liu #define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL 1981a5a25977SLeo Liu 1982a5a25977SLeo Liu 1983a5a25977SLeo Liu // addressBlock: uvd0_uvd_pg_dec 1984a5a25977SLeo Liu //UVD_PGFSM_CONFIG 1985a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 1986a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2 1987a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4 1988a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6 1989a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8 1990a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 0xa 1991a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 0xc 1992a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe 1993a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10 1994a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12 1995a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 0x14 1996a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16 1997a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 0x18 1998a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 0x1a 1999a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT 0x1c 2000a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L 2001a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL 2002a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L 2003a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L 2004a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L 2005a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG_MASK 0x00000C00L 2006a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG_MASK 0x00003000L 2007a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L 2008a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L 2009a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L 2010a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG_MASK 0x00300000L 2011a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L 2012a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG_MASK 0x03000000L 2013a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG_MASK 0x0C000000L 2014a5a25977SLeo Liu #define UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG_MASK 0x30000000L 2015a5a25977SLeo Liu //UVD_PGFSM_STATUS 2016a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0 2017a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2 2018a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4 2019a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6 2020a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8 2021a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 0xa 2022a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 0xc 2023a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe 2024a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10 2025a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12 2026a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 0x14 2027a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16 2028a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 0x18 2029a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 0x1a 2030a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT 0x1c 2031a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L 2032a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL 2033a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L 2034a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L 2035a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L 2036a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS_MASK 0x00000C00L 2037a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDLM_PWR_STATUS_MASK 0x00003000L 2038a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L 2039a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L 2040a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L 2041a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDAB_PWR_STATUS_MASK 0x00300000L 2042a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L 2043a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDATD_PWR_STATUS_MASK 0x03000000L 2044a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDNA_PWR_STATUS_MASK 0x0C000000L 2045a5a25977SLeo Liu #define UVD_PGFSM_STATUS__UVDNB_PWR_STATUS_MASK 0x30000000L 2046a5a25977SLeo Liu //UVD_POWER_STATUS 2047a5a25977SLeo Liu #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 2048a5a25977SLeo Liu #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 2049a5a25977SLeo Liu #define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 2050a5a25977SLeo Liu #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 2051a5a25977SLeo Liu #define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 2052a5a25977SLeo Liu #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb 2053a5a25977SLeo Liu #define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f 2054a5a25977SLeo Liu #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L 2055a5a25977SLeo Liu #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L 2056a5a25977SLeo Liu #define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L 2057a5a25977SLeo Liu #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L 2058a5a25977SLeo Liu #define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L 2059a5a25977SLeo Liu #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L 2060a5a25977SLeo Liu #define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L 2061a5a25977SLeo Liu //UVD_PG_IND_INDEX 2062a5a25977SLeo Liu #define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0 2063a5a25977SLeo Liu #define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL 2064a5a25977SLeo Liu //UVD_PG_IND_DATA 2065a5a25977SLeo Liu #define UVD_PG_IND_DATA__DATA__SHIFT 0x0 2066a5a25977SLeo Liu #define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL 2067a5a25977SLeo Liu //CC_UVD_HARVESTING 2068a5a25977SLeo Liu #define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0 2069a5a25977SLeo Liu #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 2070a5a25977SLeo Liu #define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L 2071a5a25977SLeo Liu #define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 2072a5a25977SLeo Liu //UVD_JPEG_POWER_STATUS 2073a5a25977SLeo Liu #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0 2074a5a25977SLeo Liu #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4 2075a5a25977SLeo Liu #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8 2076a5a25977SLeo Liu #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9 2077a5a25977SLeo Liu #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f 2078a5a25977SLeo Liu #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L 2079a5a25977SLeo Liu #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L 2080a5a25977SLeo Liu #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L 2081a5a25977SLeo Liu #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L 2082a5a25977SLeo Liu #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L 2083a5a25977SLeo Liu //UVD_MC_DJPEG_RD_SPACE 2084a5a25977SLeo Liu #define UVD_MC_DJPEG_RD_SPACE__DJPEG_RD_SPACE__SHIFT 0x0 2085a5a25977SLeo Liu #define UVD_MC_DJPEG_RD_SPACE__DJPEG_RD_SPACE_MASK 0x0003FFFFL 2086a5a25977SLeo Liu //UVD_MC_DJPEG_WR_SPACE 2087a5a25977SLeo Liu #define UVD_MC_DJPEG_WR_SPACE__DJPEG_WR_SPACE__SHIFT 0x0 2088a5a25977SLeo Liu #define UVD_MC_DJPEG_WR_SPACE__DJPEG_WR_SPACE_MASK 0x0003FFFFL 2089a5a25977SLeo Liu //UVD_MC_EJPEG_RD_SPACE 2090a5a25977SLeo Liu #define UVD_MC_EJPEG_RD_SPACE__EJPEG_RD_SPACE__SHIFT 0x0 2091a5a25977SLeo Liu #define UVD_MC_EJPEG_RD_SPACE__EJPEG_RD_SPACE_MASK 0x0003FFFFL 2092a5a25977SLeo Liu //UVD_MC_EJPEG_WR_SPACE 2093a5a25977SLeo Liu #define UVD_MC_EJPEG_WR_SPACE__EJPEG_WR_SPACE__SHIFT 0x0 2094a5a25977SLeo Liu #define UVD_MC_EJPEG_WR_SPACE__EJPEG_WR_SPACE_MASK 0x0003FFFFL 2095a5a25977SLeo Liu //UVD_DPG_LMA_CTL 2096a5a25977SLeo Liu #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 2097a5a25977SLeo Liu #define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 2098a5a25977SLeo Liu #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 2099a5a25977SLeo Liu #define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 2100a5a25977SLeo Liu #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 2101a5a25977SLeo Liu #define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L 2102a5a25977SLeo Liu #define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L 2103a5a25977SLeo Liu #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L 2104a5a25977SLeo Liu #define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L 2105a5a25977SLeo Liu #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L 2106a5a25977SLeo Liu //UVD_DPG_LMA_DATA 2107a5a25977SLeo Liu #define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0 2108a5a25977SLeo Liu #define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL 2109a5a25977SLeo Liu //UVD_DPG_LMA_MASK 2110a5a25977SLeo Liu #define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0 2111a5a25977SLeo Liu #define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL 2112a5a25977SLeo Liu //UVD_DPG_PAUSE 2113a5a25977SLeo Liu #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 2114a5a25977SLeo Liu #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 2115a5a25977SLeo Liu #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 2116a5a25977SLeo Liu #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 2117a5a25977SLeo Liu #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L 2118a5a25977SLeo Liu #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L 2119a5a25977SLeo Liu #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L 2120a5a25977SLeo Liu #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L 2121a5a25977SLeo Liu //UVD_SCRATCH1 2122a5a25977SLeo Liu #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 2123a5a25977SLeo Liu #define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL 2124a5a25977SLeo Liu //UVD_SCRATCH2 2125a5a25977SLeo Liu #define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 2126a5a25977SLeo Liu #define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL 2127a5a25977SLeo Liu //UVD_SCRATCH3 2128a5a25977SLeo Liu #define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 2129a5a25977SLeo Liu #define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL 2130a5a25977SLeo Liu //UVD_SCRATCH4 2131a5a25977SLeo Liu #define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 2132a5a25977SLeo Liu #define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL 2133a5a25977SLeo Liu //UVD_SCRATCH5 2134a5a25977SLeo Liu #define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 2135a5a25977SLeo Liu #define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL 2136a5a25977SLeo Liu //UVD_SCRATCH6 2137a5a25977SLeo Liu #define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 2138a5a25977SLeo Liu #define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL 2139a5a25977SLeo Liu //UVD_SCRATCH7 2140a5a25977SLeo Liu #define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 2141a5a25977SLeo Liu #define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL 2142a5a25977SLeo Liu //UVD_SCRATCH8 2143a5a25977SLeo Liu #define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 2144a5a25977SLeo Liu #define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL 2145a5a25977SLeo Liu //UVD_SCRATCH9 2146a5a25977SLeo Liu #define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 2147a5a25977SLeo Liu #define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL 2148a5a25977SLeo Liu //UVD_SCRATCH10 2149a5a25977SLeo Liu #define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 2150a5a25977SLeo Liu #define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL 2151a5a25977SLeo Liu //UVD_SCRATCH11 2152a5a25977SLeo Liu #define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 2153a5a25977SLeo Liu #define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL 2154a5a25977SLeo Liu //UVD_SCRATCH12 2155a5a25977SLeo Liu #define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 2156a5a25977SLeo Liu #define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL 2157a5a25977SLeo Liu //UVD_SCRATCH13 2158a5a25977SLeo Liu #define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 2159a5a25977SLeo Liu #define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL 2160a5a25977SLeo Liu //UVD_SCRATCH14 2161a5a25977SLeo Liu #define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 2162a5a25977SLeo Liu #define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL 2163a5a25977SLeo Liu //UVD_FREE_COUNTER_REG 2164a5a25977SLeo Liu #define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0 2165a5a25977SLeo Liu #define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL 2166a5a25977SLeo Liu //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 2167a5a25977SLeo Liu #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 2168a5a25977SLeo Liu #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 2169a5a25977SLeo Liu //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 2170a5a25977SLeo Liu #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 2171a5a25977SLeo Liu #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 2172a5a25977SLeo Liu //UVD_DPG_VCPU_CACHE_OFFSET0 2173a5a25977SLeo Liu #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 2174a5a25977SLeo Liu #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL 2175a5a25977SLeo Liu //UVD_DPG_LMI_VCPU_CACHE_VMID 2176a5a25977SLeo Liu #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 2177a5a25977SLeo Liu #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 2178a5a25977SLeo Liu //UVD_REG_FILTER_EN 2179a5a25977SLeo Liu #define UVD_REG_FILTER_EN__UVD_REG_FILTER_EN__SHIFT 0x0 2180a5a25977SLeo Liu #define UVD_REG_FILTER_EN__MMSCH_HI_PRIV__SHIFT 0x1 2181a5a25977SLeo Liu #define UVD_REG_FILTER_EN__VIDEO_PRIV_EN__SHIFT 0x2 2182a5a25977SLeo Liu #define UVD_REG_FILTER_EN__JPEG_PRIV_EN__SHIFT 0x3 2183a5a25977SLeo Liu #define UVD_REG_FILTER_EN__UVD_REG_FILTER_EN_MASK 0x00000001L 2184a5a25977SLeo Liu #define UVD_REG_FILTER_EN__MMSCH_HI_PRIV_MASK 0x00000002L 2185a5a25977SLeo Liu #define UVD_REG_FILTER_EN__VIDEO_PRIV_EN_MASK 0x00000004L 2186a5a25977SLeo Liu #define UVD_REG_FILTER_EN__JPEG_PRIV_EN_MASK 0x00000008L 2187a5a25977SLeo Liu //CC_UVD_VCPU_ERR_DETECT_BOT_LO 2188a5a25977SLeo Liu #define CC_UVD_VCPU_ERR_DETECT_BOT_LO__UVD_VCPU_ERR_DETECT_BOT_LO__SHIFT 0xc 2189a5a25977SLeo Liu #define CC_UVD_VCPU_ERR_DETECT_BOT_LO__UVD_VCPU_ERR_DETECT_BOT_LO_MASK 0xFFFFF000L 2190a5a25977SLeo Liu //CC_UVD_VCPU_ERR_DETECT_BOT_HI 2191a5a25977SLeo Liu #define CC_UVD_VCPU_ERR_DETECT_BOT_HI__UVD_VCPU_ERR_DETECT_BOT_HI__SHIFT 0x0 2192a5a25977SLeo Liu #define CC_UVD_VCPU_ERR_DETECT_BOT_HI__UVD_VCPU_ERR_DETECT_BOT_HI_MASK 0x0000FFFFL 2193a5a25977SLeo Liu //CC_UVD_VCPU_ERR_DETECT_TOP_LO 2194a5a25977SLeo Liu #define CC_UVD_VCPU_ERR_DETECT_TOP_LO__UVD_VCPU_ERR_DETECT_TOP_LO__SHIFT 0xc 2195a5a25977SLeo Liu #define CC_UVD_VCPU_ERR_DETECT_TOP_LO__UVD_VCPU_ERR_DETECT_TOP_LO_MASK 0xFFFFF000L 2196a5a25977SLeo Liu //CC_UVD_VCPU_ERR_DETECT_TOP_HI 2197a5a25977SLeo Liu #define CC_UVD_VCPU_ERR_DETECT_TOP_HI__UVD_VCPU_ERR_DETECT_TOP_HI__SHIFT 0x0 2198a5a25977SLeo Liu #define CC_UVD_VCPU_ERR_DETECT_TOP_HI__UVD_VCPU_ERR_DETECT_TOP_HI_MASK 0x0000FFFFL 2199a5a25977SLeo Liu //CC_UVD_VCPU_ERR 2200a5a25977SLeo Liu #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_STATUS__SHIFT 0x0 2201a5a25977SLeo Liu #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_CLEAR__SHIFT 0x1 2202a5a25977SLeo Liu #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_DETECT_EN__SHIFT 0x2 2203a5a25977SLeo Liu #define CC_UVD_VCPU_ERR__RESET_ON_FAULT__SHIFT 0x4 2204a5a25977SLeo Liu #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_STATUS_MASK 0x00000001L 2205a5a25977SLeo Liu #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_CLEAR_MASK 0x00000002L 2206a5a25977SLeo Liu #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_DETECT_EN_MASK 0x00000004L 2207a5a25977SLeo Liu #define CC_UVD_VCPU_ERR__RESET_ON_FAULT_MASK 0x00000010L 2208a5a25977SLeo Liu //CC_UVD_VCPU_ERR_INST_ADDR_LO 2209a5a25977SLeo Liu #define CC_UVD_VCPU_ERR_INST_ADDR_LO__UVD_VCPU_ERR_INST_ADDR_LO__SHIFT 0x0 2210a5a25977SLeo Liu #define CC_UVD_VCPU_ERR_INST_ADDR_LO__UVD_VCPU_ERR_INST_ADDR_LO_MASK 0xFFFFFFFFL 2211a5a25977SLeo Liu //CC_UVD_VCPU_ERR_INST_ADDR_HI 2212a5a25977SLeo Liu #define CC_UVD_VCPU_ERR_INST_ADDR_HI__UVD_VCPU_ERR_INST_ADDR_HI__SHIFT 0x0 2213a5a25977SLeo Liu #define CC_UVD_VCPU_ERR_INST_ADDR_HI__UVD_VCPU_ERR_INST_ADDR_HI_MASK 0x0000FFFFL 2214a5a25977SLeo Liu //UVD_PF_STATUS 2215a5a25977SLeo Liu #define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0 2216a5a25977SLeo Liu #define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1 2217a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2 2218a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3 2219a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4 2220a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5 2221a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6 2222a5a25977SLeo Liu #define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7 2223a5a25977SLeo Liu #define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8 2224a5a25977SLeo Liu #define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9 2225a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa 2226a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb 2227a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc 2228a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd 2229a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe 2230a5a25977SLeo Liu #define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf 2231a5a25977SLeo Liu #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10 2232a5a25977SLeo Liu #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11 2233a5a25977SLeo Liu #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12 2234a5a25977SLeo Liu #define UVD_PF_STATUS__JPEG2_PF_OCCURED__SHIFT 0x13 2235a5a25977SLeo Liu #define UVD_PF_STATUS__DJ2_ATM_PF_OCCURED__SHIFT 0x14 2236a5a25977SLeo Liu #define UVD_PF_STATUS__JPEG2_PF_CLEAR__SHIFT 0x15 2237a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER5_PF_OCCURED__SHIFT 0x16 2238a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER5_PF_CLEAR__SHIFT 0x17 2239a5a25977SLeo Liu #define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L 2240a5a25977SLeo Liu #define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L 2241a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L 2242a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L 2243a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L 2244a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L 2245a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L 2246a5a25977SLeo Liu #define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L 2247a5a25977SLeo Liu #define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L 2248a5a25977SLeo Liu #define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L 2249a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L 2250a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L 2251a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L 2252a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L 2253a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L 2254a5a25977SLeo Liu #define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L 2255a5a25977SLeo Liu #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L 2256a5a25977SLeo Liu #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L 2257a5a25977SLeo Liu #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L 2258a5a25977SLeo Liu #define UVD_PF_STATUS__JPEG2_PF_OCCURED_MASK 0x00080000L 2259a5a25977SLeo Liu #define UVD_PF_STATUS__DJ2_ATM_PF_OCCURED_MASK 0x00100000L 2260a5a25977SLeo Liu #define UVD_PF_STATUS__JPEG2_PF_CLEAR_MASK 0x00200000L 2261a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER5_PF_OCCURED_MASK 0x00400000L 2262a5a25977SLeo Liu #define UVD_PF_STATUS__ENCODER5_PF_CLEAR_MASK 0x00800000L 2263a5a25977SLeo Liu //UVD_FW_VERSION 2264a5a25977SLeo Liu #define UVD_FW_VERSION__FW_VERSION__SHIFT 0x0 2265a5a25977SLeo Liu #define UVD_FW_VERSION__FW_VERSION_MASK 0xFFFFFFFFL 2266a5a25977SLeo Liu //UVD_DPG_CLK_EN_VCPU_REPORT 2267a5a25977SLeo Liu #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0 2268a5a25977SLeo Liu #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1 2269a5a25977SLeo Liu #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L 2270a5a25977SLeo Liu #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL 2271a5a25977SLeo Liu //UVD_SECURITY_REG_VIO_REPORT 2272a5a25977SLeo Liu #define UVD_SECURITY_REG_VIO_REPORT__HOST_REG_VIO__SHIFT 0x0 2273a5a25977SLeo Liu #define UVD_SECURITY_REG_VIO_REPORT__VCPU_REG_VIO__SHIFT 0x1 2274a5a25977SLeo Liu #define UVD_SECURITY_REG_VIO_REPORT__VIDEO_REG_VIO__SHIFT 0x2 2275a5a25977SLeo Liu #define UVD_SECURITY_REG_VIO_REPORT__DPG_REG_VIO__SHIFT 0x3 2276a5a25977SLeo Liu #define UVD_SECURITY_REG_VIO_REPORT__JPEG_REG_VIO__SHIFT 0x4 2277a5a25977SLeo Liu #define UVD_SECURITY_REG_VIO_REPORT__JDPG_REG_VIO__SHIFT 0x5 2278a5a25977SLeo Liu #define UVD_SECURITY_REG_VIO_REPORT__HOST_REG_VIO_MASK 0x00000001L 2279a5a25977SLeo Liu #define UVD_SECURITY_REG_VIO_REPORT__VCPU_REG_VIO_MASK 0x00000002L 2280a5a25977SLeo Liu #define UVD_SECURITY_REG_VIO_REPORT__VIDEO_REG_VIO_MASK 0x00000004L 2281a5a25977SLeo Liu #define UVD_SECURITY_REG_VIO_REPORT__DPG_REG_VIO_MASK 0x00000008L 2282a5a25977SLeo Liu #define UVD_SECURITY_REG_VIO_REPORT__JPEG_REG_VIO_MASK 0x00000010L 2283a5a25977SLeo Liu #define UVD_SECURITY_REG_VIO_REPORT__JDPG_REG_VIO_MASK 0x00000020L 2284a5a25977SLeo Liu //UVD_LMI_MMSCH_NC_SPACE 2285a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC0_SPACE__SHIFT 0x0 2286a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC1_SPACE__SHIFT 0x3 2287a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC2_SPACE__SHIFT 0x6 2288a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC3_SPACE__SHIFT 0x9 2289a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC4_SPACE__SHIFT 0xc 2290a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC5_SPACE__SHIFT 0xf 2291a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC6_SPACE__SHIFT 0x12 2292a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC7_SPACE__SHIFT 0x15 2293a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC0_SPACE_MASK 0x00000007L 2294a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC1_SPACE_MASK 0x00000038L 2295a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC2_SPACE_MASK 0x000001C0L 2296a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC3_SPACE_MASK 0x00000E00L 2297a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC4_SPACE_MASK 0x00007000L 2298a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC5_SPACE_MASK 0x00038000L 2299a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC6_SPACE_MASK 0x001C0000L 2300a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC7_SPACE_MASK 0x00E00000L 2301a5a25977SLeo Liu //UVD_LMI_ATOMIC_SPACE 2302a5a25977SLeo Liu #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER0_SPACE__SHIFT 0x0 2303a5a25977SLeo Liu #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER1_SPACE__SHIFT 0x3 2304a5a25977SLeo Liu #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER2_SPACE__SHIFT 0x6 2305a5a25977SLeo Liu #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER3_SPACE__SHIFT 0x9 2306a5a25977SLeo Liu #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER0_SPACE_MASK 0x00000007L 2307a5a25977SLeo Liu #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER1_SPACE_MASK 0x00000038L 2308a5a25977SLeo Liu #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER2_SPACE_MASK 0x000001C0L 2309a5a25977SLeo Liu #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER3_SPACE_MASK 0x00000E00L 2310a5a25977SLeo Liu //UVD_GFX10_ADDR_CONFIG 2311a5a25977SLeo Liu #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 2312a5a25977SLeo Liu #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 2313a5a25977SLeo Liu #define UVD_GFX10_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 2314a5a25977SLeo Liu #define UVD_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 2315a5a25977SLeo Liu #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 2316a5a25977SLeo Liu #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 2317a5a25977SLeo Liu #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 2318a5a25977SLeo Liu #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 2319a5a25977SLeo Liu #define UVD_GFX10_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 2320a5a25977SLeo Liu #define UVD_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 2321a5a25977SLeo Liu #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 2322a5a25977SLeo Liu #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 2323a5a25977SLeo Liu //UVD_GPCNT2_CNTL 2324a5a25977SLeo Liu #define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0 2325a5a25977SLeo Liu #define UVD_GPCNT2_CNTL__START__SHIFT 0x1 2326a5a25977SLeo Liu #define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2 2327a5a25977SLeo Liu #define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L 2328a5a25977SLeo Liu #define UVD_GPCNT2_CNTL__START_MASK 0x00000002L 2329a5a25977SLeo Liu #define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L 2330a5a25977SLeo Liu //UVD_GPCNT2_TARGET_LOWER 2331a5a25977SLeo Liu #define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0 2332a5a25977SLeo Liu #define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 2333a5a25977SLeo Liu //UVD_GPCNT2_STATUS_LOWER 2334a5a25977SLeo Liu #define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0 2335a5a25977SLeo Liu #define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 2336a5a25977SLeo Liu //UVD_GPCNT2_TARGET_UPPER 2337a5a25977SLeo Liu #define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0 2338a5a25977SLeo Liu #define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 2339a5a25977SLeo Liu //UVD_GPCNT2_STATUS_UPPER 2340a5a25977SLeo Liu #define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0 2341a5a25977SLeo Liu #define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 2342a5a25977SLeo Liu //UVD_GPCNT3_CNTL 2343a5a25977SLeo Liu #define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0 2344a5a25977SLeo Liu #define UVD_GPCNT3_CNTL__START__SHIFT 0x1 2345a5a25977SLeo Liu #define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2 2346a5a25977SLeo Liu #define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3 2347a5a25977SLeo Liu #define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa 2348a5a25977SLeo Liu #define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L 2349a5a25977SLeo Liu #define UVD_GPCNT3_CNTL__START_MASK 0x00000002L 2350a5a25977SLeo Liu #define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L 2351a5a25977SLeo Liu #define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L 2352a5a25977SLeo Liu #define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L 2353a5a25977SLeo Liu //UVD_GPCNT3_TARGET_LOWER 2354a5a25977SLeo Liu #define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0 2355a5a25977SLeo Liu #define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 2356a5a25977SLeo Liu //UVD_GPCNT3_STATUS_LOWER 2357a5a25977SLeo Liu #define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0 2358a5a25977SLeo Liu #define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 2359a5a25977SLeo Liu //UVD_GPCNT3_TARGET_UPPER 2360a5a25977SLeo Liu #define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0 2361a5a25977SLeo Liu #define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 2362a5a25977SLeo Liu //UVD_GPCNT3_STATUS_UPPER 2363a5a25977SLeo Liu #define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0 2364a5a25977SLeo Liu #define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 2365a5a25977SLeo Liu //UVD_VCLK_DS_CNTL 2366a5a25977SLeo Liu #define UVD_VCLK_DS_CNTL__VCLK_DS_EN__SHIFT 0x0 2367a5a25977SLeo Liu #define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS__SHIFT 0x4 2368a5a25977SLeo Liu #define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 2369a5a25977SLeo Liu #define UVD_VCLK_DS_CNTL__VCLK_DS_EN_MASK 0x00000001L 2370a5a25977SLeo Liu #define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS_MASK 0x00000010L 2371a5a25977SLeo Liu #define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L 2372a5a25977SLeo Liu //UVD_DCLK_DS_CNTL 2373a5a25977SLeo Liu #define UVD_DCLK_DS_CNTL__DCLK_DS_EN__SHIFT 0x0 2374a5a25977SLeo Liu #define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS__SHIFT 0x4 2375a5a25977SLeo Liu #define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 2376a5a25977SLeo Liu #define UVD_DCLK_DS_CNTL__DCLK_DS_EN_MASK 0x00000001L 2377a5a25977SLeo Liu #define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS_MASK 0x00000010L 2378a5a25977SLeo Liu #define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L 2379a5a25977SLeo Liu //UVD_TSC_LOWER 2380a5a25977SLeo Liu #define UVD_TSC_LOWER__COUNT__SHIFT 0x0 2381a5a25977SLeo Liu #define UVD_TSC_LOWER__COUNT_MASK 0xFFFFFFFFL 2382a5a25977SLeo Liu //UVD_TSC_UPPER 2383a5a25977SLeo Liu #define UVD_TSC_UPPER__COUNT__SHIFT 0x0 2384a5a25977SLeo Liu #define UVD_TSC_UPPER__COUNT_MASK 0x00FFFFFFL 2385a5a25977SLeo Liu //VCN_FEATURES 2386a5a25977SLeo Liu #define VCN_FEATURES__HAS_VIDEO_DEC__SHIFT 0x0 2387a5a25977SLeo Liu #define VCN_FEATURES__HAS_VIDEO_ENC__SHIFT 0x1 2388a5a25977SLeo Liu #define VCN_FEATURES__HAS_MJPEG_DEC__SHIFT 0x2 2389a5a25977SLeo Liu #define VCN_FEATURES__HAS_MJPEG_ENC__SHIFT 0x3 2390a5a25977SLeo Liu #define VCN_FEATURES__HAS_VIDEO_VIRT__SHIFT 0x4 2391a5a25977SLeo Liu #define VCN_FEATURES__HAS_H264_LEGACY_DEC__SHIFT 0x5 2392a5a25977SLeo Liu #define VCN_FEATURES__HAS_UDEC_DEC__SHIFT 0x6 2393a5a25977SLeo Liu #define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC__SHIFT 0x7 2394a5a25977SLeo Liu #define VCN_FEATURES__HAS_SCLR_DEC__SHIFT 0x8 2395a5a25977SLeo Liu #define VCN_FEATURES__HAS_VP9_DEC__SHIFT 0x9 23961b51916bSAlex Deucher #define VCN_FEATURES__HAS_AV1_DEC__SHIFT 0xa 2397a5a25977SLeo Liu #define VCN_FEATURES__HAS_EFC_ENC__SHIFT 0xb 2398a5a25977SLeo Liu #define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC__SHIFT 0xc 2399a5a25977SLeo Liu #define VCN_FEATURES__HAS_DUAL_MJPEG_DEC__SHIFT 0xd 2400a5a25977SLeo Liu #define VCN_FEATURES__INSTANCE_ID__SHIFT 0x1c 2401a5a25977SLeo Liu #define VCN_FEATURES__HAS_VIDEO_DEC_MASK 0x00000001L 2402a5a25977SLeo Liu #define VCN_FEATURES__HAS_VIDEO_ENC_MASK 0x00000002L 2403a5a25977SLeo Liu #define VCN_FEATURES__HAS_MJPEG_DEC_MASK 0x00000004L 2404a5a25977SLeo Liu #define VCN_FEATURES__HAS_MJPEG_ENC_MASK 0x00000008L 2405a5a25977SLeo Liu #define VCN_FEATURES__HAS_VIDEO_VIRT_MASK 0x00000010L 2406a5a25977SLeo Liu #define VCN_FEATURES__HAS_H264_LEGACY_DEC_MASK 0x00000020L 2407a5a25977SLeo Liu #define VCN_FEATURES__HAS_UDEC_DEC_MASK 0x00000040L 2408a5a25977SLeo Liu #define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC_MASK 0x00000080L 2409a5a25977SLeo Liu #define VCN_FEATURES__HAS_SCLR_DEC_MASK 0x00000100L 2410a5a25977SLeo Liu #define VCN_FEATURES__HAS_VP9_DEC_MASK 0x00000200L 24111b51916bSAlex Deucher #define VCN_FEATURES__HAS_AV1_DEC_MASK 0x00000400L 2412a5a25977SLeo Liu #define VCN_FEATURES__HAS_EFC_ENC_MASK 0x00000800L 2413a5a25977SLeo Liu #define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC_MASK 0x00001000L 2414a5a25977SLeo Liu #define VCN_FEATURES__HAS_DUAL_MJPEG_DEC_MASK 0x00002000L 2415a5a25977SLeo Liu #define VCN_FEATURES__INSTANCE_ID_MASK 0xF0000000L 2416a5a25977SLeo Liu //UVD_GPUIOV_STATUS 2417a5a25977SLeo Liu #define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE__SHIFT 0x0 2418a5a25977SLeo Liu #define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE_MASK 0x00000001L 2419a5a25977SLeo Liu 2420a5a25977SLeo Liu 2421a5a25977SLeo Liu // addressBlock: uvd0_uvddec 2422a5a25977SLeo Liu //UVD_STATUS 2423a5a25977SLeo Liu #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 2424a5a25977SLeo Liu #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 2425a5a25977SLeo Liu #define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 2426a5a25977SLeo Liu #define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f 2427a5a25977SLeo Liu #define UVD_STATUS__RBC_BUSY_MASK 0x00000001L 2428a5a25977SLeo Liu #define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL 2429a5a25977SLeo Liu #define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L 2430a5a25977SLeo Liu #define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L 2431a5a25977SLeo Liu //UVD_ENC_PIPE_BUSY 2432a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 2433a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 2434a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 2435a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 2436a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 2437a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 2438a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 2439a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 2440a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 2441a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa 2442a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 2443a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 2444a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 2445a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 2446a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 2447a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 2448a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 2449a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 2450a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 2451a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 2452a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a 2453a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b 2454a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c 2455a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d 2456a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e 2457a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__SAOE_BUSY__SHIFT 0x1f 2458a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L 2459a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L 2460a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L 2461a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L 2462a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L 2463a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L 2464a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L 2465a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L 2466a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L 2467a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L 2468a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L 2469a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L 2470a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L 2471a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L 2472a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L 2473a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L 2474a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L 2475a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L 2476a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L 2477a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L 2478a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L 2479a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L 2480a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L 2481a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L 2482a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L 2483a5a25977SLeo Liu #define UVD_ENC_PIPE_BUSY__SAOE_BUSY_MASK 0x80000000L 2484a5a25977SLeo Liu //UVD_FW_POWER_STATUS 2485a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDF_PWR_OFF__SHIFT 0x0 2486a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDC_PWR_OFF__SHIFT 0x1 2487a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDB_PWR_OFF__SHIFT 0x2 2488a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDIRL_PWR_OFF__SHIFT 0x3 2489a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF__SHIFT 0x4 2490a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF__SHIFT 0x5 2491a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDE_PWR_OFF__SHIFT 0x6 2492a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDAB_PWR_OFF__SHIFT 0x7 2493a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDATD_PWR_OFF__SHIFT 0x8 2494a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDNA_PWR_OFF__SHIFT 0x9 2495a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDNB_PWR_OFF__SHIFT 0xa 2496a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDF_PWR_OFF_MASK 0x00000001L 2497a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDC_PWR_OFF_MASK 0x00000002L 2498a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDB_PWR_OFF_MASK 0x00000004L 2499a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDIRL_PWR_OFF_MASK 0x00000008L 2500a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF_MASK 0x00000010L 2501a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF_MASK 0x00000020L 2502a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDE_PWR_OFF_MASK 0x00000040L 2503a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDAB_PWR_OFF_MASK 0x00000080L 2504a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDATD_PWR_OFF_MASK 0x00000100L 2505a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDNA_PWR_OFF_MASK 0x00000200L 2506a5a25977SLeo Liu #define UVD_FW_POWER_STATUS__UVDNB_PWR_OFF_MASK 0x00000400L 2507a5a25977SLeo Liu //UVD_CNTL 2508a5a25977SLeo Liu #define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 2509a5a25977SLeo Liu #define UVD_CNTL__SUVD_EN__SHIFT 0x13 2510a5a25977SLeo Liu #define UVD_CNTL__CABAC_MB_ACC__SHIFT 0x1c 2511a5a25977SLeo Liu #define UVD_CNTL__LRBBM_SAFE_SYNC_DIS__SHIFT 0x1f 2512a5a25977SLeo Liu #define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L 2513a5a25977SLeo Liu #define UVD_CNTL__SUVD_EN_MASK 0x00080000L 2514a5a25977SLeo Liu #define UVD_CNTL__CABAC_MB_ACC_MASK 0x10000000L 2515a5a25977SLeo Liu #define UVD_CNTL__LRBBM_SAFE_SYNC_DIS_MASK 0x80000000L 2516a5a25977SLeo Liu //UVD_SOFT_RESET 2517a5a25977SLeo Liu #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 2518a5a25977SLeo Liu #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 2519a5a25977SLeo Liu #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 2520a5a25977SLeo Liu #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 2521a5a25977SLeo Liu #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 2522a5a25977SLeo Liu #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 2523a5a25977SLeo Liu #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 2524a5a25977SLeo Liu #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 2525a5a25977SLeo Liu #define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9 2526a5a25977SLeo Liu #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 2527a5a25977SLeo Liu #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 2528a5a25977SLeo Liu #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 2529a5a25977SLeo Liu #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 2530a5a25977SLeo Liu #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 2531a5a25977SLeo Liu #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 2532a5a25977SLeo Liu #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 2533a5a25977SLeo Liu #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 2534a5a25977SLeo Liu #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 2535a5a25977SLeo Liu #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 2536a5a25977SLeo Liu #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 2537a5a25977SLeo Liu #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 2538a5a25977SLeo Liu #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 2539a5a25977SLeo Liu #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 2540a5a25977SLeo Liu #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 2541a5a25977SLeo Liu #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 2542a5a25977SLeo Liu #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 2543a5a25977SLeo Liu #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 2544a5a25977SLeo Liu #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 2545a5a25977SLeo Liu #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 2546a5a25977SLeo Liu #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 2547a5a25977SLeo Liu #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 2548a5a25977SLeo Liu #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L 2549a5a25977SLeo Liu #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L 2550a5a25977SLeo Liu #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L 2551a5a25977SLeo Liu #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L 2552a5a25977SLeo Liu #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L 2553a5a25977SLeo Liu #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L 2554a5a25977SLeo Liu #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L 2555a5a25977SLeo Liu #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L 2556a5a25977SLeo Liu #define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L 2557a5a25977SLeo Liu #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L 2558a5a25977SLeo Liu #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L 2559a5a25977SLeo Liu #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L 2560a5a25977SLeo Liu #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L 2561a5a25977SLeo Liu #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L 2562a5a25977SLeo Liu #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L 2563a5a25977SLeo Liu #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L 2564a5a25977SLeo Liu #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L 2565a5a25977SLeo Liu #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L 2566a5a25977SLeo Liu #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L 2567a5a25977SLeo Liu #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L 2568a5a25977SLeo Liu #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L 2569a5a25977SLeo Liu #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L 2570a5a25977SLeo Liu #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L 2571a5a25977SLeo Liu #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L 2572a5a25977SLeo Liu #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L 2573a5a25977SLeo Liu #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L 2574a5a25977SLeo Liu #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L 2575a5a25977SLeo Liu #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L 2576a5a25977SLeo Liu #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L 2577a5a25977SLeo Liu #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L 2578a5a25977SLeo Liu #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L 2579a5a25977SLeo Liu //UVD_SOFT_RESET2 2580a5a25977SLeo Liu #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 2581a5a25977SLeo Liu #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10 2582a5a25977SLeo Liu #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11 2583a5a25977SLeo Liu #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 2584a5a25977SLeo Liu #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L 2585a5a25977SLeo Liu #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L 2586a5a25977SLeo Liu //UVD_MMSCH_SOFT_RESET 2587a5a25977SLeo Liu #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0 2588a5a25977SLeo Liu #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1 2589a5a25977SLeo Liu #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f 2590a5a25977SLeo Liu #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L 2591a5a25977SLeo Liu #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L 2592a5a25977SLeo Liu #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L 2593a5a25977SLeo Liu //UVD_WIG_CTRL 2594a5a25977SLeo Liu #define UVD_WIG_CTRL__AVM_SOFT_RESET__SHIFT 0x0 2595a5a25977SLeo Liu #define UVD_WIG_CTRL__ACAP_SOFT_RESET__SHIFT 0x1 2596a5a25977SLeo Liu #define UVD_WIG_CTRL__WIG_SOFT_RESET__SHIFT 0x2 2597a5a25977SLeo Liu #define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON__SHIFT 0x3 2598a5a25977SLeo Liu #define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON__SHIFT 0x4 2599a5a25977SLeo Liu #define UVD_WIG_CTRL__AVM_SOFT_RESET_MASK 0x00000001L 2600a5a25977SLeo Liu #define UVD_WIG_CTRL__ACAP_SOFT_RESET_MASK 0x00000002L 2601a5a25977SLeo Liu #define UVD_WIG_CTRL__WIG_SOFT_RESET_MASK 0x00000004L 2602a5a25977SLeo Liu #define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON_MASK 0x00000008L 2603a5a25977SLeo Liu #define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON_MASK 0x00000010L 2604a5a25977SLeo Liu //UVD_CGC_GATE 2605a5a25977SLeo Liu #define UVD_CGC_GATE__SYS__SHIFT 0x0 2606a5a25977SLeo Liu #define UVD_CGC_GATE__UDEC__SHIFT 0x1 2607a5a25977SLeo Liu #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 2608a5a25977SLeo Liu #define UVD_CGC_GATE__REGS__SHIFT 0x3 2609a5a25977SLeo Liu #define UVD_CGC_GATE__RBC__SHIFT 0x4 2610a5a25977SLeo Liu #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 2611a5a25977SLeo Liu #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 2612a5a25977SLeo Liu #define UVD_CGC_GATE__IDCT__SHIFT 0x7 2613a5a25977SLeo Liu #define UVD_CGC_GATE__MPRD__SHIFT 0x8 2614a5a25977SLeo Liu #define UVD_CGC_GATE__MPC__SHIFT 0x9 2615a5a25977SLeo Liu #define UVD_CGC_GATE__LBSI__SHIFT 0xa 2616a5a25977SLeo Liu #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 2617a5a25977SLeo Liu #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 2618a5a25977SLeo Liu #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 2619a5a25977SLeo Liu #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 2620a5a25977SLeo Liu #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 2621a5a25977SLeo Liu #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 2622a5a25977SLeo Liu #define UVD_CGC_GATE__WCB__SHIFT 0x11 2623a5a25977SLeo Liu #define UVD_CGC_GATE__VCPU__SHIFT 0x12 2624a5a25977SLeo Liu #define UVD_CGC_GATE__MMSCH__SHIFT 0x14 2625a5a25977SLeo Liu #define UVD_CGC_GATE__SYS_MASK 0x00000001L 2626a5a25977SLeo Liu #define UVD_CGC_GATE__UDEC_MASK 0x00000002L 2627a5a25977SLeo Liu #define UVD_CGC_GATE__MPEG2_MASK 0x00000004L 2628a5a25977SLeo Liu #define UVD_CGC_GATE__REGS_MASK 0x00000008L 2629a5a25977SLeo Liu #define UVD_CGC_GATE__RBC_MASK 0x00000010L 2630a5a25977SLeo Liu #define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L 2631a5a25977SLeo Liu #define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L 2632a5a25977SLeo Liu #define UVD_CGC_GATE__IDCT_MASK 0x00000080L 2633a5a25977SLeo Liu #define UVD_CGC_GATE__MPRD_MASK 0x00000100L 2634a5a25977SLeo Liu #define UVD_CGC_GATE__MPC_MASK 0x00000200L 2635a5a25977SLeo Liu #define UVD_CGC_GATE__LBSI_MASK 0x00000400L 2636a5a25977SLeo Liu #define UVD_CGC_GATE__LRBBM_MASK 0x00000800L 2637a5a25977SLeo Liu #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L 2638a5a25977SLeo Liu #define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L 2639a5a25977SLeo Liu #define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L 2640a5a25977SLeo Liu #define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L 2641a5a25977SLeo Liu #define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L 2642a5a25977SLeo Liu #define UVD_CGC_GATE__WCB_MASK 0x00020000L 2643a5a25977SLeo Liu #define UVD_CGC_GATE__VCPU_MASK 0x00040000L 2644a5a25977SLeo Liu #define UVD_CGC_GATE__MMSCH_MASK 0x00100000L 2645a5a25977SLeo Liu //UVD_CGC_STATUS 2646a5a25977SLeo Liu #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 2647a5a25977SLeo Liu #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 2648a5a25977SLeo Liu #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 2649a5a25977SLeo Liu #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 2650a5a25977SLeo Liu #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 2651a5a25977SLeo Liu #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 2652a5a25977SLeo Liu #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 2653a5a25977SLeo Liu #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 2654a5a25977SLeo Liu #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 2655a5a25977SLeo Liu #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 2656a5a25977SLeo Liu #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 2657a5a25977SLeo Liu #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 2658a5a25977SLeo Liu #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 2659a5a25977SLeo Liu #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 2660a5a25977SLeo Liu #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 2661a5a25977SLeo Liu #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 2662a5a25977SLeo Liu #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 2663a5a25977SLeo Liu #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 2664a5a25977SLeo Liu #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 2665a5a25977SLeo Liu #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 2666a5a25977SLeo Liu #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 2667a5a25977SLeo Liu #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 2668a5a25977SLeo Liu #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 2669a5a25977SLeo Liu #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 2670a5a25977SLeo Liu #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 2671a5a25977SLeo Liu #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 2672a5a25977SLeo Liu #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 2673a5a25977SLeo Liu #define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b 2674a5a25977SLeo Liu #define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c 2675a5a25977SLeo Liu #define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d 2676a5a25977SLeo Liu #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 2677a5a25977SLeo Liu #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L 2678a5a25977SLeo Liu #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L 2679a5a25977SLeo Liu #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L 2680a5a25977SLeo Liu #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L 2681a5a25977SLeo Liu #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L 2682a5a25977SLeo Liu #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L 2683a5a25977SLeo Liu #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L 2684a5a25977SLeo Liu #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L 2685a5a25977SLeo Liu #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L 2686a5a25977SLeo Liu #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L 2687a5a25977SLeo Liu #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L 2688a5a25977SLeo Liu #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L 2689a5a25977SLeo Liu #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L 2690a5a25977SLeo Liu #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L 2691a5a25977SLeo Liu #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L 2692a5a25977SLeo Liu #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L 2693a5a25977SLeo Liu #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L 2694a5a25977SLeo Liu #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L 2695a5a25977SLeo Liu #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L 2696a5a25977SLeo Liu #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L 2697a5a25977SLeo Liu #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L 2698a5a25977SLeo Liu #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L 2699a5a25977SLeo Liu #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L 2700a5a25977SLeo Liu #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L 2701a5a25977SLeo Liu #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L 2702a5a25977SLeo Liu #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L 2703a5a25977SLeo Liu #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L 2704a5a25977SLeo Liu #define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L 2705a5a25977SLeo Liu #define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L 2706a5a25977SLeo Liu #define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L 2707a5a25977SLeo Liu #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L 2708a5a25977SLeo Liu //UVD_CGC_CTRL 2709a5a25977SLeo Liu #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 2710a5a25977SLeo Liu #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 2711a5a25977SLeo Liu #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 2712a5a25977SLeo Liu #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 2713a5a25977SLeo Liu #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 2714a5a25977SLeo Liu #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 2715a5a25977SLeo Liu #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 2716a5a25977SLeo Liu #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 2717a5a25977SLeo Liu #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 2718a5a25977SLeo Liu #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 2719a5a25977SLeo Liu #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 2720a5a25977SLeo Liu #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 2721a5a25977SLeo Liu #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 2722a5a25977SLeo Liu #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 2723a5a25977SLeo Liu #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 2724a5a25977SLeo Liu #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 2725a5a25977SLeo Liu #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 2726a5a25977SLeo Liu #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 2727a5a25977SLeo Liu #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 2728a5a25977SLeo Liu #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 2729a5a25977SLeo Liu #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 2730a5a25977SLeo Liu #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 2731a5a25977SLeo Liu #define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f 2732a5a25977SLeo Liu #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 2733a5a25977SLeo Liu #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 2734a5a25977SLeo Liu #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L 2735a5a25977SLeo Liu #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L 2736a5a25977SLeo Liu #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L 2737a5a25977SLeo Liu #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L 2738a5a25977SLeo Liu #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L 2739a5a25977SLeo Liu #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L 2740a5a25977SLeo Liu #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L 2741a5a25977SLeo Liu #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L 2742a5a25977SLeo Liu #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L 2743a5a25977SLeo Liu #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L 2744a5a25977SLeo Liu #define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L 2745a5a25977SLeo Liu #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L 2746a5a25977SLeo Liu #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L 2747a5a25977SLeo Liu #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L 2748a5a25977SLeo Liu #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L 2749a5a25977SLeo Liu #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L 2750a5a25977SLeo Liu #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L 2751a5a25977SLeo Liu #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L 2752a5a25977SLeo Liu #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L 2753a5a25977SLeo Liu #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L 2754a5a25977SLeo Liu #define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L 2755a5a25977SLeo Liu //UVD_CGC_UDEC_STATUS 2756a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 2757a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 2758a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 2759a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 2760a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 2761a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 2762a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 2763a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 2764a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 2765a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 2766a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 2767a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 2768a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 2769a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 2770a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 2771a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L 2772a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L 2773a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L 2774a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L 2775a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L 2776a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L 2777a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L 2778a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L 2779a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L 2780a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L 2781a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L 2782a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L 2783a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L 2784a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L 2785a5a25977SLeo Liu #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L 2786a5a25977SLeo Liu //UVD_SUVD_CGC_GATE 2787a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 2788a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 2789a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 2790a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 2791a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 2792a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 2793a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 2794a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 2795a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 2796a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 2797a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 2798a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 2799a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 2800a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 2801a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 2802a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf 2803a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 2804a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 2805a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 2806a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 2807a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 2808a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 2809a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 2810a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 2811a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 2812a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 2813a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 28141b51916bSAlex Deucher #define UVD_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 2815a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 2816a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 28171b51916bSAlex Deucher #define UVD_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 2818a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 2819a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L 2820a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L 2821a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L 2822a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L 2823a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L 2824a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 2825a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 2826a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 2827a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 2828a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 2829a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 2830a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 2831a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 2832a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 2833a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 2834a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L 2835a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L 2836a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 2837a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 2838a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L 2839a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 2840a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 2841a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 2842a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 2843a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 2844a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L 2845a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 28461b51916bSAlex Deucher #define UVD_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 2847a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 2848a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 28491b51916bSAlex Deucher #define UVD_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 2850a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 2851a5a25977SLeo Liu //UVD_SUVD_CGC_STATUS 2852a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 2853a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 2854a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 2855a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 2856a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 2857a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 2858a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 2859a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 2860a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 2861a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 2862a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 2863a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 2864a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 2865a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 2866a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe 2867a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf 2868a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 2869a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 2870a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 2871a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 2872a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 2873a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 2874a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 2875a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 2876a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 2877a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 2878a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a 2879a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b 2880a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c 2881a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SAOE_DCLK__SHIFT 0x1d 28821b51916bSAlex Deucher #define UVD_SUVD_CGC_STATUS__SRE_AV1_VCLK__SHIFT 0x1e 28831b51916bSAlex Deucher #define UVD_SUVD_CGC_STATUS__SCM_AV1_DCLK__SHIFT 0x1f 2884a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L 2885a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L 2886a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L 2887a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L 2888a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L 2889a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L 2890a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L 2891a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L 2892a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L 2893a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L 2894a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L 2895a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L 2896a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L 2897a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L 2898a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L 2899a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L 2900a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L 2901a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L 2902a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L 2903a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L 2904a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L 2905a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L 2906a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L 2907a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L 2908a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L 2909a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L 2910a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L 2911a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L 2912a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L 2913a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS__SAOE_DCLK_MASK 0x20000000L 29141b51916bSAlex Deucher #define UVD_SUVD_CGC_STATUS__SRE_AV1_VCLK_MASK 0x40000000L 29151b51916bSAlex Deucher #define UVD_SUVD_CGC_STATUS__SCM_AV1_DCLK_MASK 0x80000000L 2916a5a25977SLeo Liu //UVD_SUVD_CGC_CTRL 2917a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2918a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2919a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2920a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2921a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2922a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2923a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2924a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2925a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2926a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2927a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2928a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2929a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2930a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2931a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 29321b51916bSAlex Deucher #define UVD_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 29331b51916bSAlex Deucher #define UVD_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2934a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2935a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2936a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2937a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2938a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2939a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2940a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2941a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2942a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2943a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2944a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2945a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2946a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2947a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2948a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2949a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2950a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2951a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 29521b51916bSAlex Deucher #define UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 29531b51916bSAlex Deucher #define UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2954a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2955a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2956a5a25977SLeo Liu #define UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2957a5a25977SLeo Liu //UVD_GPCOM_VCPU_CMD 2958a5a25977SLeo Liu #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 2959a5a25977SLeo Liu #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 2960a5a25977SLeo Liu #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 2961a5a25977SLeo Liu #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L 2962a5a25977SLeo Liu #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL 2963a5a25977SLeo Liu #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L 2964a5a25977SLeo Liu //UVD_GPCOM_VCPU_DATA0 2965a5a25977SLeo Liu #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 2966a5a25977SLeo Liu #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL 2967a5a25977SLeo Liu //UVD_GPCOM_VCPU_DATA1 2968a5a25977SLeo Liu #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 2969a5a25977SLeo Liu #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL 2970a5a25977SLeo Liu //UVD_GPCOM_SYS_CMD 2971a5a25977SLeo Liu #define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 2972a5a25977SLeo Liu #define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 2973a5a25977SLeo Liu #define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f 2974a5a25977SLeo Liu #define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L 2975a5a25977SLeo Liu #define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL 2976a5a25977SLeo Liu #define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L 2977a5a25977SLeo Liu //UVD_GPCOM_SYS_DATA0 2978a5a25977SLeo Liu #define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 2979a5a25977SLeo Liu #define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL 2980a5a25977SLeo Liu //UVD_GPCOM_SYS_DATA1 2981a5a25977SLeo Liu #define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 2982a5a25977SLeo Liu #define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL 2983a5a25977SLeo Liu //UVD_VCPU_INT_EN 2984a5a25977SLeo Liu #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 2985a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 2986a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 2987a5a25977SLeo Liu #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3 2988a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4 2989a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5 2990a5a25977SLeo Liu #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 2991a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7 2992a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9 2993a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa 2994a5a25977SLeo Liu #define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb 2995a5a25977SLeo Liu #define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc 2996a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SUVD_EN__SHIFT 0xf 2997a5a25977SLeo Liu #define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10 2998a5a25977SLeo Liu #define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11 2999a5a25977SLeo Liu #define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12 3000a5a25977SLeo Liu #define UVD_VCPU_INT_EN__CNN_3D_BLOCK_DONE_INT_EN__SHIFT 0x13 3001a5a25977SLeo Liu #define UVD_VCPU_INT_EN__CNN_MIF_DMA_DONE_INT_EN__SHIFT 0x15 3002a5a25977SLeo Liu #define UVD_VCPU_INT_EN__CNN_FEATURE_THRESHOLD_DONE_INT_EN__SHIFT 0x16 3003a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 3004a5a25977SLeo Liu #define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18 3005a5a25977SLeo Liu #define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19 3006a5a25977SLeo Liu #define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a 3007a5a25977SLeo Liu #define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b 3008a5a25977SLeo Liu #define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 3009a5a25977SLeo Liu #define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 3010a5a25977SLeo Liu #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e 3011a5a25977SLeo Liu #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f 3012a5a25977SLeo Liu #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 3013a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 3014a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 3015a5a25977SLeo Liu #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L 3016a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L 3017a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L 3018a5a25977SLeo Liu #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 3019a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L 3020a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L 3021a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L 3022a5a25977SLeo Liu #define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L 3023a5a25977SLeo Liu #define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L 3024a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SUVD_EN_MASK 0x00008000L 3025a5a25977SLeo Liu #define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L 3026a5a25977SLeo Liu #define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L 3027a5a25977SLeo Liu #define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L 3028a5a25977SLeo Liu #define UVD_VCPU_INT_EN__CNN_3D_BLOCK_DONE_INT_EN_MASK 0x00080000L 3029a5a25977SLeo Liu #define UVD_VCPU_INT_EN__CNN_MIF_DMA_DONE_INT_EN_MASK 0x00200000L 3030a5a25977SLeo Liu #define UVD_VCPU_INT_EN__CNN_FEATURE_THRESHOLD_DONE_INT_EN_MASK 0x00400000L 3031a5a25977SLeo Liu #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 3032a5a25977SLeo Liu #define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L 3033a5a25977SLeo Liu #define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L 3034a5a25977SLeo Liu #define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L 3035a5a25977SLeo Liu #define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L 3036a5a25977SLeo Liu #define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 3037a5a25977SLeo Liu #define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 3038a5a25977SLeo Liu #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L 3039a5a25977SLeo Liu #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L 3040a5a25977SLeo Liu //UVD_VCPU_INT_STATUS 3041a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 3042a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 3043a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 3044a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT__SHIFT 0x3 3045a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SW_RB1_INT__SHIFT 0x4 3046a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SW_RB2_INT__SHIFT 0x5 3047a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 3048a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SW_RB3_INT__SHIFT 0x7 3049a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SW_RB4_INT__SHIFT 0x9 3050a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SW_RB5_INT__SHIFT 0xa 3051a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__LBSI_INT__SHIFT 0xb 3052a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__UDEC_INT__SHIFT 0xc 3053a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SUVD_INT__SHIFT 0xf 3054a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__RPTR_WR_INT__SHIFT 0x10 3055a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__JOB_START_INT__SHIFT 0x11 3056a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__NJ_PF_INT__SHIFT 0x12 3057a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__CNN_3D_BLOCK_DONE_INT__SHIFT 0x13 3058a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__GPCOM_INT__SHIFT 0x14 3059a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__CNN_MIF_DMA_DONE_INT__SHIFT 0x15 3060a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__CNN_FEATURE_THRESHOLD_DONE_INT__SHIFT 0x16 3061a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 3062a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__IDCT_INT__SHIFT 0x18 3063a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__MPRD_INT__SHIFT 0x19 3064a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__AVM_INT__SHIFT 0x1a 3065a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 3066a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__MIF_HWINT__SHIFT 0x1c 3067a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 3068a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT__SHIFT 0x1e 3069a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT__SHIFT 0x1f 3070a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 3071a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 3072a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 3073a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT_MASK 0x00000008L 3074a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SW_RB1_INT_MASK 0x00000010L 3075a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SW_RB2_INT_MASK 0x00000020L 3076a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 3077a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SW_RB3_INT_MASK 0x00000080L 3078a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SW_RB4_INT_MASK 0x00000200L 3079a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SW_RB5_INT_MASK 0x00000400L 3080a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__LBSI_INT_MASK 0x00000800L 3081a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__UDEC_INT_MASK 0x00001000L 3082a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SUVD_INT_MASK 0x00008000L 3083a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__RPTR_WR_INT_MASK 0x00010000L 3084a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__JOB_START_INT_MASK 0x00020000L 3085a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__NJ_PF_INT_MASK 0x00040000L 3086a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__CNN_3D_BLOCK_DONE_INT_MASK 0x00080000L 3087a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__GPCOM_INT_MASK 0x00100000L 3088a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__CNN_MIF_DMA_DONE_INT_MASK 0x00200000L 3089a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__CNN_FEATURE_THRESHOLD_DONE_INT_MASK 0x00400000L 3090a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 3091a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__IDCT_INT_MASK 0x01000000L 3092a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__MPRD_INT_MASK 0x02000000L 3093a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__AVM_INT_MASK 0x04000000L 3094a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 3095a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__MIF_HWINT_MASK 0x10000000L 3096a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 3097a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT_MASK 0x40000000L 3098a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT_MASK 0x80000000L 3099a5a25977SLeo Liu //UVD_VCPU_INT_ACK 3100a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 3101a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 3102a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 3103a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3 3104a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4 3105a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5 3106a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 3107a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7 3108a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9 3109a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa 3110a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb 3111a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc 3112a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SUVD_ACK__SHIFT 0xf 3113a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10 3114a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11 3115a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12 3116a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__CNN_3D_BLOCK_DONE_INT_ACK__SHIFT 0x13 3117a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__CNN_MIF_DMA_DONE_INT_ACK__SHIFT 0x15 3118a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__CNN_FEATURE_THRESHOLD_DONE_INT_ACK__SHIFT 0x16 3119a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 3120a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18 3121a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19 3122a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a 3123a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 3124a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 3125a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 3126a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e 3127a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f 3128a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 3129a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 3130a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 3131a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L 3132a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L 3133a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L 3134a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 3135a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L 3136a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L 3137a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L 3138a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L 3139a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L 3140a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SUVD_ACK_MASK 0x00008000L 3141a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L 3142a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L 3143a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L 3144a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__CNN_3D_BLOCK_DONE_INT_ACK_MASK 0x00080000L 3145a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__CNN_MIF_DMA_DONE_INT_ACK_MASK 0x00200000L 3146a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__CNN_FEATURE_THRESHOLD_DONE_INT_ACK_MASK 0x00400000L 3147a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 3148a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L 3149a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L 3150a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L 3151a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 3152a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 3153a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 3154a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L 3155a5a25977SLeo Liu #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L 3156a5a25977SLeo Liu //UVD_VCPU_INT_ROUTE 3157a5a25977SLeo Liu #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0 3158a5a25977SLeo Liu #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1 3159a5a25977SLeo Liu #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2 3160a5a25977SLeo Liu #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L 3161a5a25977SLeo Liu #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L 3162a5a25977SLeo Liu #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L 3163a5a25977SLeo Liu //UVD_DRV_FW_MSG 3164a5a25977SLeo Liu #define UVD_DRV_FW_MSG__MSG__SHIFT 0x0 3165a5a25977SLeo Liu #define UVD_DRV_FW_MSG__MSG_MASK 0xFFFFFFFFL 3166a5a25977SLeo Liu //UVD_FW_DRV_MSG_ACK 3167a5a25977SLeo Liu #define UVD_FW_DRV_MSG_ACK__ACK__SHIFT 0x0 3168a5a25977SLeo Liu #define UVD_FW_DRV_MSG_ACK__ACK_MASK 0x00000001L 3169a5a25977SLeo Liu //UVD_SUVD_INT_EN 3170a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN__SHIFT 0x0 3171a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SRE_ERR_INT_EN__SHIFT 0x5 3172a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN__SHIFT 0x6 3173a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SIT_ERR_INT_EN__SHIFT 0xb 3174a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN__SHIFT 0xc 3175a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SMP_ERR_INT_EN__SHIFT 0x11 3176a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN__SHIFT 0x12 3177a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SCM_ERR_INT_EN__SHIFT 0x17 3178a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN__SHIFT 0x18 3179a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SDB_ERR_INT_EN__SHIFT 0x1d 3180a5a25977SLeo Liu #define UVD_SUVD_INT_EN__FBC_ERR_INT_EN__SHIFT 0x1e 3181a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN_MASK 0x0000001FL 3182a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SRE_ERR_INT_EN_MASK 0x00000020L 3183a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN_MASK 0x000007C0L 3184a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SIT_ERR_INT_EN_MASK 0x00000800L 3185a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN_MASK 0x0001F000L 3186a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SMP_ERR_INT_EN_MASK 0x00020000L 3187a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN_MASK 0x007C0000L 3188a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SCM_ERR_INT_EN_MASK 0x00800000L 3189a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN_MASK 0x1F000000L 3190a5a25977SLeo Liu #define UVD_SUVD_INT_EN__SDB_ERR_INT_EN_MASK 0x20000000L 3191a5a25977SLeo Liu #define UVD_SUVD_INT_EN__FBC_ERR_INT_EN_MASK 0x40000000L 3192a5a25977SLeo Liu //UVD_SUVD_INT_STATUS 3193a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SRE_FUNC_INT__SHIFT 0x0 3194a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SRE_ERR_INT__SHIFT 0x5 3195a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SIT_FUNC_INT__SHIFT 0x6 3196a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SIT_ERR_INT__SHIFT 0xb 3197a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SMP_FUNC_INT__SHIFT 0xc 3198a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SMP_ERR_INT__SHIFT 0x11 3199a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SCM_FUNC_INT__SHIFT 0x12 3200a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SCM_ERR_INT__SHIFT 0x17 3201a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SDB_FUNC_INT__SHIFT 0x18 3202a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SDB_ERR_INT__SHIFT 0x1d 3203a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__FBC_ERR_INT__SHIFT 0x1e 3204a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SRE_FUNC_INT_MASK 0x0000001FL 3205a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SRE_ERR_INT_MASK 0x00000020L 3206a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SIT_FUNC_INT_MASK 0x000007C0L 3207a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SIT_ERR_INT_MASK 0x00000800L 3208a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SMP_FUNC_INT_MASK 0x0001F000L 3209a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SMP_ERR_INT_MASK 0x00020000L 3210a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SCM_FUNC_INT_MASK 0x007C0000L 3211a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SCM_ERR_INT_MASK 0x00800000L 3212a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SDB_FUNC_INT_MASK 0x1F000000L 3213a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__SDB_ERR_INT_MASK 0x20000000L 3214a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS__FBC_ERR_INT_MASK 0x40000000L 3215a5a25977SLeo Liu //UVD_SUVD_INT_ACK 3216a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK__SHIFT 0x0 3217a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK__SHIFT 0x5 3218a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK__SHIFT 0x6 3219a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK__SHIFT 0xb 3220a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK__SHIFT 0xc 3221a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK__SHIFT 0x11 3222a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK__SHIFT 0x12 3223a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK__SHIFT 0x17 3224a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK__SHIFT 0x18 3225a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK__SHIFT 0x1d 3226a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__FBC_ERR_INT_ACK__SHIFT 0x1e 3227a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK_MASK 0x0000001FL 3228a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK_MASK 0x00000020L 3229a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK_MASK 0x000007C0L 3230a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK_MASK 0x00000800L 3231a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK_MASK 0x0001F000L 3232a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK_MASK 0x00020000L 3233a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK_MASK 0x007C0000L 3234a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK_MASK 0x00800000L 3235a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK_MASK 0x1F000000L 3236a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK_MASK 0x20000000L 3237a5a25977SLeo Liu #define UVD_SUVD_INT_ACK__FBC_ERR_INT_ACK_MASK 0x40000000L 3238a5a25977SLeo Liu //UVD_ENC_VCPU_INT_EN 3239a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0 3240a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1 3241a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2 3242a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L 3243a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L 3244a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L 3245a5a25977SLeo Liu //UVD_ENC_VCPU_INT_STATUS 3246a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT__SHIFT 0x0 3247a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT__SHIFT 0x1 3248a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT__SHIFT 0x2 3249a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT_MASK 0x00000001L 3250a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT_MASK 0x00000002L 3251a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT_MASK 0x00000004L 3252a5a25977SLeo Liu //UVD_ENC_VCPU_INT_ACK 3253a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0 3254a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1 3255a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2 3256a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L 3257a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L 3258a5a25977SLeo Liu #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L 3259a5a25977SLeo Liu //UVD_MASTINT_EN 3260a5a25977SLeo Liu #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 3261a5a25977SLeo Liu #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 3262a5a25977SLeo Liu #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 3263a5a25977SLeo Liu #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 3264a5a25977SLeo Liu #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 3265a5a25977SLeo Liu #define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L 3266a5a25977SLeo Liu #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L 3267a5a25977SLeo Liu #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 3268a5a25977SLeo Liu //UVD_SYS_INT_EN 3269a5a25977SLeo Liu #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 3270a5a25977SLeo Liu #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 3271a5a25977SLeo Liu #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 3272a5a25977SLeo Liu #define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3 3273a5a25977SLeo Liu #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 3274a5a25977SLeo Liu #define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb 3275a5a25977SLeo Liu #define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc 3276a5a25977SLeo Liu #define UVD_SYS_INT_EN__SUVD_EN__SHIFT 0xf 3277a5a25977SLeo Liu #define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10 3278a5a25977SLeo Liu #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 3279a5a25977SLeo Liu #define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18 3280a5a25977SLeo Liu #define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19 3281a5a25977SLeo Liu #define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b 3282a5a25977SLeo Liu #define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 3283a5a25977SLeo Liu #define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 3284a5a25977SLeo Liu #define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f 3285a5a25977SLeo Liu #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 3286a5a25977SLeo Liu #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 3287a5a25977SLeo Liu #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 3288a5a25977SLeo Liu #define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L 3289a5a25977SLeo Liu #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 3290a5a25977SLeo Liu #define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L 3291a5a25977SLeo Liu #define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L 3292a5a25977SLeo Liu #define UVD_SYS_INT_EN__SUVD_EN_MASK 0x00008000L 3293a5a25977SLeo Liu #define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L 3294a5a25977SLeo Liu #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 3295a5a25977SLeo Liu #define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L 3296a5a25977SLeo Liu #define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L 3297a5a25977SLeo Liu #define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L 3298a5a25977SLeo Liu #define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 3299a5a25977SLeo Liu #define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 3300a5a25977SLeo Liu #define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L 3301a5a25977SLeo Liu //UVD_SYS_INT_STATUS 3302a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 3303a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 3304a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 3305a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3 3306a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 3307a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb 3308a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc 3309a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__SUVD_INT__SHIFT 0xf 3310a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10 3311a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12 3312a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 3313a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18 3314a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19 3315a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 3316a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c 3317a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 3318a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f 3319a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 3320a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 3321a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 3322a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L 3323a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 3324a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L 3325a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L 3326a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__SUVD_INT_MASK 0x00008000L 3327a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L 3328a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L 3329a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 3330a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L 3331a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L 3332a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 3333a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L 3334a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 3335a5a25977SLeo Liu #define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L 3336a5a25977SLeo Liu //UVD_SYS_INT_ACK 3337a5a25977SLeo Liu #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 3338a5a25977SLeo Liu #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 3339a5a25977SLeo Liu #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 3340a5a25977SLeo Liu #define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3 3341a5a25977SLeo Liu #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 3342a5a25977SLeo Liu #define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb 3343a5a25977SLeo Liu #define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc 3344a5a25977SLeo Liu #define UVD_SYS_INT_ACK__SUVD_ACK__SHIFT 0xf 3345a5a25977SLeo Liu #define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10 3346a5a25977SLeo Liu #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 3347a5a25977SLeo Liu #define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18 3348a5a25977SLeo Liu #define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19 3349a5a25977SLeo Liu #define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 3350a5a25977SLeo Liu #define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 3351a5a25977SLeo Liu #define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 3352a5a25977SLeo Liu #define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f 3353a5a25977SLeo Liu #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 3354a5a25977SLeo Liu #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 3355a5a25977SLeo Liu #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 3356a5a25977SLeo Liu #define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L 3357a5a25977SLeo Liu #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 3358a5a25977SLeo Liu #define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L 3359a5a25977SLeo Liu #define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L 3360a5a25977SLeo Liu #define UVD_SYS_INT_ACK__SUVD_ACK_MASK 0x00008000L 3361a5a25977SLeo Liu #define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L 3362a5a25977SLeo Liu #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 3363a5a25977SLeo Liu #define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L 3364a5a25977SLeo Liu #define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L 3365a5a25977SLeo Liu #define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 3366a5a25977SLeo Liu #define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 3367a5a25977SLeo Liu #define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 3368a5a25977SLeo Liu #define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L 3369a5a25977SLeo Liu //UVD_JOB_DONE 3370a5a25977SLeo Liu #define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0 3371a5a25977SLeo Liu #define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L 3372a5a25977SLeo Liu //UVD_CBUF_ID 3373a5a25977SLeo Liu #define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0 3374a5a25977SLeo Liu #define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL 3375a5a25977SLeo Liu //UVD_CONTEXT_ID 3376a5a25977SLeo Liu #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 3377a5a25977SLeo Liu #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL 3378a5a25977SLeo Liu //UVD_CONTEXT_ID2 3379a5a25977SLeo Liu #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 3380a5a25977SLeo Liu #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL 3381a5a25977SLeo Liu //UVD_NO_OP 3382a5a25977SLeo Liu #define UVD_NO_OP__NO_OP__SHIFT 0x0 3383a5a25977SLeo Liu #define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL 3384a5a25977SLeo Liu //UVD_RB_BASE_LO 3385a5a25977SLeo Liu #define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3386a5a25977SLeo Liu #define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3387a5a25977SLeo Liu //UVD_RB_BASE_HI 3388a5a25977SLeo Liu #define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3389a5a25977SLeo Liu #define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3390a5a25977SLeo Liu //UVD_RB_SIZE 3391a5a25977SLeo Liu #define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 3392a5a25977SLeo Liu #define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3393a5a25977SLeo Liu //UVD_RB_RPTR 3394a5a25977SLeo Liu #define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 3395a5a25977SLeo Liu #define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 3396a5a25977SLeo Liu //UVD_RB_WPTR 3397a5a25977SLeo Liu #define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 3398a5a25977SLeo Liu #define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 3399a5a25977SLeo Liu //UVD_RB_BASE_LO2 3400a5a25977SLeo Liu #define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 3401a5a25977SLeo Liu #define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L 3402a5a25977SLeo Liu //UVD_RB_BASE_HI2 3403a5a25977SLeo Liu #define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 3404a5a25977SLeo Liu #define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL 3405a5a25977SLeo Liu //UVD_RB_SIZE2 3406a5a25977SLeo Liu #define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 3407a5a25977SLeo Liu #define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L 3408a5a25977SLeo Liu //UVD_RB_RPTR2 3409a5a25977SLeo Liu #define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 3410a5a25977SLeo Liu #define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L 3411a5a25977SLeo Liu //UVD_RB_WPTR2 3412a5a25977SLeo Liu #define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 3413a5a25977SLeo Liu #define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L 3414a5a25977SLeo Liu //UVD_RB_BASE_LO3 3415a5a25977SLeo Liu #define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 3416a5a25977SLeo Liu #define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L 3417a5a25977SLeo Liu //UVD_RB_BASE_HI3 3418a5a25977SLeo Liu #define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 3419a5a25977SLeo Liu #define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL 3420a5a25977SLeo Liu //UVD_RB_SIZE3 3421a5a25977SLeo Liu #define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 3422a5a25977SLeo Liu #define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L 3423a5a25977SLeo Liu //UVD_RB_RPTR3 3424a5a25977SLeo Liu #define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 3425a5a25977SLeo Liu #define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L 3426a5a25977SLeo Liu //UVD_RB_WPTR3 3427a5a25977SLeo Liu #define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 3428a5a25977SLeo Liu #define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L 3429a5a25977SLeo Liu //UVD_RB_BASE_LO4 3430a5a25977SLeo Liu #define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 3431a5a25977SLeo Liu #define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L 3432a5a25977SLeo Liu //UVD_RB_BASE_HI4 3433a5a25977SLeo Liu #define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 3434a5a25977SLeo Liu #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL 3435a5a25977SLeo Liu //UVD_RB_SIZE4 3436a5a25977SLeo Liu #define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 3437a5a25977SLeo Liu #define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L 3438a5a25977SLeo Liu //UVD_RB_RPTR4 3439a5a25977SLeo Liu #define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 3440a5a25977SLeo Liu #define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L 3441a5a25977SLeo Liu //UVD_RB_WPTR4 3442a5a25977SLeo Liu #define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 3443a5a25977SLeo Liu #define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L 3444a5a25977SLeo Liu //UVD_OUT_RB_BASE_LO 3445a5a25977SLeo Liu #define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3446a5a25977SLeo Liu #define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3447a5a25977SLeo Liu //UVD_OUT_RB_BASE_HI 3448a5a25977SLeo Liu #define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3449a5a25977SLeo Liu #define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3450a5a25977SLeo Liu //UVD_OUT_RB_SIZE 3451a5a25977SLeo Liu #define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4 3452a5a25977SLeo Liu #define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3453a5a25977SLeo Liu //UVD_OUT_RB_RPTR 3454a5a25977SLeo Liu #define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4 3455a5a25977SLeo Liu #define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 3456a5a25977SLeo Liu //UVD_OUT_RB_WPTR 3457a5a25977SLeo Liu #define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4 3458a5a25977SLeo Liu #define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 3459a5a25977SLeo Liu //UVD_IOV_ACTIVE_FCN_ID 3460a5a25977SLeo Liu #define UVD_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 3461a5a25977SLeo Liu #define UVD_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 3462a5a25977SLeo Liu #define UVD_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000003FL 3463a5a25977SLeo Liu #define UVD_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L 3464a5a25977SLeo Liu //UVD_IOV_MAILBOX 3465a5a25977SLeo Liu #define UVD_IOV_MAILBOX__MAILBOX__SHIFT 0x0 3466a5a25977SLeo Liu #define UVD_IOV_MAILBOX__MAILBOX_MASK 0xFFFFFFFFL 3467a5a25977SLeo Liu //UVD_IOV_MAILBOX_RESP 3468a5a25977SLeo Liu #define UVD_IOV_MAILBOX_RESP__RESP__SHIFT 0x0 3469a5a25977SLeo Liu #define UVD_IOV_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 3470a5a25977SLeo Liu //UVD_RB_ARB_CTRL 3471a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0 3472a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1 3473a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2 3474a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3 3475a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4 3476a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5 3477a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6 3478a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7 3479a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8 3480a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L 3481a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L 3482a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L 3483a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L 3484a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L 3485a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L 3486a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L 3487a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L 3488a5a25977SLeo Liu #define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L 3489a5a25977SLeo Liu //UVD_CTX_INDEX 3490a5a25977SLeo Liu #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 3491a5a25977SLeo Liu #define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL 3492a5a25977SLeo Liu //UVD_CTX_DATA 3493a5a25977SLeo Liu #define UVD_CTX_DATA__DATA__SHIFT 0x0 3494a5a25977SLeo Liu #define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL 3495a5a25977SLeo Liu //UVD_CXW_WR 3496a5a25977SLeo Liu #define UVD_CXW_WR__DAT__SHIFT 0x0 3497a5a25977SLeo Liu #define UVD_CXW_WR__STAT__SHIFT 0x1f 3498a5a25977SLeo Liu #define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL 3499a5a25977SLeo Liu #define UVD_CXW_WR__STAT_MASK 0x80000000L 3500a5a25977SLeo Liu //UVD_CXW_WR_INT_ID 3501a5a25977SLeo Liu #define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0 3502a5a25977SLeo Liu #define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL 3503a5a25977SLeo Liu //UVD_CXW_WR_INT_CTX_ID 3504a5a25977SLeo Liu #define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0 3505a5a25977SLeo Liu #define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL 3506a5a25977SLeo Liu //UVD_CXW_INT_ID 3507a5a25977SLeo Liu #define UVD_CXW_INT_ID__ID__SHIFT 0x0 3508a5a25977SLeo Liu #define UVD_CXW_INT_ID__ID_MASK 0x000000FFL 3509a5a25977SLeo Liu //UVD_MPEG2_ERROR 3510a5a25977SLeo Liu #define UVD_MPEG2_ERROR__STATUS__SHIFT 0x0 3511a5a25977SLeo Liu #define UVD_MPEG2_ERROR__STATUS_MASK 0xFFFFFFFFL 3512a5a25977SLeo Liu //UVD_TOP_CTRL 3513a5a25977SLeo Liu #define UVD_TOP_CTRL__STANDARD__SHIFT 0x0 3514a5a25977SLeo Liu #define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4 3515a5a25977SLeo Liu #define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL 3516a5a25977SLeo Liu #define UVD_TOP_CTRL__STD_VERSION_MASK 0x000000F0L 3517a5a25977SLeo Liu //UVD_YBASE 3518a5a25977SLeo Liu #define UVD_YBASE__DUM__SHIFT 0x0 3519a5a25977SLeo Liu #define UVD_YBASE__DUM_MASK 0xFFFFFFFFL 3520a5a25977SLeo Liu //UVD_UVBASE 3521a5a25977SLeo Liu #define UVD_UVBASE__DUM__SHIFT 0x0 3522a5a25977SLeo Liu #define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL 3523a5a25977SLeo Liu //UVD_PITCH 3524a5a25977SLeo Liu #define UVD_PITCH__DUM__SHIFT 0x0 3525a5a25977SLeo Liu #define UVD_PITCH__DUM_MASK 0xFFFFFFFFL 3526a5a25977SLeo Liu //UVD_WIDTH 3527a5a25977SLeo Liu #define UVD_WIDTH__DUM__SHIFT 0x0 3528a5a25977SLeo Liu #define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL 3529a5a25977SLeo Liu //UVD_HEIGHT 3530a5a25977SLeo Liu #define UVD_HEIGHT__DUM__SHIFT 0x0 3531a5a25977SLeo Liu #define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL 3532a5a25977SLeo Liu //UVD_PICCOUNT 3533a5a25977SLeo Liu #define UVD_PICCOUNT__DUM__SHIFT 0x0 3534a5a25977SLeo Liu #define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL 3535a5a25977SLeo Liu //UVD_MPRD_INITIAL_XY 3536a5a25977SLeo Liu #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X__SHIFT 0x0 3537a5a25977SLeo Liu #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y__SHIFT 0x10 3538a5a25977SLeo Liu #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X_MASK 0x00000FFFL 3539a5a25977SLeo Liu #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y_MASK 0x0FFF0000L 3540a5a25977SLeo Liu //UVD_MPEG2_CTRL 3541a5a25977SLeo Liu #define UVD_MPEG2_CTRL__EN__SHIFT 0x0 3542a5a25977SLeo Liu #define UVD_MPEG2_CTRL__TRICK_MODE__SHIFT 0x1 3543a5a25977SLeo Liu #define UVD_MPEG2_CTRL__NUM_MB_PER_JOB__SHIFT 0x10 3544a5a25977SLeo Liu #define UVD_MPEG2_CTRL__EN_MASK 0x00000001L 3545a5a25977SLeo Liu #define UVD_MPEG2_CTRL__TRICK_MODE_MASK 0x00000002L 3546a5a25977SLeo Liu #define UVD_MPEG2_CTRL__NUM_MB_PER_JOB_MASK 0xFFFF0000L 3547a5a25977SLeo Liu //UVD_MB_CTL_BUF_BASE 3548a5a25977SLeo Liu #define UVD_MB_CTL_BUF_BASE__BASE__SHIFT 0x0 3549a5a25977SLeo Liu #define UVD_MB_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL 3550a5a25977SLeo Liu //UVD_PIC_CTL_BUF_BASE 3551a5a25977SLeo Liu #define UVD_PIC_CTL_BUF_BASE__BASE__SHIFT 0x0 3552a5a25977SLeo Liu #define UVD_PIC_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL 3553a5a25977SLeo Liu //UVD_DXVA_BUF_SIZE 3554a5a25977SLeo Liu #define UVD_DXVA_BUF_SIZE__PIC_SIZE__SHIFT 0x0 3555a5a25977SLeo Liu #define UVD_DXVA_BUF_SIZE__MB_SIZE__SHIFT 0x10 3556a5a25977SLeo Liu #define UVD_DXVA_BUF_SIZE__PIC_SIZE_MASK 0x0000FFFFL 3557a5a25977SLeo Liu #define UVD_DXVA_BUF_SIZE__MB_SIZE_MASK 0xFFFF0000L 3558a5a25977SLeo Liu //UVD_SCRATCH_NP 3559a5a25977SLeo Liu #define UVD_SCRATCH_NP__DATA__SHIFT 0x0 3560a5a25977SLeo Liu #define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL 3561a5a25977SLeo Liu //UVD_CLK_SWT_HANDSHAKE 3562a5a25977SLeo Liu #define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE__SHIFT 0x0 3563a5a25977SLeo Liu #define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT__SHIFT 0x8 3564a5a25977SLeo Liu #define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE_MASK 0x00000003L 3565a5a25977SLeo Liu #define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT_MASK 0x00000300L 3566a5a25977SLeo Liu //UVD_VERSION 3567a5a25977SLeo Liu #define UVD_VERSION__VARIANT_TYPE__SHIFT 0x0 3568a5a25977SLeo Liu #define UVD_VERSION__MINOR_VERSION__SHIFT 0x8 3569a5a25977SLeo Liu #define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 3570a5a25977SLeo Liu #define UVD_VERSION__INSTANCE_ID__SHIFT 0x1c 3571a5a25977SLeo Liu #define UVD_VERSION__VARIANT_TYPE_MASK 0x000000FFL 3572a5a25977SLeo Liu #define UVD_VERSION__MINOR_VERSION_MASK 0x0000FF00L 3573a5a25977SLeo Liu #define UVD_VERSION__MAJOR_VERSION_MASK 0x0FFF0000L 3574a5a25977SLeo Liu #define UVD_VERSION__INSTANCE_ID_MASK 0xF0000000L 3575a5a25977SLeo Liu //UVD_GP_SCRATCH0 3576a5a25977SLeo Liu #define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 3577a5a25977SLeo Liu #define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL 3578a5a25977SLeo Liu //UVD_GP_SCRATCH1 3579a5a25977SLeo Liu #define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 3580a5a25977SLeo Liu #define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL 3581a5a25977SLeo Liu //UVD_GP_SCRATCH2 3582a5a25977SLeo Liu #define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 3583a5a25977SLeo Liu #define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL 3584a5a25977SLeo Liu //UVD_GP_SCRATCH3 3585a5a25977SLeo Liu #define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 3586a5a25977SLeo Liu #define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL 3587a5a25977SLeo Liu //UVD_GP_SCRATCH4 3588a5a25977SLeo Liu #define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 3589a5a25977SLeo Liu #define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL 3590a5a25977SLeo Liu //UVD_GP_SCRATCH5 3591a5a25977SLeo Liu #define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 3592a5a25977SLeo Liu #define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL 3593a5a25977SLeo Liu //UVD_GP_SCRATCH6 3594a5a25977SLeo Liu #define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 3595a5a25977SLeo Liu #define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL 3596a5a25977SLeo Liu //UVD_GP_SCRATCH7 3597a5a25977SLeo Liu #define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 3598a5a25977SLeo Liu #define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL 3599a5a25977SLeo Liu //UVD_GP_SCRATCH8 3600a5a25977SLeo Liu #define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 3601a5a25977SLeo Liu #define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL 3602a5a25977SLeo Liu //UVD_GP_SCRATCH9 3603a5a25977SLeo Liu #define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 3604a5a25977SLeo Liu #define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL 3605a5a25977SLeo Liu //UVD_GP_SCRATCH10 3606a5a25977SLeo Liu #define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 3607a5a25977SLeo Liu #define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL 3608a5a25977SLeo Liu //UVD_GP_SCRATCH11 3609a5a25977SLeo Liu #define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 3610a5a25977SLeo Liu #define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL 3611a5a25977SLeo Liu //UVD_GP_SCRATCH12 3612a5a25977SLeo Liu #define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 3613a5a25977SLeo Liu #define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL 3614a5a25977SLeo Liu //UVD_GP_SCRATCH13 3615a5a25977SLeo Liu #define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 3616a5a25977SLeo Liu #define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL 3617a5a25977SLeo Liu //UVD_GP_SCRATCH14 3618a5a25977SLeo Liu #define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 3619a5a25977SLeo Liu #define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL 3620a5a25977SLeo Liu //UVD_GP_SCRATCH15 3621a5a25977SLeo Liu #define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 3622a5a25977SLeo Liu #define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL 3623a5a25977SLeo Liu //UVD_GP_SCRATCH16 3624a5a25977SLeo Liu #define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 3625a5a25977SLeo Liu #define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL 3626a5a25977SLeo Liu //UVD_GP_SCRATCH17 3627a5a25977SLeo Liu #define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 3628a5a25977SLeo Liu #define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL 3629a5a25977SLeo Liu //UVD_GP_SCRATCH18 3630a5a25977SLeo Liu #define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 3631a5a25977SLeo Liu #define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL 3632a5a25977SLeo Liu //UVD_GP_SCRATCH19 3633a5a25977SLeo Liu #define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 3634a5a25977SLeo Liu #define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL 3635a5a25977SLeo Liu //UVD_GP_SCRATCH20 3636a5a25977SLeo Liu #define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 3637a5a25977SLeo Liu #define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL 3638a5a25977SLeo Liu //UVD_GP_SCRATCH21 3639a5a25977SLeo Liu #define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 3640a5a25977SLeo Liu #define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL 3641a5a25977SLeo Liu //UVD_GP_SCRATCH22 3642a5a25977SLeo Liu #define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 3643a5a25977SLeo Liu #define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL 3644a5a25977SLeo Liu //UVD_GP_SCRATCH23 3645a5a25977SLeo Liu #define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 3646a5a25977SLeo Liu #define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL 3647a5a25977SLeo Liu //UVD_AUDIO_RB_BASE_LO 3648a5a25977SLeo Liu #define UVD_AUDIO_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3649a5a25977SLeo Liu #define UVD_AUDIO_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3650a5a25977SLeo Liu //UVD_AUDIO_RB_BASE_HI 3651a5a25977SLeo Liu #define UVD_AUDIO_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3652a5a25977SLeo Liu #define UVD_AUDIO_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3653a5a25977SLeo Liu //UVD_AUDIO_RB_SIZE 3654a5a25977SLeo Liu #define UVD_AUDIO_RB_SIZE__RB_SIZE__SHIFT 0x4 3655a5a25977SLeo Liu #define UVD_AUDIO_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3656a5a25977SLeo Liu //UVD_AUDIO_RB_RPTR 3657a5a25977SLeo Liu #define UVD_AUDIO_RB_RPTR__RB_RPTR__SHIFT 0x4 3658a5a25977SLeo Liu #define UVD_AUDIO_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 3659a5a25977SLeo Liu //UVD_AUDIO_RB_WPTR 3660a5a25977SLeo Liu #define UVD_AUDIO_RB_WPTR__RB_WPTR__SHIFT 0x4 3661a5a25977SLeo Liu #define UVD_AUDIO_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 3662a5a25977SLeo Liu //UVD_VCPU_INT_STATUS2 3663a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS2__SW_RB6_INT__SHIFT 0x0 3664a5a25977SLeo Liu #define UVD_VCPU_INT_STATUS2__SW_RB6_INT_MASK 0x00000001L 3665a5a25977SLeo Liu //UVD_VCPU_INT_ACK2 3666a5a25977SLeo Liu #define UVD_VCPU_INT_ACK2__SW_RB6_INT_ACK__SHIFT 0x0 3667a5a25977SLeo Liu #define UVD_VCPU_INT_ACK2__SW_RB6_INT_ACK_MASK 0x00000001L 3668a5a25977SLeo Liu //UVD_VCPU_INT_EN2 3669a5a25977SLeo Liu #define UVD_VCPU_INT_EN2__SW_RB6_INT_EN__SHIFT 0x0 3670a5a25977SLeo Liu #define UVD_VCPU_INT_EN2__SW_RB6_INT_EN_MASK 0x00000001L 3671a5a25977SLeo Liu //UVD_SUVD_CGC_STATUS2 3672a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__SMPA_VCLK__SHIFT 0x0 3673a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__SMPA_DCLK__SHIFT 0x1 3674a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__MPBE1_DCLK__SHIFT 0x3 36751b51916bSAlex Deucher #define UVD_SUVD_CGC_STATUS2__SIT_AV1_DCLK__SHIFT 0x4 36761b51916bSAlex Deucher #define UVD_SUVD_CGC_STATUS2__SDB_AV1_DCLK__SHIFT 0x5 3677a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__MPC1_DCLK__SHIFT 0x6 3678a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__MPC1_SCLK__SHIFT 0x7 3679a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__MPC1_VCLK__SHIFT 0x8 3680a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__FBC_PCLK__SHIFT 0x1c 3681a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__FBC_CCLK__SHIFT 0x1d 3682a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__SMPA_VCLK_MASK 0x00000001L 3683a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__SMPA_DCLK_MASK 0x00000002L 3684a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__MPBE1_DCLK_MASK 0x00000008L 36851b51916bSAlex Deucher #define UVD_SUVD_CGC_STATUS2__SIT_AV1_DCLK_MASK 0x00000010L 36861b51916bSAlex Deucher #define UVD_SUVD_CGC_STATUS2__SDB_AV1_DCLK_MASK 0x00000020L 3687a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__MPC1_DCLK_MASK 0x00000040L 3688a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__MPC1_SCLK_MASK 0x00000080L 3689a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__MPC1_VCLK_MASK 0x00000100L 3690a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__FBC_PCLK_MASK 0x10000000L 3691a5a25977SLeo Liu #define UVD_SUVD_CGC_STATUS2__FBC_CCLK_MASK 0x20000000L 3692a5a25977SLeo Liu //UVD_SUVD_CGC_GATE2 3693a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 3694a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 36951b51916bSAlex Deucher #define UVD_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 36961b51916bSAlex Deucher #define UVD_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 3697a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 3698a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 3699a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 37001b51916bSAlex Deucher #define UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 37011b51916bSAlex Deucher #define UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 3702a5a25977SLeo Liu #define UVD_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 3703a5a25977SLeo Liu //UVD_SUVD_INT_STATUS2 3704a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS2__SMPA_FUNC_INT__SHIFT 0x0 3705a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS2__SMPA_ERR_INT__SHIFT 0x5 37061b51916bSAlex Deucher #define UVD_SUVD_INT_STATUS2__SDB_AV1_FUNC_INT__SHIFT 0x6 37071b51916bSAlex Deucher #define UVD_SUVD_INT_STATUS2__SDB_AV1_ERR_INT__SHIFT 0xb 3708a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS2__SMPA_FUNC_INT_MASK 0x0000001FL 3709a5a25977SLeo Liu #define UVD_SUVD_INT_STATUS2__SMPA_ERR_INT_MASK 0x00000020L 37101b51916bSAlex Deucher #define UVD_SUVD_INT_STATUS2__SDB_AV1_FUNC_INT_MASK 0x000007C0L 37111b51916bSAlex Deucher #define UVD_SUVD_INT_STATUS2__SDB_AV1_ERR_INT_MASK 0x00000800L 3712a5a25977SLeo Liu //UVD_SUVD_INT_EN2 3713a5a25977SLeo Liu #define UVD_SUVD_INT_EN2__SMPA_FUNC_INT_EN__SHIFT 0x0 3714a5a25977SLeo Liu #define UVD_SUVD_INT_EN2__SMPA_ERR_INT_EN__SHIFT 0x5 37151b51916bSAlex Deucher #define UVD_SUVD_INT_EN2__SDB_AV1_FUNC_INT_EN__SHIFT 0x6 37161b51916bSAlex Deucher #define UVD_SUVD_INT_EN2__SDB_AV1_ERR_INT_EN__SHIFT 0xb 3717a5a25977SLeo Liu #define UVD_SUVD_INT_EN2__SMPA_FUNC_INT_EN_MASK 0x0000001FL 3718a5a25977SLeo Liu #define UVD_SUVD_INT_EN2__SMPA_ERR_INT_EN_MASK 0x00000020L 37191b51916bSAlex Deucher #define UVD_SUVD_INT_EN2__SDB_AV1_FUNC_INT_EN_MASK 0x000007C0L 37201b51916bSAlex Deucher #define UVD_SUVD_INT_EN2__SDB_AV1_ERR_INT_EN_MASK 0x00000800L 3721a5a25977SLeo Liu //UVD_SUVD_INT_ACK2 3722a5a25977SLeo Liu #define UVD_SUVD_INT_ACK2__SMPA_FUNC_INT_ACK__SHIFT 0x0 3723a5a25977SLeo Liu #define UVD_SUVD_INT_ACK2__SMPA_ERR_INT_ACK__SHIFT 0x5 37241b51916bSAlex Deucher #define UVD_SUVD_INT_ACK2__SDB_AV1_FUNC_INT_ACK__SHIFT 0x6 37251b51916bSAlex Deucher #define UVD_SUVD_INT_ACK2__SDB_AV1_ERR_INT_ACK__SHIFT 0xb 3726a5a25977SLeo Liu #define UVD_SUVD_INT_ACK2__SMPA_FUNC_INT_ACK_MASK 0x0000001FL 3727a5a25977SLeo Liu #define UVD_SUVD_INT_ACK2__SMPA_ERR_INT_ACK_MASK 0x00000020L 37281b51916bSAlex Deucher #define UVD_SUVD_INT_ACK2__SDB_AV1_FUNC_INT_ACK_MASK 0x000007C0L 37291b51916bSAlex Deucher #define UVD_SUVD_INT_ACK2__SDB_AV1_ERR_INT_ACK_MASK 0x00000800L 3730a5a25977SLeo Liu 3731a5a25977SLeo Liu 3732a5a25977SLeo Liu // addressBlock: uvd0_ecpudec 3733a5a25977SLeo Liu //UVD_VCPU_CACHE_OFFSET0 3734a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 3735a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL 3736a5a25977SLeo Liu //UVD_VCPU_CACHE_SIZE0 3737a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 3738a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL 3739a5a25977SLeo Liu //UVD_VCPU_CACHE_OFFSET1 3740a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 3741a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL 3742a5a25977SLeo Liu //UVD_VCPU_CACHE_SIZE1 3743a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 3744a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL 3745a5a25977SLeo Liu //UVD_VCPU_CACHE_OFFSET2 3746a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 3747a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL 3748a5a25977SLeo Liu //UVD_VCPU_CACHE_SIZE2 3749a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 3750a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL 3751a5a25977SLeo Liu //UVD_VCPU_CACHE_OFFSET3 3752a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0 3753a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL 3754a5a25977SLeo Liu //UVD_VCPU_CACHE_SIZE3 3755a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0 3756a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL 3757a5a25977SLeo Liu //UVD_VCPU_CACHE_OFFSET4 3758a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0 3759a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL 3760a5a25977SLeo Liu //UVD_VCPU_CACHE_SIZE4 3761a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0 3762a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL 3763a5a25977SLeo Liu //UVD_VCPU_CACHE_OFFSET5 3764a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0 3765a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL 3766a5a25977SLeo Liu //UVD_VCPU_CACHE_SIZE5 3767a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0 3768a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL 3769a5a25977SLeo Liu //UVD_VCPU_CACHE_OFFSET6 3770a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0 3771a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL 3772a5a25977SLeo Liu //UVD_VCPU_CACHE_SIZE6 3773a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0 3774a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL 3775a5a25977SLeo Liu //UVD_VCPU_CACHE_OFFSET7 3776a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0 3777a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL 3778a5a25977SLeo Liu //UVD_VCPU_CACHE_SIZE7 3779a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0 3780a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL 3781a5a25977SLeo Liu //UVD_VCPU_CACHE_OFFSET8 3782a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0 3783a5a25977SLeo Liu #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL 3784a5a25977SLeo Liu //UVD_VCPU_CACHE_SIZE8 3785a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0 3786a5a25977SLeo Liu #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL 3787a5a25977SLeo Liu //UVD_VCPU_NONCACHE_OFFSET0 3788a5a25977SLeo Liu #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0 3789a5a25977SLeo Liu #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL 3790a5a25977SLeo Liu //UVD_VCPU_NONCACHE_SIZE0 3791a5a25977SLeo Liu #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0 3792a5a25977SLeo Liu #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL 3793a5a25977SLeo Liu //UVD_VCPU_NONCACHE_OFFSET1 3794a5a25977SLeo Liu #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0 3795a5a25977SLeo Liu #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL 3796a5a25977SLeo Liu //UVD_VCPU_NONCACHE_SIZE1 3797a5a25977SLeo Liu #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0 3798a5a25977SLeo Liu #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL 3799a5a25977SLeo Liu //UVD_VCPU_CNTL 3800a5a25977SLeo Liu #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 3801a5a25977SLeo Liu #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 3802a5a25977SLeo Liu #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 3803a5a25977SLeo Liu #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 3804a5a25977SLeo Liu #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 3805a5a25977SLeo Liu #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 3806a5a25977SLeo Liu #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 3807a5a25977SLeo Liu #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 3808a5a25977SLeo Liu #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 3809a5a25977SLeo Liu #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 3810a5a25977SLeo Liu #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 3811a5a25977SLeo Liu #define UVD_VCPU_CNTL__BLK_RST__SHIFT 0x1c 3812a5a25977SLeo Liu #define UVD_VCPU_CNTL__RUNSTALL__SHIFT 0x1d 3813a5a25977SLeo Liu #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL 3814a5a25977SLeo Liu #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L 3815a5a25977SLeo Liu #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L 3816a5a25977SLeo Liu #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L 3817a5a25977SLeo Liu #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L 3818a5a25977SLeo Liu #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L 3819a5a25977SLeo Liu #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L 3820a5a25977SLeo Liu #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L 3821a5a25977SLeo Liu #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L 3822a5a25977SLeo Liu #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L 3823a5a25977SLeo Liu #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 3824a5a25977SLeo Liu #define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L 3825a5a25977SLeo Liu #define UVD_VCPU_CNTL__RUNSTALL_MASK 0x20000000L 3826a5a25977SLeo Liu //UVD_VCPU_PRID 3827a5a25977SLeo Liu #define UVD_VCPU_PRID__PRID__SHIFT 0x0 3828a5a25977SLeo Liu #define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL 3829a5a25977SLeo Liu //UVD_VCPU_TRCE 3830a5a25977SLeo Liu #define UVD_VCPU_TRCE__PC__SHIFT 0x0 3831a5a25977SLeo Liu #define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL 3832a5a25977SLeo Liu //UVD_VCPU_TRCE_RD 3833a5a25977SLeo Liu #define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0 3834a5a25977SLeo Liu #define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL 3835a5a25977SLeo Liu //UVD_VCPU_IND_INDEX 3836a5a25977SLeo Liu #define UVD_VCPU_IND_INDEX__INDEX__SHIFT 0x0 3837a5a25977SLeo Liu #define UVD_VCPU_IND_INDEX__INDEX_MASK 0x000001FFL 3838a5a25977SLeo Liu //UVD_VCPU_IND_DATA 3839a5a25977SLeo Liu #define UVD_VCPU_IND_DATA__DATA__SHIFT 0x0 3840a5a25977SLeo Liu #define UVD_VCPU_IND_DATA__DATA_MASK 0xFFFFFFFFL 3841a5a25977SLeo Liu 3842a5a25977SLeo Liu 3843a5a25977SLeo Liu // addressBlock: uvd0_uvd_mpcdec 3844a5a25977SLeo Liu //UVD_MP_SWAP_CNTL 3845a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 3846a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 3847a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 3848a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 3849a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 3850a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 3851a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 3852a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 3853a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 3854a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 3855a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 3856a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 3857a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 3858a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 3859a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 3860a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 3861a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L 3862a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL 3863a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L 3864a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L 3865a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L 3866a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L 3867a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L 3868a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L 3869a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L 3870a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L 3871a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L 3872a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L 3873a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L 3874a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L 3875a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L 3876a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L 3877a5a25977SLeo Liu //UVD_MP_SWAP_CNTL2 3878a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP__SHIFT 0x0 3879a5a25977SLeo Liu #define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP_MASK 0x00000003L 3880a5a25977SLeo Liu //UVD_MPC_LUMA_SRCH 3881a5a25977SLeo Liu #define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0 3882a5a25977SLeo Liu #define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL 3883a5a25977SLeo Liu //UVD_MPC_LUMA_HIT 3884a5a25977SLeo Liu #define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0 3885a5a25977SLeo Liu #define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL 3886a5a25977SLeo Liu //UVD_MPC_LUMA_HITPEND 3887a5a25977SLeo Liu #define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0 3888a5a25977SLeo Liu #define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 3889a5a25977SLeo Liu //UVD_MPC_CHROMA_SRCH 3890a5a25977SLeo Liu #define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0 3891a5a25977SLeo Liu #define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL 3892a5a25977SLeo Liu //UVD_MPC_CHROMA_HIT 3893a5a25977SLeo Liu #define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0 3894a5a25977SLeo Liu #define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL 3895a5a25977SLeo Liu //UVD_MPC_CHROMA_HITPEND 3896a5a25977SLeo Liu #define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0 3897a5a25977SLeo Liu #define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 3898a5a25977SLeo Liu //UVD_MPC_CNTL 3899a5a25977SLeo Liu #define UVD_MPC_CNTL__BLK_RST__SHIFT 0x0 3900a5a25977SLeo Liu #define UVD_MPC_CNTL__REG_MPC1_PERF_SELECT__SHIFT 0x1 3901a5a25977SLeo Liu #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 3902a5a25977SLeo Liu #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 3903a5a25977SLeo Liu #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 3904a5a25977SLeo Liu #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 3905a5a25977SLeo Liu #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13 3906a5a25977SLeo Liu #define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14 3907a5a25977SLeo Liu #define UVD_MPC_CNTL__BLK_RST_MASK 0x00000001L 3908a5a25977SLeo Liu #define UVD_MPC_CNTL__REG_MPC1_PERF_SELECT_MASK 0x00000002L 3909a5a25977SLeo Liu #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L 3910a5a25977SLeo Liu #define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L 3911a5a25977SLeo Liu #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L 3912a5a25977SLeo Liu #define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L 3913a5a25977SLeo Liu #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L 3914a5a25977SLeo Liu #define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00100000L 3915a5a25977SLeo Liu //UVD_MPC_PITCH 3916a5a25977SLeo Liu #define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0 3917a5a25977SLeo Liu #define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL 3918a5a25977SLeo Liu //UVD_MPC_SET_MUXA0 3919a5a25977SLeo Liu #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 3920a5a25977SLeo Liu #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 3921a5a25977SLeo Liu #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 3922a5a25977SLeo Liu #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 3923a5a25977SLeo Liu #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 3924a5a25977SLeo Liu #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL 3925a5a25977SLeo Liu #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L 3926a5a25977SLeo Liu #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L 3927a5a25977SLeo Liu #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L 3928a5a25977SLeo Liu #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L 3929a5a25977SLeo Liu //UVD_MPC_SET_MUXA1 3930a5a25977SLeo Liu #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 3931a5a25977SLeo Liu #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 3932a5a25977SLeo Liu #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 3933a5a25977SLeo Liu #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL 3934a5a25977SLeo Liu #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L 3935a5a25977SLeo Liu #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L 3936a5a25977SLeo Liu //UVD_MPC_SET_MUXB0 3937a5a25977SLeo Liu #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 3938a5a25977SLeo Liu #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 3939a5a25977SLeo Liu #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 3940a5a25977SLeo Liu #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 3941a5a25977SLeo Liu #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 3942a5a25977SLeo Liu #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL 3943a5a25977SLeo Liu #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L 3944a5a25977SLeo Liu #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L 3945a5a25977SLeo Liu #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L 3946a5a25977SLeo Liu #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L 3947a5a25977SLeo Liu //UVD_MPC_SET_MUXB1 3948a5a25977SLeo Liu #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 3949a5a25977SLeo Liu #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 3950a5a25977SLeo Liu #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 3951a5a25977SLeo Liu #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL 3952a5a25977SLeo Liu #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L 3953a5a25977SLeo Liu #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L 3954a5a25977SLeo Liu //UVD_MPC_SET_MUX 3955a5a25977SLeo Liu #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 3956a5a25977SLeo Liu #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 3957a5a25977SLeo Liu #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 3958a5a25977SLeo Liu #define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L 3959a5a25977SLeo Liu #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L 3960a5a25977SLeo Liu #define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L 3961a5a25977SLeo Liu //UVD_MPC_SET_ALU 3962a5a25977SLeo Liu #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 3963a5a25977SLeo Liu #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 3964a5a25977SLeo Liu #define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L 3965a5a25977SLeo Liu #define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L 3966a5a25977SLeo Liu //UVD_MPC_PERF0 3967a5a25977SLeo Liu #define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0 3968a5a25977SLeo Liu #define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL 3969a5a25977SLeo Liu //UVD_MPC_PERF1 3970a5a25977SLeo Liu #define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0 3971a5a25977SLeo Liu #define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL 3972a5a25977SLeo Liu //UVD_MPC_IND_INDEX 3973a5a25977SLeo Liu #define UVD_MPC_IND_INDEX__INDEX__SHIFT 0x0 3974a5a25977SLeo Liu #define UVD_MPC_IND_INDEX__INDEX_MASK 0x000001FFL 3975a5a25977SLeo Liu //UVD_MPC_IND_DATA 3976a5a25977SLeo Liu #define UVD_MPC_IND_DATA__DATA__SHIFT 0x0 3977a5a25977SLeo Liu #define UVD_MPC_IND_DATA__DATA_MASK 0xFFFFFFFFL 3978a5a25977SLeo Liu 3979a5a25977SLeo Liu 3980a5a25977SLeo Liu // addressBlock: uvd0_uvd_rbcdec 3981a5a25977SLeo Liu //UVD_RBC_IB_SIZE 3982a5a25977SLeo Liu #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 3983a5a25977SLeo Liu #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 3984a5a25977SLeo Liu //UVD_RBC_IB_SIZE_UPDATE 3985a5a25977SLeo Liu #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 3986a5a25977SLeo Liu #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 3987a5a25977SLeo Liu //UVD_RBC_RB_CNTL 3988a5a25977SLeo Liu #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 3989a5a25977SLeo Liu #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 3990a5a25977SLeo Liu #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 3991a5a25977SLeo Liu #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 3992a5a25977SLeo Liu #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 3993a5a25977SLeo Liu #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 3994a5a25977SLeo Liu #define UVD_RBC_RB_CNTL__BLK_RST__SHIFT 0x1d 3995a5a25977SLeo Liu #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL 3996a5a25977SLeo Liu #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L 3997a5a25977SLeo Liu #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L 3998a5a25977SLeo Liu #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L 3999a5a25977SLeo Liu #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L 4000a5a25977SLeo Liu #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L 4001a5a25977SLeo Liu #define UVD_RBC_RB_CNTL__BLK_RST_MASK 0x20000000L 4002a5a25977SLeo Liu //UVD_RBC_RB_RPTR_ADDR 4003a5a25977SLeo Liu #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 4004a5a25977SLeo Liu #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL 4005a5a25977SLeo Liu //UVD_RBC_RB_RPTR 4006a5a25977SLeo Liu #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 4007a5a25977SLeo Liu #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 4008a5a25977SLeo Liu //UVD_RBC_RB_WPTR 4009a5a25977SLeo Liu #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 4010a5a25977SLeo Liu #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 4011a5a25977SLeo Liu //UVD_RBC_VCPU_ACCESS 4012a5a25977SLeo Liu #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0 4013a5a25977SLeo Liu #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L 4014a5a25977SLeo Liu //UVD_FW_SEMAPHORE_CNTL 4015a5a25977SLeo Liu #define UVD_FW_SEMAPHORE_CNTL__START__SHIFT 0x0 4016a5a25977SLeo Liu #define UVD_FW_SEMAPHORE_CNTL__BUSY__SHIFT 0x8 4017a5a25977SLeo Liu #define UVD_FW_SEMAPHORE_CNTL__PASS__SHIFT 0x9 4018a5a25977SLeo Liu #define UVD_FW_SEMAPHORE_CNTL__START_MASK 0x00000001L 4019a5a25977SLeo Liu #define UVD_FW_SEMAPHORE_CNTL__BUSY_MASK 0x00000100L 4020a5a25977SLeo Liu #define UVD_FW_SEMAPHORE_CNTL__PASS_MASK 0x00000200L 4021a5a25977SLeo Liu //UVD_RBC_READ_REQ_URGENT_CNTL 4022a5a25977SLeo Liu #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 4023a5a25977SLeo Liu #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 4024a5a25977SLeo Liu //UVD_RBC_RB_WPTR_CNTL 4025a5a25977SLeo Liu #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 4026a5a25977SLeo Liu #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL 4027a5a25977SLeo Liu //UVD_RBC_WPTR_STATUS 4028a5a25977SLeo Liu #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4 4029a5a25977SLeo Liu #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L 4030a5a25977SLeo Liu //UVD_RBC_WPTR_POLL_CNTL 4031a5a25977SLeo Liu #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0 4032a5a25977SLeo Liu #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 4033a5a25977SLeo Liu #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL 4034a5a25977SLeo Liu #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 4035a5a25977SLeo Liu //UVD_RBC_WPTR_POLL_ADDR 4036a5a25977SLeo Liu #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2 4037a5a25977SLeo Liu #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL 4038a5a25977SLeo Liu //UVD_SEMA_CMD 4039a5a25977SLeo Liu #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 4040a5a25977SLeo Liu #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 4041a5a25977SLeo Liu #define UVD_SEMA_CMD__MODE__SHIFT 0x6 4042a5a25977SLeo Liu #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 4043a5a25977SLeo Liu #define UVD_SEMA_CMD__VMID__SHIFT 0x8 4044a5a25977SLeo Liu #define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL 4045a5a25977SLeo Liu #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L 4046a5a25977SLeo Liu #define UVD_SEMA_CMD__MODE_MASK 0x00000040L 4047a5a25977SLeo Liu #define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L 4048a5a25977SLeo Liu #define UVD_SEMA_CMD__VMID_MASK 0x00000F00L 4049a5a25977SLeo Liu //UVD_SEMA_ADDR_LOW 4050a5a25977SLeo Liu #define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0 4051a5a25977SLeo Liu #define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL 4052a5a25977SLeo Liu //UVD_SEMA_ADDR_HIGH 4053a5a25977SLeo Liu #define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0 4054a5a25977SLeo Liu #define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL 4055a5a25977SLeo Liu //UVD_ENGINE_CNTL 4056a5a25977SLeo Liu #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 4057a5a25977SLeo Liu #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 4058a5a25977SLeo Liu #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2 4059a5a25977SLeo Liu #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L 4060a5a25977SLeo Liu #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L 4061a5a25977SLeo Liu #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L 4062a5a25977SLeo Liu //UVD_SEMA_TIMEOUT_STATUS 4063a5a25977SLeo Liu #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 4064a5a25977SLeo Liu #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 4065a5a25977SLeo Liu #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 4066a5a25977SLeo Liu #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 4067a5a25977SLeo Liu #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L 4068a5a25977SLeo Liu #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L 4069a5a25977SLeo Liu #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L 4070a5a25977SLeo Liu #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L 4071a5a25977SLeo Liu //UVD_SEMA_CNTL 4072a5a25977SLeo Liu #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 4073a5a25977SLeo Liu #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 4074a5a25977SLeo Liu #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L 4075a5a25977SLeo Liu #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L 4076a5a25977SLeo Liu //UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 4077a5a25977SLeo Liu #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 4078a5a25977SLeo Liu #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 4079a5a25977SLeo Liu #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 4080a5a25977SLeo Liu #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L 4081a5a25977SLeo Liu #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL 4082a5a25977SLeo Liu #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 4083a5a25977SLeo Liu //UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 4084a5a25977SLeo Liu #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 4085a5a25977SLeo Liu #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 4086a5a25977SLeo Liu #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 4087a5a25977SLeo Liu #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L 4088a5a25977SLeo Liu #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL 4089a5a25977SLeo Liu #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 4090a5a25977SLeo Liu //UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 4091a5a25977SLeo Liu #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 4092a5a25977SLeo Liu #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 4093a5a25977SLeo Liu #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 4094a5a25977SLeo Liu #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L 4095a5a25977SLeo Liu #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL 4096a5a25977SLeo Liu #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 4097a5a25977SLeo Liu //UVD_JOB_START 4098a5a25977SLeo Liu #define UVD_JOB_START__JOB_START__SHIFT 0x0 4099a5a25977SLeo Liu #define UVD_JOB_START__JOB_START_MASK 0x00000001L 4100a5a25977SLeo Liu //UVD_RBC_BUF_STATUS 4101a5a25977SLeo Liu #define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 4102a5a25977SLeo Liu #define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8 4103a5a25977SLeo Liu #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 4104a5a25977SLeo Liu #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13 4105a5a25977SLeo Liu #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16 4106a5a25977SLeo Liu #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19 4107a5a25977SLeo Liu #define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL 4108a5a25977SLeo Liu #define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L 4109a5a25977SLeo Liu #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L 4110a5a25977SLeo Liu #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L 4111a5a25977SLeo Liu #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L 4112a5a25977SLeo Liu #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L 4113a5a25977SLeo Liu //UVD_RBC_SWAP_CNTL 4114a5a25977SLeo Liu #define UVD_RBC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 4115a5a25977SLeo Liu #define UVD_RBC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 4116a5a25977SLeo Liu #define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 4117a5a25977SLeo Liu #define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 4118a5a25977SLeo Liu #define UVD_RBC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 4119a5a25977SLeo Liu #define UVD_RBC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 4120a5a25977SLeo Liu #define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L 4121a5a25977SLeo Liu #define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L 4122a5a25977SLeo Liu 4123a5a25977SLeo Liu 4124a5a25977SLeo Liu // addressBlock: uvd0_lmi_adpdec 4125a5a25977SLeo Liu //UVD_LMI_RE_64BIT_BAR_LOW 4126a5a25977SLeo Liu #define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4127a5a25977SLeo Liu #define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4128a5a25977SLeo Liu //UVD_LMI_RE_64BIT_BAR_HIGH 4129a5a25977SLeo Liu #define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4130a5a25977SLeo Liu #define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4131a5a25977SLeo Liu //UVD_LMI_IT_64BIT_BAR_LOW 4132a5a25977SLeo Liu #define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4133a5a25977SLeo Liu #define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4134a5a25977SLeo Liu //UVD_LMI_IT_64BIT_BAR_HIGH 4135a5a25977SLeo Liu #define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4136a5a25977SLeo Liu #define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4137a5a25977SLeo Liu //UVD_LMI_MP_64BIT_BAR_LOW 4138a5a25977SLeo Liu #define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4139a5a25977SLeo Liu #define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4140a5a25977SLeo Liu //UVD_LMI_MP_64BIT_BAR_HIGH 4141a5a25977SLeo Liu #define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4142a5a25977SLeo Liu #define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4143a5a25977SLeo Liu //UVD_LMI_CM_64BIT_BAR_LOW 4144a5a25977SLeo Liu #define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4145a5a25977SLeo Liu #define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4146a5a25977SLeo Liu //UVD_LMI_CM_64BIT_BAR_HIGH 4147a5a25977SLeo Liu #define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4148a5a25977SLeo Liu #define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4149a5a25977SLeo Liu //UVD_LMI_DB_64BIT_BAR_LOW 4150a5a25977SLeo Liu #define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4151a5a25977SLeo Liu #define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4152a5a25977SLeo Liu //UVD_LMI_DB_64BIT_BAR_HIGH 4153a5a25977SLeo Liu #define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4154a5a25977SLeo Liu #define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4155a5a25977SLeo Liu //UVD_LMI_DBW_64BIT_BAR_LOW 4156a5a25977SLeo Liu #define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4157a5a25977SLeo Liu #define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4158a5a25977SLeo Liu //UVD_LMI_DBW_64BIT_BAR_HIGH 4159a5a25977SLeo Liu #define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4160a5a25977SLeo Liu #define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4161a5a25977SLeo Liu //UVD_LMI_IDCT_64BIT_BAR_LOW 4162a5a25977SLeo Liu #define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4163a5a25977SLeo Liu #define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4164a5a25977SLeo Liu //UVD_LMI_IDCT_64BIT_BAR_HIGH 4165a5a25977SLeo Liu #define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4166a5a25977SLeo Liu #define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4167a5a25977SLeo Liu //UVD_LMI_MPRD_S0_64BIT_BAR_LOW 4168a5a25977SLeo Liu #define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4169a5a25977SLeo Liu #define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4170a5a25977SLeo Liu //UVD_LMI_MPRD_S0_64BIT_BAR_HIGH 4171a5a25977SLeo Liu #define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4172a5a25977SLeo Liu #define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4173a5a25977SLeo Liu //UVD_LMI_MPRD_S1_64BIT_BAR_LOW 4174a5a25977SLeo Liu #define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4175a5a25977SLeo Liu #define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4176a5a25977SLeo Liu //UVD_LMI_MPRD_S1_64BIT_BAR_HIGH 4177a5a25977SLeo Liu #define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4178a5a25977SLeo Liu #define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4179a5a25977SLeo Liu //UVD_LMI_MPRD_DBW_64BIT_BAR_LOW 4180a5a25977SLeo Liu #define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4181a5a25977SLeo Liu #define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4182a5a25977SLeo Liu //UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 4183a5a25977SLeo Liu #define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4184a5a25977SLeo Liu #define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4185a5a25977SLeo Liu //UVD_LMI_MPC_64BIT_BAR_LOW 4186a5a25977SLeo Liu #define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4187a5a25977SLeo Liu #define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4188a5a25977SLeo Liu //UVD_LMI_MPC_64BIT_BAR_HIGH 4189a5a25977SLeo Liu #define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4190a5a25977SLeo Liu #define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4191a5a25977SLeo Liu //UVD_LMI_RBC_RB_64BIT_BAR_LOW 4192a5a25977SLeo Liu #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4193a5a25977SLeo Liu #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4194a5a25977SLeo Liu //UVD_LMI_RBC_RB_64BIT_BAR_HIGH 4195a5a25977SLeo Liu #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4196a5a25977SLeo Liu #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4197a5a25977SLeo Liu //UVD_LMI_RBC_IB_64BIT_BAR_LOW 4198a5a25977SLeo Liu #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4199a5a25977SLeo Liu #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4200a5a25977SLeo Liu //UVD_LMI_RBC_IB_64BIT_BAR_HIGH 4201a5a25977SLeo Liu #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4202a5a25977SLeo Liu #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4203a5a25977SLeo Liu //UVD_LMI_LBSI_64BIT_BAR_LOW 4204a5a25977SLeo Liu #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4205a5a25977SLeo Liu #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4206a5a25977SLeo Liu //UVD_LMI_LBSI_64BIT_BAR_HIGH 4207a5a25977SLeo Liu #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4208a5a25977SLeo Liu #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4209a5a25977SLeo Liu //UVD_LMI_VCPU_NC0_64BIT_BAR_LOW 4210a5a25977SLeo Liu #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4211a5a25977SLeo Liu #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4212a5a25977SLeo Liu //UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 4213a5a25977SLeo Liu #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4214a5a25977SLeo Liu #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4215a5a25977SLeo Liu //UVD_LMI_VCPU_NC1_64BIT_BAR_LOW 4216a5a25977SLeo Liu #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4217a5a25977SLeo Liu #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4218a5a25977SLeo Liu //UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 4219a5a25977SLeo Liu #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4220a5a25977SLeo Liu #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4221a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 4222a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4223a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4224a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 4225a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4226a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4227a5a25977SLeo Liu //UVD_LMI_CENC_64BIT_BAR_LOW 4228a5a25977SLeo Liu #define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4229a5a25977SLeo Liu #define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4230a5a25977SLeo Liu //UVD_LMI_CENC_64BIT_BAR_HIGH 4231a5a25977SLeo Liu #define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4232a5a25977SLeo Liu #define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4233a5a25977SLeo Liu //UVD_LMI_SRE_64BIT_BAR_LOW 4234a5a25977SLeo Liu #define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4235a5a25977SLeo Liu #define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4236a5a25977SLeo Liu //UVD_LMI_SRE_64BIT_BAR_HIGH 4237a5a25977SLeo Liu #define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4238a5a25977SLeo Liu #define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4239a5a25977SLeo Liu //UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 4240a5a25977SLeo Liu #define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4241a5a25977SLeo Liu #define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4242a5a25977SLeo Liu //UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 4243a5a25977SLeo Liu #define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4244a5a25977SLeo Liu #define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4245a5a25977SLeo Liu //UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 4246a5a25977SLeo Liu #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4247a5a25977SLeo Liu #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4248a5a25977SLeo Liu //UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 4249a5a25977SLeo Liu #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4250a5a25977SLeo Liu #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4251a5a25977SLeo Liu //UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 4252a5a25977SLeo Liu #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4253a5a25977SLeo Liu #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4254a5a25977SLeo Liu //UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 4255a5a25977SLeo Liu #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4256a5a25977SLeo Liu #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4257a5a25977SLeo Liu //UVD_LMI_MIF_REF_64BIT_BAR_LOW 4258a5a25977SLeo Liu #define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4259a5a25977SLeo Liu #define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4260a5a25977SLeo Liu //UVD_LMI_MIF_REF_64BIT_BAR_HIGH 4261a5a25977SLeo Liu #define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4262a5a25977SLeo Liu #define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4263a5a25977SLeo Liu //UVD_LMI_MIF_DBW_64BIT_BAR_LOW 4264a5a25977SLeo Liu #define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4265a5a25977SLeo Liu #define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4266a5a25977SLeo Liu //UVD_LMI_MIF_DBW_64BIT_BAR_HIGH 4267a5a25977SLeo Liu #define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4268a5a25977SLeo Liu #define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4269a5a25977SLeo Liu //UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 4270a5a25977SLeo Liu #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4271a5a25977SLeo Liu #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4272a5a25977SLeo Liu //UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 4273a5a25977SLeo Liu #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4274a5a25977SLeo Liu #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4275a5a25977SLeo Liu //UVD_LMI_MIF_BSP0_64BIT_BAR_LOW 4276a5a25977SLeo Liu #define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4277a5a25977SLeo Liu #define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4278a5a25977SLeo Liu //UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 4279a5a25977SLeo Liu #define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4280a5a25977SLeo Liu #define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4281a5a25977SLeo Liu //UVD_LMI_MIF_BSP1_64BIT_BAR_LOW 4282a5a25977SLeo Liu #define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4283a5a25977SLeo Liu #define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4284a5a25977SLeo Liu //UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 4285a5a25977SLeo Liu #define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4286a5a25977SLeo Liu #define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4287a5a25977SLeo Liu //UVD_LMI_MIF_BSP2_64BIT_BAR_LOW 4288a5a25977SLeo Liu #define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4289a5a25977SLeo Liu #define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4290a5a25977SLeo Liu //UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 4291a5a25977SLeo Liu #define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4292a5a25977SLeo Liu #define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4293a5a25977SLeo Liu //UVD_LMI_MIF_BSP3_64BIT_BAR_LOW 4294a5a25977SLeo Liu #define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4295a5a25977SLeo Liu #define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4296a5a25977SLeo Liu //UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 4297a5a25977SLeo Liu #define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4298a5a25977SLeo Liu #define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4299a5a25977SLeo Liu //UVD_LMI_MIF_BSD0_64BIT_BAR_LOW 4300a5a25977SLeo Liu #define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4301a5a25977SLeo Liu #define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4302a5a25977SLeo Liu //UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 4303a5a25977SLeo Liu #define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4304a5a25977SLeo Liu #define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4305a5a25977SLeo Liu //UVD_LMI_MIF_BSD1_64BIT_BAR_LOW 4306a5a25977SLeo Liu #define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4307a5a25977SLeo Liu #define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4308a5a25977SLeo Liu //UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 4309a5a25977SLeo Liu #define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4310a5a25977SLeo Liu #define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4311a5a25977SLeo Liu //UVD_LMI_MIF_BSD2_64BIT_BAR_LOW 4312a5a25977SLeo Liu #define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4313a5a25977SLeo Liu #define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4314a5a25977SLeo Liu //UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 4315a5a25977SLeo Liu #define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4316a5a25977SLeo Liu #define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4317a5a25977SLeo Liu //UVD_LMI_MIF_BSD3_64BIT_BAR_LOW 4318a5a25977SLeo Liu #define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4319a5a25977SLeo Liu #define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4320a5a25977SLeo Liu //UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 4321a5a25977SLeo Liu #define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4322a5a25977SLeo Liu #define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4323a5a25977SLeo Liu //UVD_LMI_MIF_BSD4_64BIT_BAR_LOW 4324a5a25977SLeo Liu #define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4325a5a25977SLeo Liu #define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4326a5a25977SLeo Liu //UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 4327a5a25977SLeo Liu #define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4328a5a25977SLeo Liu #define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4329a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 4330a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4331a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4332a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 4333a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4334a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4335a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 4336a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4337a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4338a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 4339a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4340a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4341a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 4342a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4343a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4344a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 4345a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4346a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4347a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 4348a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4349a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4350a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 4351a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4352a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4353a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 4354a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4355a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4356a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 4357a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4358a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4359a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 4360a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4361a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4362a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 4363a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4364a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4365a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 4366a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4367a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4368a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 4369a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4370a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4371a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 4372a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4373a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4374a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 4375a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4376a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4377a5a25977SLeo Liu //UVD_LMI_MIF_SCLR_64BIT_BAR_LOW 4378a5a25977SLeo Liu #define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4379a5a25977SLeo Liu #define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4380a5a25977SLeo Liu //UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 4381a5a25977SLeo Liu #define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4382a5a25977SLeo Liu #define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4383a5a25977SLeo Liu //UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 4384a5a25977SLeo Liu #define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4385a5a25977SLeo Liu #define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4386a5a25977SLeo Liu //UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 4387a5a25977SLeo Liu #define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4388a5a25977SLeo Liu #define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4389a5a25977SLeo Liu //UVD_LMI_SPH_64BIT_BAR_HIGH 4390a5a25977SLeo Liu #define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4391a5a25977SLeo Liu #define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4392a5a25977SLeo Liu //UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 4393a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4394a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4395a5a25977SLeo Liu //UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 4396a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4397a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4398a5a25977SLeo Liu //UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 4399a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4400a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4401a5a25977SLeo Liu //UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 4402a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4403a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4404a5a25977SLeo Liu //UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 4405a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4406a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4407a5a25977SLeo Liu //UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 4408a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4409a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4410a5a25977SLeo Liu //UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 4411a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4412a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4413a5a25977SLeo Liu //UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 4414a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4415a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4416a5a25977SLeo Liu //UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 4417a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4418a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4419a5a25977SLeo Liu //UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 4420a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4421a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4422a5a25977SLeo Liu //UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 4423a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4424a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4425a5a25977SLeo Liu //UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 4426a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4427a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4428a5a25977SLeo Liu //UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 4429a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4430a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4431a5a25977SLeo Liu //UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 4432a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4433a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4434a5a25977SLeo Liu //UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 4435a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4436a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4437a5a25977SLeo Liu //UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 4438a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4439a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4440a5a25977SLeo Liu //UVD_LMI_MMSCH_NC_VMID 4441a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0 4442a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4 4443a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8 4444a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc 4445a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10 4446a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14 4447a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18 4448a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c 4449a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL 4450a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L 4451a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L 4452a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L 4453a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L 4454a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L 4455a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L 4456a5a25977SLeo Liu #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L 4457a5a25977SLeo Liu //UVD_LMI_MMSCH_CTRL 4458a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0 4459a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1 4460a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH__SHIFT 0x2 4461a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3 4462a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5 4463a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7 4464a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9 4465a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb 4466a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc 4467a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L 4468a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L 4469a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH_MASK 0x00000004L 4470a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L 4471a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L 4472a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L 4473a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L 4474a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L 4475a5a25977SLeo Liu #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L 4476a5a25977SLeo Liu //UVD_MMSCH_LMI_STATUS 4477a5a25977SLeo Liu #define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN__SHIFT 0x2 4478a5a25977SLeo Liu #define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN__SHIFT 0xd 4479a5a25977SLeo Liu #define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN__SHIFT 0xe 4480a5a25977SLeo Liu #define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN_MASK 0x00000004L 4481a5a25977SLeo Liu #define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN_MASK 0x00002000L 4482a5a25977SLeo Liu #define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN_MASK 0x00004000L 4483a5a25977SLeo Liu //UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 4484a5a25977SLeo Liu #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4485a5a25977SLeo Liu #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4486a5a25977SLeo Liu //UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 4487a5a25977SLeo Liu #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4488a5a25977SLeo Liu #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4489a5a25977SLeo Liu //UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 4490a5a25977SLeo Liu #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4491a5a25977SLeo Liu #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4492a5a25977SLeo Liu //UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 4493a5a25977SLeo Liu #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4494a5a25977SLeo Liu #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4495a5a25977SLeo Liu //UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 4496a5a25977SLeo Liu #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4497a5a25977SLeo Liu #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4498a5a25977SLeo Liu //UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 4499a5a25977SLeo Liu #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4500a5a25977SLeo Liu #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4501a5a25977SLeo Liu //UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 4502a5a25977SLeo Liu #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4503a5a25977SLeo Liu #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4504a5a25977SLeo Liu //UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 4505a5a25977SLeo Liu #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4506a5a25977SLeo Liu #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4507a5a25977SLeo Liu //UVD_ADP_ATOMIC_CONFIG 4508a5a25977SLeo Liu #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE__SHIFT 0x0 4509a5a25977SLeo Liu #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE__SHIFT 0x4 4510a5a25977SLeo Liu #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE__SHIFT 0x8 4511a5a25977SLeo Liu #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE__SHIFT 0xc 4512a5a25977SLeo Liu #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG__SHIFT 0x10 4513a5a25977SLeo Liu #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE_MASK 0x0000000FL 4514a5a25977SLeo Liu #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE_MASK 0x000000F0L 4515a5a25977SLeo Liu #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE_MASK 0x00000F00L 4516a5a25977SLeo Liu #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE_MASK 0x0000F000L 4517a5a25977SLeo Liu #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG_MASK 0x000F0000L 4518a5a25977SLeo Liu //UVD_LMI_ARB_CTRL2 4519a5a25977SLeo Liu #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0 4520a5a25977SLeo Liu #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1 4521a5a25977SLeo Liu #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2 4522a5a25977SLeo Liu #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6 4523a5a25977SLeo Liu #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa 4524a5a25977SLeo Liu #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14 4525a5a25977SLeo Liu #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L 4526a5a25977SLeo Liu #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L 4527a5a25977SLeo Liu #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL 4528a5a25977SLeo Liu #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L 4529a5a25977SLeo Liu #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L 4530a5a25977SLeo Liu #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L 4531a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE_VMIDS_MULTI 4532a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0 4533a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4 4534a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8 4535a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc 4536a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10 4537a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14 4538a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18 4539a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c 4540a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL 4541a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L 4542a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L 4543a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L 4544a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L 4545a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L 4546a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L 4547a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L 4548a5a25977SLeo Liu //UVD_LMI_VCPU_NC_VMIDS_MULTI 4549a5a25977SLeo Liu #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4 4550a5a25977SLeo Liu #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8 4551a5a25977SLeo Liu #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc 4552a5a25977SLeo Liu #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10 4553a5a25977SLeo Liu #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14 4554a5a25977SLeo Liu #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18 4555a5a25977SLeo Liu #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L 4556a5a25977SLeo Liu #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L 4557a5a25977SLeo Liu #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L 4558a5a25977SLeo Liu #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L 4559a5a25977SLeo Liu #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L 4560a5a25977SLeo Liu #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L 4561a5a25977SLeo Liu //UVD_LMI_LAT_CTRL 4562a5a25977SLeo Liu #define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0 4563a5a25977SLeo Liu #define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8 4564a5a25977SLeo Liu #define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9 4565a5a25977SLeo Liu #define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa 4566a5a25977SLeo Liu #define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 4567a5a25977SLeo Liu #define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10 4568a5a25977SLeo Liu #define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL 4569a5a25977SLeo Liu #define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L 4570a5a25977SLeo Liu #define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L 4571a5a25977SLeo Liu #define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L 4572a5a25977SLeo Liu #define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 4573a5a25977SLeo Liu #define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L 4574a5a25977SLeo Liu //UVD_LMI_LAT_CNTR 4575a5a25977SLeo Liu #define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 4576a5a25977SLeo Liu #define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 4577a5a25977SLeo Liu #define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 4578a5a25977SLeo Liu #define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 4579a5a25977SLeo Liu //UVD_LMI_AVG_LAT_CNTR 4580a5a25977SLeo Liu #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 4581a5a25977SLeo Liu #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 4582a5a25977SLeo Liu #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 4583a5a25977SLeo Liu #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 4584a5a25977SLeo Liu #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 4585a5a25977SLeo Liu #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 4586a5a25977SLeo Liu //UVD_LMI_SPH 4587a5a25977SLeo Liu #define UVD_LMI_SPH__ADDR__SHIFT 0x0 4588a5a25977SLeo Liu #define UVD_LMI_SPH__STS__SHIFT 0x1c 4589a5a25977SLeo Liu #define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e 4590a5a25977SLeo Liu #define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f 4591a5a25977SLeo Liu #define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL 4592a5a25977SLeo Liu #define UVD_LMI_SPH__STS_MASK 0x30000000L 4593a5a25977SLeo Liu #define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L 4594a5a25977SLeo Liu #define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L 4595a5a25977SLeo Liu //UVD_LMI_VCPU_CACHE_VMID 4596a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 4597a5a25977SLeo Liu #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 4598a5a25977SLeo Liu //UVD_LMI_CTRL2 4599a5a25977SLeo Liu #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 4600a5a25977SLeo Liu #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 4601a5a25977SLeo Liu #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 4602a5a25977SLeo Liu #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 4603a5a25977SLeo Liu #define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4 4604a5a25977SLeo Liu #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 4605a5a25977SLeo Liu #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 4606a5a25977SLeo Liu #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 4607a5a25977SLeo Liu #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 4608a5a25977SLeo Liu #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 4609a5a25977SLeo Liu #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 4610a5a25977SLeo Liu #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 4611a5a25977SLeo Liu #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 4612a5a25977SLeo Liu #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 4613a5a25977SLeo Liu #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19 4614a5a25977SLeo Liu #define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a 4615a5a25977SLeo Liu #define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b 4616a5a25977SLeo Liu #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L 4617a5a25977SLeo Liu #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 4618a5a25977SLeo Liu #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 4619a5a25977SLeo Liu #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L 4620a5a25977SLeo Liu #define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L 4621a5a25977SLeo Liu #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L 4622a5a25977SLeo Liu #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 4623a5a25977SLeo Liu #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L 4624a5a25977SLeo Liu #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L 4625a5a25977SLeo Liu #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L 4626a5a25977SLeo Liu #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L 4627a5a25977SLeo Liu #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L 4628a5a25977SLeo Liu #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L 4629a5a25977SLeo Liu #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L 4630a5a25977SLeo Liu #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L 4631a5a25977SLeo Liu #define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L 4632a5a25977SLeo Liu #define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L 4633a5a25977SLeo Liu //UVD_LMI_URGENT_CTRL 4634a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 4635a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1 4636a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2 4637a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8 4638a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9 4639a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa 4640a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10 4641a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11 4642a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12 4643a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18 4644a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19 4645a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a 4646a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 4647a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L 4648a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL 4649a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L 4650a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L 4651a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L 4652a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L 4653a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L 4654a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L 4655a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L 4656a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L 4657a5a25977SLeo Liu #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L 4658a5a25977SLeo Liu //UVD_LMI_CTRL 4659a5a25977SLeo Liu #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 4660a5a25977SLeo Liu #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 4661a5a25977SLeo Liu #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 4662a5a25977SLeo Liu #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 4663a5a25977SLeo Liu #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 4664a5a25977SLeo Liu #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 4665a5a25977SLeo Liu #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 4666a5a25977SLeo Liu #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 4667a5a25977SLeo Liu #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 4668a5a25977SLeo Liu #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 4669a5a25977SLeo Liu #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 4670a5a25977SLeo Liu #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 4671a5a25977SLeo Liu #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 4672a5a25977SLeo Liu #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 4673a5a25977SLeo Liu #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 4674a5a25977SLeo Liu #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b 4675a5a25977SLeo Liu #define UVD_LMI_CTRL__MC_BLK_RST__SHIFT 0x1c 4676a5a25977SLeo Liu #define UVD_LMI_CTRL__UMC_BLK_RST__SHIFT 0x1d 4677a5a25977SLeo Liu #define UVD_LMI_CTRL__RFU__SHIFT 0x1e 4678a5a25977SLeo Liu #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL 4679a5a25977SLeo Liu #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L 4680a5a25977SLeo Liu #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L 4681a5a25977SLeo Liu #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L 4682a5a25977SLeo Liu #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L 4683a5a25977SLeo Liu #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L 4684a5a25977SLeo Liu #define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L 4685a5a25977SLeo Liu #define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L 4686a5a25977SLeo Liu #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L 4687a5a25977SLeo Liu #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 4688a5a25977SLeo Liu #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L 4689a5a25977SLeo Liu #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L 4690a5a25977SLeo Liu #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L 4691a5a25977SLeo Liu #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L 4692a5a25977SLeo Liu #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L 4693a5a25977SLeo Liu #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L 4694a5a25977SLeo Liu #define UVD_LMI_CTRL__MC_BLK_RST_MASK 0x10000000L 4695a5a25977SLeo Liu #define UVD_LMI_CTRL__UMC_BLK_RST_MASK 0x20000000L 4696a5a25977SLeo Liu #define UVD_LMI_CTRL__RFU_MASK 0xC0000000L 4697a5a25977SLeo Liu //UVD_LMI_STATUS 4698a5a25977SLeo Liu #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 4699a5a25977SLeo Liu #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 4700a5a25977SLeo Liu #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 4701a5a25977SLeo Liu #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 4702a5a25977SLeo Liu #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 4703a5a25977SLeo Liu #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 4704a5a25977SLeo Liu #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 4705a5a25977SLeo Liu #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 4706a5a25977SLeo Liu #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 4707a5a25977SLeo Liu #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 4708a5a25977SLeo Liu #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 4709a5a25977SLeo Liu #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 4710a5a25977SLeo Liu #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 4711a5a25977SLeo Liu #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 4712a5a25977SLeo Liu #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12 4713a5a25977SLeo Liu #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13 4714a5a25977SLeo Liu #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14 4715a5a25977SLeo Liu #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15 4716a5a25977SLeo Liu #define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16 4717a5a25977SLeo Liu #define UVD_LMI_STATUS__DPB_MPC2_NO_HIT__SHIFT 0x1c 4718a5a25977SLeo Liu #define UVD_LMI_STATUS__DPB_MPC2_MULTI_HIT__SHIFT 0x1d 4719a5a25977SLeo Liu #define UVD_LMI_STATUS__DPB_MPC_NO_HIT__SHIFT 0x1e 4720a5a25977SLeo Liu #define UVD_LMI_STATUS__DPB_MPC_MULTI_HIT__SHIFT 0x1f 4721a5a25977SLeo Liu #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L 4722a5a25977SLeo Liu #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L 4723a5a25977SLeo Liu #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L 4724a5a25977SLeo Liu #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L 4725a5a25977SLeo Liu #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L 4726a5a25977SLeo Liu #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L 4727a5a25977SLeo Liu #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L 4728a5a25977SLeo Liu #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L 4729a5a25977SLeo Liu #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L 4730a5a25977SLeo Liu #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L 4731a5a25977SLeo Liu #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L 4732a5a25977SLeo Liu #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L 4733a5a25977SLeo Liu #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L 4734a5a25977SLeo Liu #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L 4735a5a25977SLeo Liu #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L 4736a5a25977SLeo Liu #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L 4737a5a25977SLeo Liu #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L 4738a5a25977SLeo Liu #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L 4739a5a25977SLeo Liu #define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L 4740a5a25977SLeo Liu #define UVD_LMI_STATUS__DPB_MPC2_NO_HIT_MASK 0x10000000L 4741a5a25977SLeo Liu #define UVD_LMI_STATUS__DPB_MPC2_MULTI_HIT_MASK 0x20000000L 4742a5a25977SLeo Liu #define UVD_LMI_STATUS__DPB_MPC_NO_HIT_MASK 0x40000000L 4743a5a25977SLeo Liu #define UVD_LMI_STATUS__DPB_MPC_MULTI_HIT_MASK 0x80000000L 4744a5a25977SLeo Liu //UVD_LMI_PERFMON_CTRL 4745a5a25977SLeo Liu #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 4746a5a25977SLeo Liu #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 4747a5a25977SLeo Liu #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 4748a5a25977SLeo Liu #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L 4749a5a25977SLeo Liu //UVD_LMI_PERFMON_COUNT_LO 4750a5a25977SLeo Liu #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 4751a5a25977SLeo Liu #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 4752a5a25977SLeo Liu //UVD_LMI_PERFMON_COUNT_HI 4753a5a25977SLeo Liu #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 4754a5a25977SLeo Liu #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 4755a5a25977SLeo Liu //UVD_LMI_ADP_SWAP_CNTL 4756a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 4757a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 4758a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 4759a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 4760a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 4761a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 4762a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 4763a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__PREF_MC_SWAP__SHIFT 0x14 4764a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 4765a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 4766a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 4767a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L 4768a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L 4769a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L 4770a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L 4771a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L 4772a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L 4773a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L 4774a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__PREF_MC_SWAP_MASK 0x00300000L 4775a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L 4776a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L 4777a5a25977SLeo Liu #define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L 4778a5a25977SLeo Liu //UVD_LMI_RBC_RB_VMID 4779a5a25977SLeo Liu #define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 4780a5a25977SLeo Liu #define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL 4781a5a25977SLeo Liu //UVD_LMI_RBC_IB_VMID 4782a5a25977SLeo Liu #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 4783a5a25977SLeo Liu #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL 4784a5a25977SLeo Liu //UVD_LMI_MC_CREDITS 4785a5a25977SLeo Liu #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0 4786a5a25977SLeo Liu #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8 4787a5a25977SLeo Liu #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10 4788a5a25977SLeo Liu #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18 4789a5a25977SLeo Liu #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL 4790a5a25977SLeo Liu #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L 4791a5a25977SLeo Liu #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L 4792a5a25977SLeo Liu #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L 4793a5a25977SLeo Liu //UVD_LMI_ADP_IND_INDEX 4794a5a25977SLeo Liu #define UVD_LMI_ADP_IND_INDEX__INDEX__SHIFT 0x0 4795a5a25977SLeo Liu #define UVD_LMI_ADP_IND_INDEX__INDEX_MASK 0x00001FFFL 4796a5a25977SLeo Liu //UVD_LMI_ADP_IND_DATA 4797a5a25977SLeo Liu #define UVD_LMI_ADP_IND_DATA__DATA__SHIFT 0x0 4798a5a25977SLeo Liu #define UVD_LMI_ADP_IND_DATA__DATA_MASK 0xFFFFFFFFL 4799a5a25977SLeo Liu //UVD_LMI_ADP_PF_EN 4800a5a25977SLeo Liu #define UVD_LMI_ADP_PF_EN__VCPU_CACHE0_PF_EN__SHIFT 0x0 4801a5a25977SLeo Liu #define UVD_LMI_ADP_PF_EN__VCPU_CACHE1_PF_EN__SHIFT 0x1 4802a5a25977SLeo Liu #define UVD_LMI_ADP_PF_EN__VCPU_CACHE2_PF_EN__SHIFT 0x2 4803a5a25977SLeo Liu #define UVD_LMI_ADP_PF_EN__VCPU_CACHE0_PF_EN_MASK 0x00000001L 4804a5a25977SLeo Liu #define UVD_LMI_ADP_PF_EN__VCPU_CACHE1_PF_EN_MASK 0x00000002L 4805a5a25977SLeo Liu #define UVD_LMI_ADP_PF_EN__VCPU_CACHE2_PF_EN_MASK 0x00000004L 4806a5a25977SLeo Liu //UVD_LMI_ADP_CNN_CTRL 4807a5a25977SLeo Liu #define UVD_LMI_ADP_CNN_CTRL__CNN_MODE_EN__SHIFT 0x0 4808a5a25977SLeo Liu #define UVD_LMI_ADP_CNN_CTRL__CNN_MODE_EN_MASK 0x00000001L 4809a5a25977SLeo Liu //UVD_LMI_PREF_CTRL 4810a5a25977SLeo Liu #define UVD_LMI_PREF_CTRL__PREF_RST__SHIFT 0x0 4811a5a25977SLeo Liu #define UVD_LMI_PREF_CTRL__PREF_BUSY_STATUS__SHIFT 0x1 4812a5a25977SLeo Liu #define UVD_LMI_PREF_CTRL__PREF_WSTRB__SHIFT 0x2 4813a5a25977SLeo Liu #define UVD_LMI_PREF_CTRL__PREF_WRITE_SIZE__SHIFT 0x3 4814a5a25977SLeo Liu #define UVD_LMI_PREF_CTRL__PREF_STEP_SIZE__SHIFT 0x4 4815a5a25977SLeo Liu #define UVD_LMI_PREF_CTRL__PREF_SIZE__SHIFT 0x13 4816a5a25977SLeo Liu #define UVD_LMI_PREF_CTRL__PREF_RST_MASK 0x00000001L 4817a5a25977SLeo Liu #define UVD_LMI_PREF_CTRL__PREF_BUSY_STATUS_MASK 0x00000002L 4818a5a25977SLeo Liu #define UVD_LMI_PREF_CTRL__PREF_WSTRB_MASK 0x00000004L 4819a5a25977SLeo Liu #define UVD_LMI_PREF_CTRL__PREF_WRITE_SIZE_MASK 0x00000008L 4820a5a25977SLeo Liu #define UVD_LMI_PREF_CTRL__PREF_STEP_SIZE_MASK 0x00000070L 4821a5a25977SLeo Liu #define UVD_LMI_PREF_CTRL__PREF_SIZE_MASK 0xFFF80000L 4822a5a25977SLeo Liu //UVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW 4823a5a25977SLeo Liu #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4824a5a25977SLeo Liu #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4825a5a25977SLeo Liu //UVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH 4826a5a25977SLeo Liu #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4827a5a25977SLeo Liu #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4828a5a25977SLeo Liu 4829a5a25977SLeo Liu 4830a5a25977SLeo Liu // addressBlock: uvdctxind 4831a5a25977SLeo Liu //UVD_CGC_MEM_CTRL 4832a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 4833a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 4834a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 4835a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 4836a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 4837a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 4838a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 4839a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 4840a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 4841a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 4842a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 4843a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 4844a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 4845a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__MMSCH_LS_EN__SHIFT 0xe 4846a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__MPC1_LS_EN__SHIFT 0xf 4847a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 4848a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 4849a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x00000001L 4850a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x00000002L 4851a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x00000004L 4852a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x00000008L 4853a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x00000010L 4854a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x00000020L 4855a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x00000040L 4856a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x00000080L 4857a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x00000100L 4858a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x00000200L 4859a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x00000400L 4860a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x00001000L 4861a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x00002000L 4862a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__MMSCH_LS_EN_MASK 0x00004000L 4863a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__MPC1_LS_EN_MASK 0x00008000L 4864a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L 4865a5a25977SLeo Liu #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L 4866a5a25977SLeo Liu //UVD_CGC_CTRL2 4867a5a25977SLeo Liu #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 4868a5a25977SLeo Liu #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 4869a5a25977SLeo Liu #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 4870a5a25977SLeo Liu #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L 4871a5a25977SLeo Liu #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L 4872a5a25977SLeo Liu #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001CL 4873a5a25977SLeo Liu //UVD_CGC_MEM_DS_CTRL 4874a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN__SHIFT 0x0 4875a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN__SHIFT 0x1 4876a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN__SHIFT 0x2 4877a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN__SHIFT 0x3 4878a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN__SHIFT 0x4 4879a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN__SHIFT 0x5 4880a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN__SHIFT 0x6 4881a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN__SHIFT 0x7 4882a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN__SHIFT 0x8 4883a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN__SHIFT 0x9 4884a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN__SHIFT 0xa 4885a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN__SHIFT 0xc 4886a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN__SHIFT 0xd 4887a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN__SHIFT 0xe 4888a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN__SHIFT 0xf 4889a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN_MASK 0x00000001L 4890a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN_MASK 0x00000002L 4891a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN_MASK 0x00000004L 4892a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN_MASK 0x00000008L 4893a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN_MASK 0x00000010L 4894a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN_MASK 0x00000020L 4895a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN_MASK 0x00000040L 4896a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN_MASK 0x00000080L 4897a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN_MASK 0x00000100L 4898a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN_MASK 0x00000200L 4899a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN_MASK 0x00000400L 4900a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN_MASK 0x00001000L 4901a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN_MASK 0x00002000L 4902a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN_MASK 0x00004000L 4903a5a25977SLeo Liu #define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN_MASK 0x00008000L 4904a5a25977SLeo Liu //UVD_CGC_MEM_SD_CTRL 4905a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__LMI_MC_SD_EN__SHIFT 0x0 4906a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__MPC_SD_EN__SHIFT 0x1 4907a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__MPRD_SD_EN__SHIFT 0x2 4908a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__WCB_SD_EN__SHIFT 0x3 4909a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__UDEC_RE_SD_EN__SHIFT 0x4 4910a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN__SHIFT 0x5 4911a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__UDEC_IT_SD_EN__SHIFT 0x6 4912a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__UDEC_DB_SD_EN__SHIFT 0x7 4913a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__UDEC_MP_SD_EN__SHIFT 0x8 4914a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__SYS_SD_EN__SHIFT 0x9 4915a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN__SHIFT 0xa 4916a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__MIF_SD_EN__SHIFT 0xc 4917a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__LCM_SD_EN__SHIFT 0xd 4918a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__MMSCH_SD_EN__SHIFT 0xe 4919a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__MPC1_SD_EN__SHIFT 0xf 4920a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__LMI_MC_SD_EN_MASK 0x00000001L 4921a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__MPC_SD_EN_MASK 0x00000002L 4922a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__MPRD_SD_EN_MASK 0x00000004L 4923a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__WCB_SD_EN_MASK 0x00000008L 4924a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__UDEC_RE_SD_EN_MASK 0x00000010L 4925a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN_MASK 0x00000020L 4926a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__UDEC_IT_SD_EN_MASK 0x00000040L 4927a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__UDEC_DB_SD_EN_MASK 0x00000080L 4928a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__UDEC_MP_SD_EN_MASK 0x00000100L 4929a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__SYS_SD_EN_MASK 0x00000200L 4930a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN_MASK 0x00000400L 4931a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__MIF_SD_EN_MASK 0x00001000L 4932a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__LCM_SD_EN_MASK 0x00002000L 4933a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__MMSCH_SD_EN_MASK 0x00004000L 4934a5a25977SLeo Liu #define UVD_CGC_MEM_SD_CTRL__MPC1_SD_EN_MASK 0x00008000L 4935a5a25977SLeo Liu //UVD_SW_SCRATCH_00 4936a5a25977SLeo Liu #define UVD_SW_SCRATCH_00__DATA__SHIFT 0x0 4937a5a25977SLeo Liu #define UVD_SW_SCRATCH_00__DATA_MASK 0xFFFFFFFFL 4938a5a25977SLeo Liu //UVD_SW_SCRATCH_01 4939a5a25977SLeo Liu #define UVD_SW_SCRATCH_01__DATA__SHIFT 0x0 4940a5a25977SLeo Liu #define UVD_SW_SCRATCH_01__DATA_MASK 0xFFFFFFFFL 4941a5a25977SLeo Liu //UVD_SW_SCRATCH_02 4942a5a25977SLeo Liu #define UVD_SW_SCRATCH_02__DATA__SHIFT 0x0 4943a5a25977SLeo Liu #define UVD_SW_SCRATCH_02__DATA_MASK 0xFFFFFFFFL 4944a5a25977SLeo Liu //UVD_SW_SCRATCH_03 4945a5a25977SLeo Liu #define UVD_SW_SCRATCH_03__DATA__SHIFT 0x0 4946a5a25977SLeo Liu #define UVD_SW_SCRATCH_03__DATA_MASK 0xFFFFFFFFL 4947a5a25977SLeo Liu //UVD_SW_SCRATCH_04 4948a5a25977SLeo Liu #define UVD_SW_SCRATCH_04__DATA__SHIFT 0x0 4949a5a25977SLeo Liu #define UVD_SW_SCRATCH_04__DATA_MASK 0xFFFFFFFFL 4950a5a25977SLeo Liu //UVD_SW_SCRATCH_05 4951a5a25977SLeo Liu #define UVD_SW_SCRATCH_05__DATA__SHIFT 0x0 4952a5a25977SLeo Liu #define UVD_SW_SCRATCH_05__DATA_MASK 0xFFFFFFFFL 4953a5a25977SLeo Liu //UVD_SW_SCRATCH_06 4954a5a25977SLeo Liu #define UVD_SW_SCRATCH_06__DATA__SHIFT 0x0 4955a5a25977SLeo Liu #define UVD_SW_SCRATCH_06__DATA_MASK 0xFFFFFFFFL 4956a5a25977SLeo Liu //UVD_SW_SCRATCH_07 4957a5a25977SLeo Liu #define UVD_SW_SCRATCH_07__DATA__SHIFT 0x0 4958a5a25977SLeo Liu #define UVD_SW_SCRATCH_07__DATA_MASK 0xFFFFFFFFL 4959a5a25977SLeo Liu //UVD_SW_SCRATCH_08 4960a5a25977SLeo Liu #define UVD_SW_SCRATCH_08__DATA__SHIFT 0x0 4961a5a25977SLeo Liu #define UVD_SW_SCRATCH_08__DATA_MASK 0xFFFFFFFFL 4962a5a25977SLeo Liu //UVD_SW_SCRATCH_09 4963a5a25977SLeo Liu #define UVD_SW_SCRATCH_09__DATA__SHIFT 0x0 4964a5a25977SLeo Liu #define UVD_SW_SCRATCH_09__DATA_MASK 0xFFFFFFFFL 4965a5a25977SLeo Liu //UVD_SW_SCRATCH_10 4966a5a25977SLeo Liu #define UVD_SW_SCRATCH_10__DATA__SHIFT 0x0 4967a5a25977SLeo Liu #define UVD_SW_SCRATCH_10__DATA_MASK 0xFFFFFFFFL 4968a5a25977SLeo Liu //UVD_SW_SCRATCH_11 4969a5a25977SLeo Liu #define UVD_SW_SCRATCH_11__DATA__SHIFT 0x0 4970a5a25977SLeo Liu #define UVD_SW_SCRATCH_11__DATA_MASK 0xFFFFFFFFL 4971a5a25977SLeo Liu //UVD_SW_SCRATCH_12 4972a5a25977SLeo Liu #define UVD_SW_SCRATCH_12__DATA__SHIFT 0x0 4973a5a25977SLeo Liu #define UVD_SW_SCRATCH_12__DATA_MASK 0xFFFFFFFFL 4974a5a25977SLeo Liu //UVD_SW_SCRATCH_13 4975a5a25977SLeo Liu #define UVD_SW_SCRATCH_13__DATA__SHIFT 0x0 4976a5a25977SLeo Liu #define UVD_SW_SCRATCH_13__DATA_MASK 0xFFFFFFFFL 4977a5a25977SLeo Liu //UVD_SW_SCRATCH_14 4978a5a25977SLeo Liu #define UVD_SW_SCRATCH_14__DATA__SHIFT 0x0 4979a5a25977SLeo Liu #define UVD_SW_SCRATCH_14__DATA_MASK 0xFFFFFFFFL 4980a5a25977SLeo Liu //UVD_SW_SCRATCH_15 4981a5a25977SLeo Liu #define UVD_SW_SCRATCH_15__DATA__SHIFT 0x0 4982a5a25977SLeo Liu #define UVD_SW_SCRATCH_15__DATA_MASK 0xFFFFFFFFL 4983a5a25977SLeo Liu //UVD_MEMCHECK_SYS_INT_EN 4984a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__RE_ERR_EN__SHIFT 0x0 4985a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__IT_ERR_EN__SHIFT 0x1 4986a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MP_ERR_EN__SHIFT 0x2 4987a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__DB_ERR_EN__SHIFT 0x3 4988a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__DBW_ERR_EN__SHIFT 0x4 4989a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__CM_ERR_EN__SHIFT 0x5 4990a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_REF_ERR_EN__SHIFT 0x6 4991a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__VCPU_ERR_EN__SHIFT 0x7 4992a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_DBW_ERR_EN__SHIFT 0x8 4993a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_CM_COLOC_ERR_EN__SHIFT 0x9 4994a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa 4995a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP1_ERR_EN__SHIFT 0xb 4996a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__SRE_ERR_EN__SHIFT 0xc 4997a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__IT_RD_ERR_EN__SHIFT 0xf 4998a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__CM_RD_ERR_EN__SHIFT 0x10 4999a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__DB_RD_ERR_EN__SHIFT 0x11 5000a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_RD_ERR_EN__SHIFT 0x12 5001a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__IDCT_RD_ERR_EN__SHIFT 0x13 5002a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MPC_RD_ERR_EN__SHIFT 0x14 5003a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__LBSI_RD_ERR_EN__SHIFT 0x15 5004a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__RBC_RD_ERR_EN__SHIFT 0x18 5005a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP2_ERR_EN__SHIFT 0x1b 5006a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP3_ERR_EN__SHIFT 0x1c 5007a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR_ERR_EN__SHIFT 0x1d 5008a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR2_ERR_EN__SHIFT 0x1e 5009a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__PREF_ERR_EN__SHIFT 0x1f 5010a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__RE_ERR_EN_MASK 0x00000001L 5011a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__IT_ERR_EN_MASK 0x00000002L 5012a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MP_ERR_EN_MASK 0x00000004L 5013a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__DB_ERR_EN_MASK 0x00000008L 5014a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__DBW_ERR_EN_MASK 0x00000010L 5015a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__CM_ERR_EN_MASK 0x00000020L 5016a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_REF_ERR_EN_MASK 0x00000040L 5017a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__VCPU_ERR_EN_MASK 0x00000080L 5018a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_DBW_ERR_EN_MASK 0x00000100L 5019a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_CM_COLOC_ERR_EN_MASK 0x00000200L 5020a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP0_ERR_EN_MASK 0x00000400L 5021a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP1_ERR_EN_MASK 0x00000800L 5022a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__SRE_ERR_EN_MASK 0x00001000L 5023a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__IT_RD_ERR_EN_MASK 0x00008000L 5024a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__CM_RD_ERR_EN_MASK 0x00010000L 5025a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__DB_RD_ERR_EN_MASK 0x00020000L 5026a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_RD_ERR_EN_MASK 0x00040000L 5027a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__IDCT_RD_ERR_EN_MASK 0x00080000L 5028a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MPC_RD_ERR_EN_MASK 0x00100000L 5029a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__LBSI_RD_ERR_EN_MASK 0x00200000L 5030a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__RBC_RD_ERR_EN_MASK 0x01000000L 5031a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP2_ERR_EN_MASK 0x08000000L 5032a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP3_ERR_EN_MASK 0x10000000L 5033a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR_ERR_EN_MASK 0x20000000L 5034a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR2_ERR_EN_MASK 0x40000000L 5035a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_EN__PREF_ERR_EN_MASK 0x80000000L 5036a5a25977SLeo Liu //UVD_MEMCHECK_SYS_INT_STAT 5037a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__RE_LO_ERR__SHIFT 0x0 5038a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__RE_HI_ERR__SHIFT 0x1 5039a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__IT_LO_ERR__SHIFT 0x2 5040a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__IT_HI_ERR__SHIFT 0x3 5041a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MP_LO_ERR__SHIFT 0x4 5042a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MP_HI_ERR__SHIFT 0x5 5043a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__DB_LO_ERR__SHIFT 0x6 5044a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__DB_HI_ERR__SHIFT 0x7 5045a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__DBW_LO_ERR__SHIFT 0x8 5046a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__DBW_HI_ERR__SHIFT 0x9 5047a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__CM_LO_ERR__SHIFT 0xa 5048a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__CM_HI_ERR__SHIFT 0xb 5049a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_LO_ERR__SHIFT 0xc 5050a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_HI_ERR__SHIFT 0xd 5051a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_LO_ERR__SHIFT 0xe 5052a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_HI_ERR__SHIFT 0xf 5053a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_LO_ERR__SHIFT 0x10 5054a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_HI_ERR__SHIFT 0x11 5055a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_LO_ERR__SHIFT 0x12 5056a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_HI_ERR__SHIFT 0x13 5057a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_LO_ERR__SHIFT 0x14 5058a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_HI_ERR__SHIFT 0x15 5059a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_LO_ERR__SHIFT 0x16 5060a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_HI_ERR__SHIFT 0x17 5061a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__SRE_LO_ERR__SHIFT 0x18 5062a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__SRE_HI_ERR__SHIFT 0x19 5063a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_LO_ERR__SHIFT 0x1e 5064a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_HI_ERR__SHIFT 0x1f 5065a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__RE_LO_ERR_MASK 0x00000001L 5066a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__RE_HI_ERR_MASK 0x00000002L 5067a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__IT_LO_ERR_MASK 0x00000004L 5068a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__IT_HI_ERR_MASK 0x00000008L 5069a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MP_LO_ERR_MASK 0x00000010L 5070a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MP_HI_ERR_MASK 0x00000020L 5071a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__DB_LO_ERR_MASK 0x00000040L 5072a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__DB_HI_ERR_MASK 0x00000080L 5073a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__DBW_LO_ERR_MASK 0x00000100L 5074a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__DBW_HI_ERR_MASK 0x00000200L 5075a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__CM_LO_ERR_MASK 0x00000400L 5076a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__CM_HI_ERR_MASK 0x00000800L 5077a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_LO_ERR_MASK 0x00001000L 5078a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_HI_ERR_MASK 0x00002000L 5079a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_LO_ERR_MASK 0x00004000L 5080a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_HI_ERR_MASK 0x00008000L 5081a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_LO_ERR_MASK 0x00010000L 5082a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_HI_ERR_MASK 0x00020000L 5083a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_LO_ERR_MASK 0x00040000L 5084a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_HI_ERR_MASK 0x00080000L 5085a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_LO_ERR_MASK 0x00100000L 5086a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_HI_ERR_MASK 0x00200000L 5087a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_LO_ERR_MASK 0x00400000L 5088a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_HI_ERR_MASK 0x00800000L 5089a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__SRE_LO_ERR_MASK 0x01000000L 5090a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__SRE_HI_ERR_MASK 0x02000000L 5091a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_LO_ERR_MASK 0x40000000L 5092a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_HI_ERR_MASK 0x80000000L 5093a5a25977SLeo Liu //UVD_MEMCHECK_SYS_INT_ACK 5094a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__RE_LO_ACK__SHIFT 0x0 5095a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__RE_HI_ACK__SHIFT 0x1 5096a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__IT_LO_ACK__SHIFT 0x2 5097a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__IT_HI_ACK__SHIFT 0x3 5098a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MP_LO_ACK__SHIFT 0x4 5099a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MP_HI_ACK__SHIFT 0x5 5100a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__DB_LO_ACK__SHIFT 0x6 5101a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__DB_HI_ACK__SHIFT 0x7 5102a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__DBW_LO_ACK__SHIFT 0x8 5103a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__DBW_HI_ACK__SHIFT 0x9 5104a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__CM_LO_ACK__SHIFT 0xa 5105a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__CM_HI_ACK__SHIFT 0xb 5106a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_LO_ACK__SHIFT 0xc 5107a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_HI_ACK__SHIFT 0xd 5108a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_LO_ACK__SHIFT 0xe 5109a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_HI_ACK__SHIFT 0xf 5110a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_LO_ACK__SHIFT 0x10 5111a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_HI_ACK__SHIFT 0x11 5112a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_LO_ACK__SHIFT 0x12 5113a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_HI_ACK__SHIFT 0x13 5114a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_LO_ACK__SHIFT 0x14 5115a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_HI_ACK__SHIFT 0x15 5116a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_LO_ACK__SHIFT 0x16 5117a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_HI_ACK__SHIFT 0x17 5118a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__SRE_LO_ACK__SHIFT 0x18 5119a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__SRE_HI_ACK__SHIFT 0x19 5120a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_LO_ACK__SHIFT 0x1e 5121a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_HI_ACK__SHIFT 0x1f 5122a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__RE_LO_ACK_MASK 0x00000001L 5123a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__RE_HI_ACK_MASK 0x00000002L 5124a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__IT_LO_ACK_MASK 0x00000004L 5125a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__IT_HI_ACK_MASK 0x00000008L 5126a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MP_LO_ACK_MASK 0x00000010L 5127a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MP_HI_ACK_MASK 0x00000020L 5128a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__DB_LO_ACK_MASK 0x00000040L 5129a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__DB_HI_ACK_MASK 0x00000080L 5130a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__DBW_LO_ACK_MASK 0x00000100L 5131a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__DBW_HI_ACK_MASK 0x00000200L 5132a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__CM_LO_ACK_MASK 0x00000400L 5133a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__CM_HI_ACK_MASK 0x00000800L 5134a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_LO_ACK_MASK 0x00001000L 5135a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_HI_ACK_MASK 0x00002000L 5136a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_LO_ACK_MASK 0x00004000L 5137a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_HI_ACK_MASK 0x00008000L 5138a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_LO_ACK_MASK 0x00010000L 5139a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_HI_ACK_MASK 0x00020000L 5140a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_LO_ACK_MASK 0x00040000L 5141a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_HI_ACK_MASK 0x00080000L 5142a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_LO_ACK_MASK 0x00100000L 5143a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_HI_ACK_MASK 0x00200000L 5144a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_LO_ACK_MASK 0x00400000L 5145a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_HI_ACK_MASK 0x00800000L 5146a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__SRE_LO_ACK_MASK 0x01000000L 5147a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__SRE_HI_ACK_MASK 0x02000000L 5148a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_LO_ACK_MASK 0x40000000L 5149a5a25977SLeo Liu #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_HI_ACK_MASK 0x80000000L 5150a5a25977SLeo Liu //UVD_MEMCHECK_VCPU_INT_EN 5151a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__RE_ERR_EN__SHIFT 0x0 5152a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__IT_ERR_EN__SHIFT 0x1 5153a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MP_ERR_EN__SHIFT 0x2 5154a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__DB_ERR_EN__SHIFT 0x3 5155a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__DBW_ERR_EN__SHIFT 0x4 5156a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__CM_ERR_EN__SHIFT 0x5 5157a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_REF_ERR_EN__SHIFT 0x6 5158a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__VCPU_ERR_EN__SHIFT 0x7 5159a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_DBW_ERR_EN__SHIFT 0x8 5160a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_CM_COLOC_ERR_EN__SHIFT 0x9 5161a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa 5162a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP1_ERR_EN__SHIFT 0xb 5163a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__SRE_ERR_EN__SHIFT 0xc 5164a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__IT_RD_ERR_EN__SHIFT 0xf 5165a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__CM_RD_ERR_EN__SHIFT 0x10 5166a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__DB_RD_ERR_EN__SHIFT 0x11 5167a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_RD_ERR_EN__SHIFT 0x12 5168a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__IDCT_RD_ERR_EN__SHIFT 0x13 5169a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MPC_RD_ERR_EN__SHIFT 0x14 5170a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__LBSI_RD_ERR_EN__SHIFT 0x15 5171a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__RBC_RD_ERR_EN__SHIFT 0x18 5172a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP2_ERR_EN__SHIFT 0x19 5173a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP3_ERR_EN__SHIFT 0x1a 5174a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR_ERR_EN__SHIFT 0x1b 5175a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR2_ERR_EN__SHIFT 0x1c 5176a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__PREF_ERR_EN__SHIFT 0x1d 5177a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__RE_ERR_EN_MASK 0x00000001L 5178a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__IT_ERR_EN_MASK 0x00000002L 5179a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MP_ERR_EN_MASK 0x00000004L 5180a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__DB_ERR_EN_MASK 0x00000008L 5181a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__DBW_ERR_EN_MASK 0x00000010L 5182a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__CM_ERR_EN_MASK 0x00000020L 5183a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_REF_ERR_EN_MASK 0x00000040L 5184a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__VCPU_ERR_EN_MASK 0x00000080L 5185a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_DBW_ERR_EN_MASK 0x00000100L 5186a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_CM_COLOC_ERR_EN_MASK 0x00000200L 5187a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP0_ERR_EN_MASK 0x00000400L 5188a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP1_ERR_EN_MASK 0x00000800L 5189a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__SRE_ERR_EN_MASK 0x00001000L 5190a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__IT_RD_ERR_EN_MASK 0x00008000L 5191a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__CM_RD_ERR_EN_MASK 0x00010000L 5192a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__DB_RD_ERR_EN_MASK 0x00020000L 5193a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_RD_ERR_EN_MASK 0x00040000L 5194a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__IDCT_RD_ERR_EN_MASK 0x00080000L 5195a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MPC_RD_ERR_EN_MASK 0x00100000L 5196a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__LBSI_RD_ERR_EN_MASK 0x00200000L 5197a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__RBC_RD_ERR_EN_MASK 0x01000000L 5198a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP2_ERR_EN_MASK 0x02000000L 5199a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP3_ERR_EN_MASK 0x04000000L 5200a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR_ERR_EN_MASK 0x08000000L 5201a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR2_ERR_EN_MASK 0x10000000L 5202a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_EN__PREF_ERR_EN_MASK 0x20000000L 5203a5a25977SLeo Liu //UVD_MEMCHECK_VCPU_INT_STAT 5204a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__RE_LO_ERR__SHIFT 0x0 5205a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__RE_HI_ERR__SHIFT 0x1 5206a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__IT_LO_ERR__SHIFT 0x2 5207a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__IT_HI_ERR__SHIFT 0x3 5208a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MP_LO_ERR__SHIFT 0x4 5209a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MP_HI_ERR__SHIFT 0x5 5210a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__DB_LO_ERR__SHIFT 0x6 5211a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__DB_HI_ERR__SHIFT 0x7 5212a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_LO_ERR__SHIFT 0x8 5213a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_HI_ERR__SHIFT 0x9 5214a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__CM_LO_ERR__SHIFT 0xa 5215a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__CM_HI_ERR__SHIFT 0xb 5216a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_LO_ERR__SHIFT 0xc 5217a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_HI_ERR__SHIFT 0xd 5218a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_LO_ERR__SHIFT 0xe 5219a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_HI_ERR__SHIFT 0xf 5220a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_LO_ERR__SHIFT 0x10 5221a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_HI_ERR__SHIFT 0x11 5222a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_LO_ERR__SHIFT 0x12 5223a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_HI_ERR__SHIFT 0x13 5224a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_LO_ERR__SHIFT 0x14 5225a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_HI_ERR__SHIFT 0x15 5226a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_LO_ERR__SHIFT 0x16 5227a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_HI_ERR__SHIFT 0x17 5228a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_LO_ERR__SHIFT 0x18 5229a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_HI_ERR__SHIFT 0x19 5230a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_LO_ERR__SHIFT 0x1e 5231a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_HI_ERR__SHIFT 0x1f 5232a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__RE_LO_ERR_MASK 0x00000001L 5233a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__RE_HI_ERR_MASK 0x00000002L 5234a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__IT_LO_ERR_MASK 0x00000004L 5235a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__IT_HI_ERR_MASK 0x00000008L 5236a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MP_LO_ERR_MASK 0x00000010L 5237a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MP_HI_ERR_MASK 0x00000020L 5238a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__DB_LO_ERR_MASK 0x00000040L 5239a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__DB_HI_ERR_MASK 0x00000080L 5240a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_LO_ERR_MASK 0x00000100L 5241a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_HI_ERR_MASK 0x00000200L 5242a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__CM_LO_ERR_MASK 0x00000400L 5243a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__CM_HI_ERR_MASK 0x00000800L 5244a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_LO_ERR_MASK 0x00001000L 5245a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_HI_ERR_MASK 0x00002000L 5246a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_LO_ERR_MASK 0x00004000L 5247a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_HI_ERR_MASK 0x00008000L 5248a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_LO_ERR_MASK 0x00010000L 5249a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_HI_ERR_MASK 0x00020000L 5250a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_LO_ERR_MASK 0x00040000L 5251a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_HI_ERR_MASK 0x00080000L 5252a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_LO_ERR_MASK 0x00100000L 5253a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_HI_ERR_MASK 0x00200000L 5254a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_LO_ERR_MASK 0x00400000L 5255a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_HI_ERR_MASK 0x00800000L 5256a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_LO_ERR_MASK 0x01000000L 5257a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_HI_ERR_MASK 0x02000000L 5258a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_LO_ERR_MASK 0x40000000L 5259a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_HI_ERR_MASK 0x80000000L 5260a5a25977SLeo Liu //UVD_MEMCHECK_VCPU_INT_ACK 5261a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__RE_LO_ACK__SHIFT 0x0 5262a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__RE_HI_ACK__SHIFT 0x1 5263a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__IT_LO_ACK__SHIFT 0x2 5264a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__IT_HI_ACK__SHIFT 0x3 5265a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MP_LO_ACK__SHIFT 0x4 5266a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MP_HI_ACK__SHIFT 0x5 5267a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__DB_LO_ACK__SHIFT 0x6 5268a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__DB_HI_ACK__SHIFT 0x7 5269a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_LO_ACK__SHIFT 0x8 5270a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_HI_ACK__SHIFT 0x9 5271a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__CM_LO_ACK__SHIFT 0xa 5272a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__CM_HI_ACK__SHIFT 0xb 5273a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_LO_ACK__SHIFT 0xc 5274a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_HI_ACK__SHIFT 0xd 5275a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_LO_ACK__SHIFT 0xe 5276a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_HI_ACK__SHIFT 0xf 5277a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_LO_ACK__SHIFT 0x10 5278a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_HI_ACK__SHIFT 0x11 5279a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_LO_ACK__SHIFT 0x12 5280a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_HI_ACK__SHIFT 0x13 5281a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_LO_ACK__SHIFT 0x14 5282a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_HI_ACK__SHIFT 0x15 5283a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_LO_ACK__SHIFT 0x16 5284a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_HI_ACK__SHIFT 0x17 5285a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_LO_ACK__SHIFT 0x18 5286a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_HI_ACK__SHIFT 0x19 5287a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_LO_ACK__SHIFT 0x1e 5288a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_HI_ACK__SHIFT 0x1f 5289a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__RE_LO_ACK_MASK 0x00000001L 5290a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__RE_HI_ACK_MASK 0x00000002L 5291a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__IT_LO_ACK_MASK 0x00000004L 5292a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__IT_HI_ACK_MASK 0x00000008L 5293a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MP_LO_ACK_MASK 0x00000010L 5294a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MP_HI_ACK_MASK 0x00000020L 5295a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__DB_LO_ACK_MASK 0x00000040L 5296a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__DB_HI_ACK_MASK 0x00000080L 5297a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_LO_ACK_MASK 0x00000100L 5298a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_HI_ACK_MASK 0x00000200L 5299a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__CM_LO_ACK_MASK 0x00000400L 5300a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__CM_HI_ACK_MASK 0x00000800L 5301a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_LO_ACK_MASK 0x00001000L 5302a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_HI_ACK_MASK 0x00002000L 5303a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_LO_ACK_MASK 0x00004000L 5304a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_HI_ACK_MASK 0x00008000L 5305a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_LO_ACK_MASK 0x00010000L 5306a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_HI_ACK_MASK 0x00020000L 5307a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_LO_ACK_MASK 0x00040000L 5308a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_HI_ACK_MASK 0x00080000L 5309a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_LO_ACK_MASK 0x00100000L 5310a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_HI_ACK_MASK 0x00200000L 5311a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_LO_ACK_MASK 0x00400000L 5312a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_HI_ACK_MASK 0x00800000L 5313a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_LO_ACK_MASK 0x01000000L 5314a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_HI_ACK_MASK 0x02000000L 5315a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_LO_ACK_MASK 0x40000000L 5316a5a25977SLeo Liu #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_HI_ACK_MASK 0x80000000L 5317a5a25977SLeo Liu //UVD_MEMCHECK2_SYS_INT_STAT 5318a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_LO_ERR__SHIFT 0x0 5319a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_HI_ERR__SHIFT 0x1 5320a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_LO_ERR__SHIFT 0x2 5321a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_HI_ERR__SHIFT 0x3 5322a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_LO_ERR__SHIFT 0x4 5323a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5 5324a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_LO_ERR__SHIFT 0x6 5325a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_HI_ERR__SHIFT 0x7 5326a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_LO_ERR__SHIFT 0x8 5327a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_HI_ERR__SHIFT 0x9 5328a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa 5329a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_HI_ERR__SHIFT 0xb 5330a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_LO_ERR__SHIFT 0x10 5331a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_HI_ERR__SHIFT 0x11 5332a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_LO_ERR__SHIFT 0x16 5333a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_HI_ERR__SHIFT 0x17 5334a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_LO_ERR__SHIFT 0x18 5335a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_HI_ERR__SHIFT 0x19 5336a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_LO_ERR__SHIFT 0x1a 5337a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_HI_ERR__SHIFT 0x1b 5338a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_LO_ERR__SHIFT 0x1c 5339a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_HI_ERR__SHIFT 0x1d 5340a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_LO_ERR__SHIFT 0x1e 5341a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_HI_ERR__SHIFT 0x1f 5342a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_LO_ERR_MASK 0x00000001L 5343a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_HI_ERR_MASK 0x00000002L 5344a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_LO_ERR_MASK 0x00000004L 5345a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_HI_ERR_MASK 0x00000008L 5346a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_LO_ERR_MASK 0x00000010L 5347a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_HI_ERR_MASK 0x00000020L 5348a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_LO_ERR_MASK 0x00000040L 5349a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_HI_ERR_MASK 0x00000080L 5350a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_LO_ERR_MASK 0x00000100L 5351a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_HI_ERR_MASK 0x00000200L 5352a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR_MASK 0x00000400L 5353a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_HI_ERR_MASK 0x00000800L 5354a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_LO_ERR_MASK 0x00010000L 5355a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_HI_ERR_MASK 0x00020000L 5356a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_LO_ERR_MASK 0x00400000L 5357a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_HI_ERR_MASK 0x00800000L 5358a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_LO_ERR_MASK 0x01000000L 5359a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_HI_ERR_MASK 0x02000000L 5360a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_LO_ERR_MASK 0x04000000L 5361a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_HI_ERR_MASK 0x08000000L 5362a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_LO_ERR_MASK 0x10000000L 5363a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_HI_ERR_MASK 0x20000000L 5364a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_LO_ERR_MASK 0x40000000L 5365a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_HI_ERR_MASK 0x80000000L 5366a5a25977SLeo Liu //UVD_MEMCHECK2_SYS_INT_ACK 5367a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_LO_ACK__SHIFT 0x0 5368a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_HI_ACK__SHIFT 0x1 5369a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_LO_ACK__SHIFT 0x2 5370a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_HI_ACK__SHIFT 0x3 5371a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_LO_ACK__SHIFT 0x4 5372a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5 5373a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_LO_ACK__SHIFT 0x6 5374a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_HI_ACK__SHIFT 0x7 5375a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_LO_ACK__SHIFT 0x8 5376a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_HI_ACK__SHIFT 0x9 5377a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa 5378a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_HI_ACK__SHIFT 0xb 5379a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_LO_ACK__SHIFT 0x10 5380a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_HI_ACK__SHIFT 0x11 5381a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_LO_ACK__SHIFT 0x16 5382a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_HI_ACK__SHIFT 0x17 5383a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_LO_ACK__SHIFT 0x18 5384a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_HI_ACK__SHIFT 0x19 5385a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_LO_ACK__SHIFT 0x1a 5386a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_HI_ACK__SHIFT 0x1b 5387a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_LO_ACK__SHIFT 0x1c 5388a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_HI_ACK__SHIFT 0x1d 5389a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_LO_ACK__SHIFT 0x1e 5390a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_HI_ACK__SHIFT 0x1f 5391a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_LO_ACK_MASK 0x00000001L 5392a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_HI_ACK_MASK 0x00000002L 5393a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_LO_ACK_MASK 0x00000004L 5394a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_HI_ACK_MASK 0x00000008L 5395a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_LO_ACK_MASK 0x00000010L 5396a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_HI_ACK_MASK 0x00000020L 5397a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_LO_ACK_MASK 0x00000040L 5398a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_HI_ACK_MASK 0x00000080L 5399a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_LO_ACK_MASK 0x00000100L 5400a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_HI_ACK_MASK 0x00000200L 5401a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK_MASK 0x00000400L 5402a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_HI_ACK_MASK 0x00000800L 5403a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_LO_ACK_MASK 0x00010000L 5404a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_HI_ACK_MASK 0x00020000L 5405a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_LO_ACK_MASK 0x00400000L 5406a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_HI_ACK_MASK 0x00800000L 5407a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_LO_ACK_MASK 0x01000000L 5408a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_HI_ACK_MASK 0x02000000L 5409a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_LO_ACK_MASK 0x04000000L 5410a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_HI_ACK_MASK 0x08000000L 5411a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_LO_ACK_MASK 0x10000000L 5412a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_HI_ACK_MASK 0x20000000L 5413a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_LO_ACK_MASK 0x40000000L 5414a5a25977SLeo Liu #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_HI_ACK_MASK 0x80000000L 5415a5a25977SLeo Liu //UVD_MEMCHECK2_VCPU_INT_STAT 5416a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_LO_ERR__SHIFT 0x0 5417a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_HI_ERR__SHIFT 0x1 5418a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_LO_ERR__SHIFT 0x2 5419a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_HI_ERR__SHIFT 0x3 5420a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_LO_ERR__SHIFT 0x4 5421a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5 5422a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_LO_ERR__SHIFT 0x6 5423a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_HI_ERR__SHIFT 0x7 5424a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_LO_ERR__SHIFT 0x8 5425a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_HI_ERR__SHIFT 0x9 5426a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa 5427a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_HI_ERR__SHIFT 0xb 5428a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_LO_ERR__SHIFT 0x10 5429a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_HI_ERR__SHIFT 0x11 5430a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_LO_ERR__SHIFT 0x12 5431a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_HI_ERR__SHIFT 0x13 5432a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_LO_ERR__SHIFT 0x14 5433a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_HI_ERR__SHIFT 0x15 5434a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_LO_ERR__SHIFT 0x16 5435a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_HI_ERR__SHIFT 0x17 5436a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_LO_ERR__SHIFT 0x18 5437a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_HI_ERR__SHIFT 0x19 5438a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_LO_ERR__SHIFT 0x1a 5439a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_HI_ERR__SHIFT 0x1b 5440a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_LO_ERR_MASK 0x00000001L 5441a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_HI_ERR_MASK 0x00000002L 5442a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_LO_ERR_MASK 0x00000004L 5443a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_HI_ERR_MASK 0x00000008L 5444a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_LO_ERR_MASK 0x00000010L 5445a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_HI_ERR_MASK 0x00000020L 5446a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_LO_ERR_MASK 0x00000040L 5447a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_HI_ERR_MASK 0x00000080L 5448a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_LO_ERR_MASK 0x00000100L 5449a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_HI_ERR_MASK 0x00000200L 5450a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR_MASK 0x00000400L 5451a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_HI_ERR_MASK 0x00000800L 5452a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_LO_ERR_MASK 0x00010000L 5453a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_HI_ERR_MASK 0x00020000L 5454a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_LO_ERR_MASK 0x00040000L 5455a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_HI_ERR_MASK 0x00080000L 5456a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_LO_ERR_MASK 0x00100000L 5457a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_HI_ERR_MASK 0x00200000L 5458a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_LO_ERR_MASK 0x00400000L 5459a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_HI_ERR_MASK 0x00800000L 5460a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_LO_ERR_MASK 0x01000000L 5461a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_HI_ERR_MASK 0x02000000L 5462a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_LO_ERR_MASK 0x04000000L 5463a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_HI_ERR_MASK 0x08000000L 5464a5a25977SLeo Liu //UVD_MEMCHECK2_VCPU_INT_ACK 5465a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_LO_ACK__SHIFT 0x0 5466a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_HI_ACK__SHIFT 0x1 5467a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_LO_ACK__SHIFT 0x2 5468a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_HI_ACK__SHIFT 0x3 5469a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_LO_ACK__SHIFT 0x4 5470a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5 5471a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_LO_ACK__SHIFT 0x6 5472a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_HI_ACK__SHIFT 0x7 5473a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_LO_ACK__SHIFT 0x8 5474a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_HI_ACK__SHIFT 0x9 5475a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa 5476a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_HI_ACK__SHIFT 0xb 5477a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_LO_ACK__SHIFT 0x10 5478a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_HI_ACK__SHIFT 0x11 5479a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_LO_ACK__SHIFT 0x12 5480a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_HI_ACK__SHIFT 0x13 5481a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_LO_ACK__SHIFT 0x14 5482a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_HI_ACK__SHIFT 0x15 5483a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_LO_ACK__SHIFT 0x16 5484a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_HI_ACK__SHIFT 0x17 5485a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_LO_ACK__SHIFT 0x18 5486a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_HI_ACK__SHIFT 0x19 5487a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK__SHIFT 0x1a 5488a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK__SHIFT 0x1b 5489a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_LO_ACK_MASK 0x00000001L 5490a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_HI_ACK_MASK 0x00000002L 5491a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_LO_ACK_MASK 0x00000004L 5492a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_HI_ACK_MASK 0x00000008L 5493a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_LO_ACK_MASK 0x00000010L 5494a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_HI_ACK_MASK 0x00000020L 5495a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_LO_ACK_MASK 0x00000040L 5496a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_HI_ACK_MASK 0x00000080L 5497a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_LO_ACK_MASK 0x00000100L 5498a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_HI_ACK_MASK 0x00000200L 5499a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK_MASK 0x00000400L 5500a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_HI_ACK_MASK 0x00000800L 5501a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_LO_ACK_MASK 0x00010000L 5502a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_HI_ACK_MASK 0x00020000L 5503a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_LO_ACK_MASK 0x00040000L 5504a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_HI_ACK_MASK 0x00080000L 5505a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_LO_ACK_MASK 0x00100000L 5506a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_HI_ACK_MASK 0x00200000L 5507a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_LO_ACK_MASK 0x00400000L 5508a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_HI_ACK_MASK 0x00800000L 5509a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_LO_ACK_MASK 0x01000000L 5510a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_HI_ACK_MASK 0x02000000L 5511a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK_MASK 0x04000000L 5512a5a25977SLeo Liu #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK_MASK 0x08000000L 5513a5a25977SLeo Liu //UVD_IH_SEM_CTRL 5514a5a25977SLeo Liu #define UVD_IH_SEM_CTRL__IH_STALL_EN__SHIFT 0x0 5515a5a25977SLeo Liu #define UVD_IH_SEM_CTRL__SEM_STALL_EN__SHIFT 0x1 5516a5a25977SLeo Liu #define UVD_IH_SEM_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 5517a5a25977SLeo Liu #define UVD_IH_SEM_CTRL__SEM_STATUS_CLEAN__SHIFT 0x3 5518a5a25977SLeo Liu #define UVD_IH_SEM_CTRL__IH_VMID__SHIFT 0x4 5519a5a25977SLeo Liu #define UVD_IH_SEM_CTRL__IH_USER_DATA__SHIFT 0x8 5520a5a25977SLeo Liu #define UVD_IH_SEM_CTRL__IH_RINGID__SHIFT 0x14 5521a5a25977SLeo Liu #define UVD_IH_SEM_CTRL__IH_STALL_EN_MASK 0x00000001L 5522a5a25977SLeo Liu #define UVD_IH_SEM_CTRL__SEM_STALL_EN_MASK 0x00000002L 5523a5a25977SLeo Liu #define UVD_IH_SEM_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 5524a5a25977SLeo Liu #define UVD_IH_SEM_CTRL__SEM_STATUS_CLEAN_MASK 0x00000008L 5525a5a25977SLeo Liu #define UVD_IH_SEM_CTRL__IH_VMID_MASK 0x000000F0L 5526a5a25977SLeo Liu #define UVD_IH_SEM_CTRL__IH_USER_DATA_MASK 0x000FFF00L 5527a5a25977SLeo Liu #define UVD_IH_SEM_CTRL__IH_RINGID_MASK 0x0FF00000L 5528a5a25977SLeo Liu 5529a5a25977SLeo Liu 5530a5a25977SLeo Liu #endif 5531