1*b77a9fdfSHawking Zhang /* 2*b77a9fdfSHawking Zhang * Copyright 2020 Advanced Micro Devices, Inc. 3*b77a9fdfSHawking Zhang * 4*b77a9fdfSHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5*b77a9fdfSHawking Zhang * copy of this software and associated documentation files (the "Software"), 6*b77a9fdfSHawking Zhang * to deal in the Software without restriction, including without limitation 7*b77a9fdfSHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b77a9fdfSHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9*b77a9fdfSHawking Zhang * Software is furnished to do so, subject to the following conditions: 10*b77a9fdfSHawking Zhang * 11*b77a9fdfSHawking Zhang * The above copyright notice and this permission notice shall be included in 12*b77a9fdfSHawking Zhang * all copies or substantial portions of the Software. 13*b77a9fdfSHawking Zhang * 14*b77a9fdfSHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b77a9fdfSHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b77a9fdfSHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b77a9fdfSHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b77a9fdfSHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b77a9fdfSHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b77a9fdfSHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21*b77a9fdfSHawking Zhang * 22*b77a9fdfSHawking Zhang */ 23*b77a9fdfSHawking Zhang #ifndef _vcn_2_6_0_SH_MASK_HEADER 24*b77a9fdfSHawking Zhang #define _vcn_2_6_0_SH_MASK_HEADER 25*b77a9fdfSHawking Zhang 26*b77a9fdfSHawking Zhang 27*b77a9fdfSHawking Zhang // addressBlock: uvd0_ecpudec 28*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_OFFSET0 29*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 30*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL 31*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_SIZE0 32*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 33*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL 34*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_OFFSET1 35*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 36*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL 37*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_SIZE1 38*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 39*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL 40*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_OFFSET2 41*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 42*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL 43*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_SIZE2 44*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 45*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL 46*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_OFFSET3 47*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0 48*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL 49*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_SIZE3 50*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0 51*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL 52*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_OFFSET4 53*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0 54*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL 55*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_SIZE4 56*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0 57*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL 58*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_OFFSET5 59*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0 60*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL 61*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_SIZE5 62*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0 63*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL 64*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_OFFSET6 65*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0 66*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL 67*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_SIZE6 68*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0 69*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL 70*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_OFFSET7 71*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0 72*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL 73*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_SIZE7 74*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0 75*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL 76*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_OFFSET8 77*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0 78*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL 79*b77a9fdfSHawking Zhang //UVD_VCPU_CACHE_SIZE8 80*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0 81*b77a9fdfSHawking Zhang #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL 82*b77a9fdfSHawking Zhang //UVD_VCPU_NONCACHE_OFFSET0 83*b77a9fdfSHawking Zhang #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0 84*b77a9fdfSHawking Zhang #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL 85*b77a9fdfSHawking Zhang //UVD_VCPU_NONCACHE_SIZE0 86*b77a9fdfSHawking Zhang #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0 87*b77a9fdfSHawking Zhang #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL 88*b77a9fdfSHawking Zhang //UVD_VCPU_NONCACHE_OFFSET1 89*b77a9fdfSHawking Zhang #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0 90*b77a9fdfSHawking Zhang #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL 91*b77a9fdfSHawking Zhang //UVD_VCPU_NONCACHE_SIZE1 92*b77a9fdfSHawking Zhang #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0 93*b77a9fdfSHawking Zhang #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL 94*b77a9fdfSHawking Zhang //UVD_VCPU_CNTL 95*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 96*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 97*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 98*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 99*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 100*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 101*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 102*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 103*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 104*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 105*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 106*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__BLK_RST__SHIFT 0x1c 107*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL 108*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L 109*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L 110*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L 111*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L 112*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L 113*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L 114*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L 115*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L 116*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L 117*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 118*b77a9fdfSHawking Zhang #define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L 119*b77a9fdfSHawking Zhang //UVD_VCPU_PRID 120*b77a9fdfSHawking Zhang #define UVD_VCPU_PRID__PRID__SHIFT 0x0 121*b77a9fdfSHawking Zhang #define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL 122*b77a9fdfSHawking Zhang //UVD_VCPU_TRCE 123*b77a9fdfSHawking Zhang #define UVD_VCPU_TRCE__PC__SHIFT 0x0 124*b77a9fdfSHawking Zhang #define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL 125*b77a9fdfSHawking Zhang //UVD_VCPU_TRCE_RD 126*b77a9fdfSHawking Zhang #define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0 127*b77a9fdfSHawking Zhang #define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL 128*b77a9fdfSHawking Zhang //UVD_VCPU_IND_INDEX 129*b77a9fdfSHawking Zhang #define UVD_VCPU_IND_INDEX__INDEX__SHIFT 0x0 130*b77a9fdfSHawking Zhang #define UVD_VCPU_IND_INDEX__INDEX_MASK 0x000001FFL 131*b77a9fdfSHawking Zhang //UVD_VCPU_IND_DATA 132*b77a9fdfSHawking Zhang #define UVD_VCPU_IND_DATA__DATA__SHIFT 0x0 133*b77a9fdfSHawking Zhang #define UVD_VCPU_IND_DATA__DATA_MASK 0xFFFFFFFFL 134*b77a9fdfSHawking Zhang 135*b77a9fdfSHawking Zhang 136*b77a9fdfSHawking Zhang // addressBlock: uvd0_jpegnpdec 137*b77a9fdfSHawking Zhang //UVD_JPEG_CNTL 138*b77a9fdfSHawking Zhang #define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 139*b77a9fdfSHawking Zhang #define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 140*b77a9fdfSHawking Zhang #define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3 141*b77a9fdfSHawking Zhang #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4 142*b77a9fdfSHawking Zhang #define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L 143*b77a9fdfSHawking Zhang #define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L 144*b77a9fdfSHawking Zhang #define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L 145*b77a9fdfSHawking Zhang #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L 146*b77a9fdfSHawking Zhang //UVD_JPEG_RB_BASE 147*b77a9fdfSHawking Zhang #define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 148*b77a9fdfSHawking Zhang #define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 149*b77a9fdfSHawking Zhang #define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL 150*b77a9fdfSHawking Zhang #define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L 151*b77a9fdfSHawking Zhang //UVD_JPEG_RB_WPTR 152*b77a9fdfSHawking Zhang #define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 153*b77a9fdfSHawking Zhang #define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L 154*b77a9fdfSHawking Zhang //UVD_JPEG_RB_RPTR 155*b77a9fdfSHawking Zhang #define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 156*b77a9fdfSHawking Zhang #define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L 157*b77a9fdfSHawking Zhang //UVD_JPEG_RB_SIZE 158*b77a9fdfSHawking Zhang #define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 159*b77a9fdfSHawking Zhang #define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L 160*b77a9fdfSHawking Zhang //UVD_JPEG_DEC_CNT 161*b77a9fdfSHawking Zhang #define UVD_JPEG_DEC_CNT__DECODE_COUNT__SHIFT 0x0 162*b77a9fdfSHawking Zhang #define UVD_JPEG_DEC_CNT__DECODE_COUNT_MASK 0xFFFFFFFFL 163*b77a9fdfSHawking Zhang //UVD_JPEG_SPS_INFO 164*b77a9fdfSHawking Zhang #define UVD_JPEG_SPS_INFO__PIC_WIDTH__SHIFT 0x0 165*b77a9fdfSHawking Zhang #define UVD_JPEG_SPS_INFO__PIC_HEIGHT__SHIFT 0x10 166*b77a9fdfSHawking Zhang #define UVD_JPEG_SPS_INFO__PIC_WIDTH_MASK 0x0000FFFFL 167*b77a9fdfSHawking Zhang #define UVD_JPEG_SPS_INFO__PIC_HEIGHT_MASK 0xFFFF0000L 168*b77a9fdfSHawking Zhang //UVD_JPEG_SPS1_INFO 169*b77a9fdfSHawking Zhang #define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC__SHIFT 0x0 170*b77a9fdfSHawking Zhang #define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT__SHIFT 0x3 171*b77a9fdfSHawking Zhang #define UVD_JPEG_SPS1_INFO__OUT_FMT_422__SHIFT 0x4 172*b77a9fdfSHawking Zhang #define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC_MASK 0x00000007L 173*b77a9fdfSHawking Zhang #define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT_MASK 0x00000008L 174*b77a9fdfSHawking Zhang #define UVD_JPEG_SPS1_INFO__OUT_FMT_422_MASK 0x00000010L 175*b77a9fdfSHawking Zhang //UVD_JPEG_RE_TIMER 176*b77a9fdfSHawking Zhang #define UVD_JPEG_RE_TIMER__TIMER_OUT__SHIFT 0x0 177*b77a9fdfSHawking Zhang #define UVD_JPEG_RE_TIMER__TIMER_OUT_EN__SHIFT 0x10 178*b77a9fdfSHawking Zhang #define UVD_JPEG_RE_TIMER__TIMER_OUT_MASK 0x000000FFL 179*b77a9fdfSHawking Zhang #define UVD_JPEG_RE_TIMER__TIMER_OUT_EN_MASK 0x00010000L 180*b77a9fdfSHawking Zhang //UVD_JPEG_DEC_SCRATCH0 181*b77a9fdfSHawking Zhang #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0 182*b77a9fdfSHawking Zhang #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 183*b77a9fdfSHawking Zhang //UVD_JPEG_INT_EN 184*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0 185*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1 186*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2 187*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6 188*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7 189*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8 190*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9 191*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa 192*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb 193*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc 194*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd 195*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe 196*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf 197*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L 198*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L 199*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L 200*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L 201*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L 202*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L 203*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L 204*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L 205*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L 206*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L 207*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L 208*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L 209*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L 210*b77a9fdfSHawking Zhang //UVD_JPEG_INT_STAT 211*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0 212*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1 213*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2 214*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6 215*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7 216*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8 217*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9 218*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa 219*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb 220*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc 221*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd 222*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe 223*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf 224*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L 225*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L 226*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L 227*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L 228*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L 229*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L 230*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L 231*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L 232*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L 233*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L 234*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L 235*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L 236*b77a9fdfSHawking Zhang #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L 237*b77a9fdfSHawking Zhang //UVD_JPEG_TIER_CNTL0 238*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__TIER_SEL__SHIFT 0x0 239*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__Y_COMP_ID__SHIFT 0x2 240*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__U_COMP_ID__SHIFT 0x4 241*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__V_COMP_ID__SHIFT 0x6 242*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC__SHIFT 0x8 243*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC__SHIFT 0xb 244*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC__SHIFT 0xe 245*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC__SHIFT 0x11 246*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC__SHIFT 0x14 247*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC__SHIFT 0x17 248*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__Y_TQ__SHIFT 0x1a 249*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__U_TQ__SHIFT 0x1c 250*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__V_TQ__SHIFT 0x1e 251*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__TIER_SEL_MASK 0x00000003L 252*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__Y_COMP_ID_MASK 0x0000000CL 253*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__U_COMP_ID_MASK 0x00000030L 254*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__V_COMP_ID_MASK 0x000000C0L 255*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC_MASK 0x00000700L 256*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC_MASK 0x00003800L 257*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC_MASK 0x0001C000L 258*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC_MASK 0x000E0000L 259*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC_MASK 0x00700000L 260*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC_MASK 0x03800000L 261*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__Y_TQ_MASK 0x0C000000L 262*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__U_TQ_MASK 0x30000000L 263*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL0__V_TQ_MASK 0xC0000000L 264*b77a9fdfSHawking Zhang //UVD_JPEG_TIER_CNTL1 265*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL1__SRC_WIDTH__SHIFT 0x0 266*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT__SHIFT 0x10 267*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL1__SRC_WIDTH_MASK 0x0000FFFFL 268*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT_MASK 0xFFFF0000L 269*b77a9fdfSHawking Zhang //UVD_JPEG_TIER_CNTL2 270*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL__SHIFT 0x0 271*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TBL_TYPE__SHIFT 0x1 272*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TQ__SHIFT 0x2 273*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TH__SHIFT 0x4 274*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TC__SHIFT 0x6 275*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TD__SHIFT 0x7 276*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TA__SHIFT 0xa 277*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN__SHIFT 0xe 278*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__DRI_VAL__SHIFT 0x10 279*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL_MASK 0x00000001L 280*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TBL_TYPE_MASK 0x00000002L 281*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TQ_MASK 0x0000000CL 282*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TH_MASK 0x00000030L 283*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TC_MASK 0x00000040L 284*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TD_MASK 0x00000380L 285*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TA_MASK 0x00001C00L 286*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN_MASK 0x00004000L 287*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_CNTL2__DRI_VAL_MASK 0xFFFF0000L 288*b77a9fdfSHawking Zhang //UVD_JPEG_TIER_STATUS 289*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE__SHIFT 0x0 290*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_STATUS__DECODE_DONE__SHIFT 0x1 291*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE_MASK 0x00000001L 292*b77a9fdfSHawking Zhang #define UVD_JPEG_TIER_STATUS__DECODE_DONE_MASK 0x00000002L 293*b77a9fdfSHawking Zhang //UVD_JPEG_OUTBUF_CNTL 294*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT__SHIFT 0x0 295*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN__SHIFT 0x2 296*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX__SHIFT 0x6 297*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT__SHIFT 0x7 298*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER__SHIFT 0x9 299*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT_MASK 0x00000003L 300*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN_MASK 0x00000004L 301*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX_MASK 0x00000040L 302*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT_MASK 0x00000180L 303*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER_MASK 0x00001E00L 304*b77a9fdfSHawking Zhang //UVD_JPEG_OUTBUF_WPTR 305*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR__SHIFT 0x0 306*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR_MASK 0xFFFFFFFFL 307*b77a9fdfSHawking Zhang //UVD_JPEG_OUTBUF_RPTR 308*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR__SHIFT 0x0 309*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR_MASK 0xFFFFFFFFL 310*b77a9fdfSHawking Zhang //UVD_JPEG_PITCH 311*b77a9fdfSHawking Zhang #define UVD_JPEG_PITCH__PITCH__SHIFT 0x0 312*b77a9fdfSHawking Zhang #define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL 313*b77a9fdfSHawking Zhang //UVD_JPEG_UV_PITCH 314*b77a9fdfSHawking Zhang #define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0 315*b77a9fdfSHawking Zhang #define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL 316*b77a9fdfSHawking Zhang //JPEG_DEC_Y_GFX8_TILING_SURFACE 317*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 318*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 319*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 320*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 321*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 322*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 323*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 324*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 325*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 326*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 327*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 328*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 329*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 330*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 331*b77a9fdfSHawking Zhang //JPEG_DEC_UV_GFX8_TILING_SURFACE 332*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 333*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 334*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 335*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 336*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 337*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 338*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 339*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 340*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 341*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 342*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 343*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 344*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 345*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 346*b77a9fdfSHawking Zhang //JPEG_DEC_GFX8_ADDR_CONFIG 347*b77a9fdfSHawking Zhang #define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 348*b77a9fdfSHawking Zhang #define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 349*b77a9fdfSHawking Zhang //JPEG_DEC_Y_GFX10_TILING_SURFACE 350*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 351*b77a9fdfSHawking Zhang #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 352*b77a9fdfSHawking Zhang //JPEG_DEC_UV_GFX10_TILING_SURFACE 353*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 354*b77a9fdfSHawking Zhang #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 355*b77a9fdfSHawking Zhang //JPEG_DEC_GFX10_ADDR_CONFIG 356*b77a9fdfSHawking Zhang #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 357*b77a9fdfSHawking Zhang #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 358*b77a9fdfSHawking Zhang #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 359*b77a9fdfSHawking Zhang #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 360*b77a9fdfSHawking Zhang #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 361*b77a9fdfSHawking Zhang #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 362*b77a9fdfSHawking Zhang #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 363*b77a9fdfSHawking Zhang #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 364*b77a9fdfSHawking Zhang //JPEG_DEC_ADDR_MODE 365*b77a9fdfSHawking Zhang #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 366*b77a9fdfSHawking Zhang #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 367*b77a9fdfSHawking Zhang #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 368*b77a9fdfSHawking Zhang #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 369*b77a9fdfSHawking Zhang #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 370*b77a9fdfSHawking Zhang #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 371*b77a9fdfSHawking Zhang //UVD_JPEG_OUTPUT_XY 372*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTPUT_XY__OUTPUT_X__SHIFT 0x0 373*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTPUT_XY__OUTPUT_Y__SHIFT 0x10 374*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTPUT_XY__OUTPUT_X_MASK 0x00003FFFL 375*b77a9fdfSHawking Zhang #define UVD_JPEG_OUTPUT_XY__OUTPUT_Y_MASK 0x3FFF0000L 376*b77a9fdfSHawking Zhang //UVD_JPEG_GPCOM_CMD 377*b77a9fdfSHawking Zhang #define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 378*b77a9fdfSHawking Zhang #define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL 379*b77a9fdfSHawking Zhang //UVD_JPEG_GPCOM_DATA0 380*b77a9fdfSHawking Zhang #define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 381*b77a9fdfSHawking Zhang #define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 382*b77a9fdfSHawking Zhang //UVD_JPEG_GPCOM_DATA1 383*b77a9fdfSHawking Zhang #define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 384*b77a9fdfSHawking Zhang #define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 385*b77a9fdfSHawking Zhang //UVD_JPEG_INDEX 386*b77a9fdfSHawking Zhang #define UVD_JPEG_INDEX__INDEX__SHIFT 0x0 387*b77a9fdfSHawking Zhang #define UVD_JPEG_INDEX__INDEX_MASK 0x000001FFL 388*b77a9fdfSHawking Zhang //UVD_JPEG_DATA 389*b77a9fdfSHawking Zhang #define UVD_JPEG_DATA__DATA__SHIFT 0x0 390*b77a9fdfSHawking Zhang #define UVD_JPEG_DATA__DATA_MASK 0xFFFFFFFFL 391*b77a9fdfSHawking Zhang //UVD_JPEG_SCRATCH1 392*b77a9fdfSHawking Zhang #define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0 393*b77a9fdfSHawking Zhang #define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 394*b77a9fdfSHawking Zhang //UVD_JPEG_DEC_SOFT_RST 395*b77a9fdfSHawking Zhang #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0 396*b77a9fdfSHawking Zhang #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10 397*b77a9fdfSHawking Zhang #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L 398*b77a9fdfSHawking Zhang #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 399*b77a9fdfSHawking Zhang 400*b77a9fdfSHawking Zhang 401*b77a9fdfSHawking Zhang // addressBlock: uvd0_lmi_adpdec 402*b77a9fdfSHawking Zhang //UVD_LMI_RE_64BIT_BAR_LOW 403*b77a9fdfSHawking Zhang #define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 404*b77a9fdfSHawking Zhang #define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 405*b77a9fdfSHawking Zhang //UVD_LMI_RE_64BIT_BAR_HIGH 406*b77a9fdfSHawking Zhang #define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 407*b77a9fdfSHawking Zhang #define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 408*b77a9fdfSHawking Zhang //UVD_LMI_IT_64BIT_BAR_LOW 409*b77a9fdfSHawking Zhang #define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 410*b77a9fdfSHawking Zhang #define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 411*b77a9fdfSHawking Zhang //UVD_LMI_IT_64BIT_BAR_HIGH 412*b77a9fdfSHawking Zhang #define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 413*b77a9fdfSHawking Zhang #define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 414*b77a9fdfSHawking Zhang //UVD_LMI_MP_64BIT_BAR_LOW 415*b77a9fdfSHawking Zhang #define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 416*b77a9fdfSHawking Zhang #define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 417*b77a9fdfSHawking Zhang //UVD_LMI_MP_64BIT_BAR_HIGH 418*b77a9fdfSHawking Zhang #define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 419*b77a9fdfSHawking Zhang #define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 420*b77a9fdfSHawking Zhang //UVD_LMI_CM_64BIT_BAR_LOW 421*b77a9fdfSHawking Zhang #define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 422*b77a9fdfSHawking Zhang #define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 423*b77a9fdfSHawking Zhang //UVD_LMI_CM_64BIT_BAR_HIGH 424*b77a9fdfSHawking Zhang #define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 425*b77a9fdfSHawking Zhang #define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 426*b77a9fdfSHawking Zhang //UVD_LMI_DB_64BIT_BAR_LOW 427*b77a9fdfSHawking Zhang #define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 428*b77a9fdfSHawking Zhang #define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 429*b77a9fdfSHawking Zhang //UVD_LMI_DB_64BIT_BAR_HIGH 430*b77a9fdfSHawking Zhang #define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 431*b77a9fdfSHawking Zhang #define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 432*b77a9fdfSHawking Zhang //UVD_LMI_DBW_64BIT_BAR_LOW 433*b77a9fdfSHawking Zhang #define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 434*b77a9fdfSHawking Zhang #define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 435*b77a9fdfSHawking Zhang //UVD_LMI_DBW_64BIT_BAR_HIGH 436*b77a9fdfSHawking Zhang #define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 437*b77a9fdfSHawking Zhang #define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 438*b77a9fdfSHawking Zhang //UVD_LMI_IDCT_64BIT_BAR_LOW 439*b77a9fdfSHawking Zhang #define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 440*b77a9fdfSHawking Zhang #define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 441*b77a9fdfSHawking Zhang //UVD_LMI_IDCT_64BIT_BAR_HIGH 442*b77a9fdfSHawking Zhang #define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 443*b77a9fdfSHawking Zhang #define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 444*b77a9fdfSHawking Zhang //UVD_LMI_MPRD_S0_64BIT_BAR_LOW 445*b77a9fdfSHawking Zhang #define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 446*b77a9fdfSHawking Zhang #define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 447*b77a9fdfSHawking Zhang //UVD_LMI_MPRD_S0_64BIT_BAR_HIGH 448*b77a9fdfSHawking Zhang #define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 449*b77a9fdfSHawking Zhang #define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 450*b77a9fdfSHawking Zhang //UVD_LMI_MPRD_S1_64BIT_BAR_LOW 451*b77a9fdfSHawking Zhang #define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 452*b77a9fdfSHawking Zhang #define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 453*b77a9fdfSHawking Zhang //UVD_LMI_MPRD_S1_64BIT_BAR_HIGH 454*b77a9fdfSHawking Zhang #define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 455*b77a9fdfSHawking Zhang #define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 456*b77a9fdfSHawking Zhang //UVD_LMI_MPRD_DBW_64BIT_BAR_LOW 457*b77a9fdfSHawking Zhang #define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 458*b77a9fdfSHawking Zhang #define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 459*b77a9fdfSHawking Zhang //UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 460*b77a9fdfSHawking Zhang #define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 461*b77a9fdfSHawking Zhang #define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 462*b77a9fdfSHawking Zhang //UVD_LMI_MPC_64BIT_BAR_LOW 463*b77a9fdfSHawking Zhang #define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 464*b77a9fdfSHawking Zhang #define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 465*b77a9fdfSHawking Zhang //UVD_LMI_MPC_64BIT_BAR_HIGH 466*b77a9fdfSHawking Zhang #define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 467*b77a9fdfSHawking Zhang #define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 468*b77a9fdfSHawking Zhang //UVD_LMI_RBC_RB_64BIT_BAR_LOW 469*b77a9fdfSHawking Zhang #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 470*b77a9fdfSHawking Zhang #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 471*b77a9fdfSHawking Zhang //UVD_LMI_RBC_RB_64BIT_BAR_HIGH 472*b77a9fdfSHawking Zhang #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 473*b77a9fdfSHawking Zhang #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 474*b77a9fdfSHawking Zhang //UVD_LMI_RBC_IB_64BIT_BAR_LOW 475*b77a9fdfSHawking Zhang #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 476*b77a9fdfSHawking Zhang #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 477*b77a9fdfSHawking Zhang //UVD_LMI_RBC_IB_64BIT_BAR_HIGH 478*b77a9fdfSHawking Zhang #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 479*b77a9fdfSHawking Zhang #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 480*b77a9fdfSHawking Zhang //UVD_LMI_LBSI_64BIT_BAR_LOW 481*b77a9fdfSHawking Zhang #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 482*b77a9fdfSHawking Zhang #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 483*b77a9fdfSHawking Zhang //UVD_LMI_LBSI_64BIT_BAR_HIGH 484*b77a9fdfSHawking Zhang #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 485*b77a9fdfSHawking Zhang #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 486*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_NC0_64BIT_BAR_LOW 487*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 488*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 489*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 490*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 491*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 492*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_NC1_64BIT_BAR_LOW 493*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 494*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 495*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 496*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 497*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 498*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 499*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 500*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 501*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 502*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 503*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 504*b77a9fdfSHawking Zhang //UVD_LMI_CENC_64BIT_BAR_LOW 505*b77a9fdfSHawking Zhang #define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 506*b77a9fdfSHawking Zhang #define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 507*b77a9fdfSHawking Zhang //UVD_LMI_CENC_64BIT_BAR_HIGH 508*b77a9fdfSHawking Zhang #define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 509*b77a9fdfSHawking Zhang #define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 510*b77a9fdfSHawking Zhang //UVD_LMI_SRE_64BIT_BAR_LOW 511*b77a9fdfSHawking Zhang #define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 512*b77a9fdfSHawking Zhang #define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 513*b77a9fdfSHawking Zhang //UVD_LMI_SRE_64BIT_BAR_HIGH 514*b77a9fdfSHawking Zhang #define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 515*b77a9fdfSHawking Zhang #define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 516*b77a9fdfSHawking Zhang //UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 517*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 518*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 519*b77a9fdfSHawking Zhang //UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 520*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 521*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 522*b77a9fdfSHawking Zhang //UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 523*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 524*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 525*b77a9fdfSHawking Zhang //UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 526*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 527*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 528*b77a9fdfSHawking Zhang //UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 529*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 530*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 531*b77a9fdfSHawking Zhang //UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 532*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 533*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 534*b77a9fdfSHawking Zhang //UVD_LMI_MIF_REF_64BIT_BAR_LOW 535*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 536*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 537*b77a9fdfSHawking Zhang //UVD_LMI_MIF_REF_64BIT_BAR_HIGH 538*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 539*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 540*b77a9fdfSHawking Zhang //UVD_LMI_MIF_DBW_64BIT_BAR_LOW 541*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 542*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 543*b77a9fdfSHawking Zhang //UVD_LMI_MIF_DBW_64BIT_BAR_HIGH 544*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 545*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 546*b77a9fdfSHawking Zhang //UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 547*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 548*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 549*b77a9fdfSHawking Zhang //UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 550*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 551*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 552*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSP0_64BIT_BAR_LOW 553*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 554*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 555*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 556*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 557*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 558*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSP1_64BIT_BAR_LOW 559*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 560*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 561*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 562*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 563*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 564*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSP2_64BIT_BAR_LOW 565*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 566*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 567*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 568*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 569*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 570*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSP3_64BIT_BAR_LOW 571*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 572*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 573*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 574*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 575*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 576*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSD0_64BIT_BAR_LOW 577*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 578*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 579*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 580*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 581*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 582*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSD1_64BIT_BAR_LOW 583*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 584*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 585*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 586*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 587*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 588*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSD2_64BIT_BAR_LOW 589*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 590*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 591*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 592*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 593*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 594*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSD3_64BIT_BAR_LOW 595*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 596*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 597*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 598*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 599*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 600*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSD4_64BIT_BAR_LOW 601*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 602*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 603*b77a9fdfSHawking Zhang //UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 604*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 605*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 606*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 607*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 608*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 609*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 610*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 611*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 612*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 613*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 614*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 615*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 616*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 617*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 618*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 619*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 620*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 621*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 622*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 623*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 624*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 625*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 626*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 627*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 628*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 629*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 630*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 631*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 632*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 633*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 634*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 635*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 636*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 637*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 638*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 639*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 640*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 641*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 642*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 643*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 644*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 645*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 646*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 647*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 648*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 649*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 650*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 651*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 652*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 653*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 654*b77a9fdfSHawking Zhang //UVD_LMI_MIF_SCLR_64BIT_BAR_LOW 655*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 656*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 657*b77a9fdfSHawking Zhang //UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 658*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 659*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 660*b77a9fdfSHawking Zhang //UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 661*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 662*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 663*b77a9fdfSHawking Zhang //UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 664*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 665*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 666*b77a9fdfSHawking Zhang //UVD_LMI_SPH_64BIT_BAR_HIGH 667*b77a9fdfSHawking Zhang #define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 668*b77a9fdfSHawking Zhang #define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 669*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 670*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 671*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 672*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 673*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 674*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 675*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 676*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 677*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 678*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 679*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 680*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 681*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 682*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 683*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 684*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 685*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 686*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 687*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 688*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 689*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 690*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 691*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 692*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 693*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 694*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 695*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 696*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 697*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 698*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 699*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 700*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 701*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 702*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 703*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 704*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 705*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 706*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 707*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 708*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 709*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 710*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 711*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 712*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 713*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 714*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 715*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 716*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 717*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_NC_VMID 718*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0 719*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4 720*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8 721*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc 722*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10 723*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14 724*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18 725*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c 726*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL 727*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L 728*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L 729*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L 730*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L 731*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L 732*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L 733*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L 734*b77a9fdfSHawking Zhang //UVD_LMI_MMSCH_CTRL 735*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0 736*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1 737*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH__SHIFT 0x2 738*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3 739*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5 740*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7 741*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9 742*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb 743*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc 744*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L 745*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L 746*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH_MASK 0x00000004L 747*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L 748*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L 749*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L 750*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L 751*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L 752*b77a9fdfSHawking Zhang #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L 753*b77a9fdfSHawking Zhang //UVD_MMSCH_LMI_STATUS 754*b77a9fdfSHawking Zhang #define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN__SHIFT 0x2 755*b77a9fdfSHawking Zhang #define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN__SHIFT 0xd 756*b77a9fdfSHawking Zhang #define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN__SHIFT 0xe 757*b77a9fdfSHawking Zhang #define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN_MASK 0x00000004L 758*b77a9fdfSHawking Zhang #define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN_MASK 0x00002000L 759*b77a9fdfSHawking Zhang #define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN_MASK 0x00004000L 760*b77a9fdfSHawking Zhang //UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 761*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 762*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 763*b77a9fdfSHawking Zhang //UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 764*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 765*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 766*b77a9fdfSHawking Zhang //UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 767*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 768*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 769*b77a9fdfSHawking Zhang //UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 770*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 771*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 772*b77a9fdfSHawking Zhang //UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 773*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 774*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 775*b77a9fdfSHawking Zhang //UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 776*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 777*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 778*b77a9fdfSHawking Zhang //UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 779*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 780*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 781*b77a9fdfSHawking Zhang //UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 782*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 783*b77a9fdfSHawking Zhang #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 784*b77a9fdfSHawking Zhang //UVD_ADP_ATOMIC_CONFIG 785*b77a9fdfSHawking Zhang #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE__SHIFT 0x0 786*b77a9fdfSHawking Zhang #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE__SHIFT 0x4 787*b77a9fdfSHawking Zhang #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE__SHIFT 0x8 788*b77a9fdfSHawking Zhang #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE__SHIFT 0xc 789*b77a9fdfSHawking Zhang #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG__SHIFT 0x10 790*b77a9fdfSHawking Zhang #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE_MASK 0x0000000FL 791*b77a9fdfSHawking Zhang #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE_MASK 0x000000F0L 792*b77a9fdfSHawking Zhang #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE_MASK 0x00000F00L 793*b77a9fdfSHawking Zhang #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE_MASK 0x0000F000L 794*b77a9fdfSHawking Zhang #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG_MASK 0x000F0000L 795*b77a9fdfSHawking Zhang //UVD_LMI_ARB_CTRL2 796*b77a9fdfSHawking Zhang #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0 797*b77a9fdfSHawking Zhang #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1 798*b77a9fdfSHawking Zhang #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2 799*b77a9fdfSHawking Zhang #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6 800*b77a9fdfSHawking Zhang #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa 801*b77a9fdfSHawking Zhang #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14 802*b77a9fdfSHawking Zhang #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L 803*b77a9fdfSHawking Zhang #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L 804*b77a9fdfSHawking Zhang #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL 805*b77a9fdfSHawking Zhang #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L 806*b77a9fdfSHawking Zhang #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L 807*b77a9fdfSHawking Zhang #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L 808*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE_VMIDS_MULTI 809*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0 810*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4 811*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8 812*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc 813*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10 814*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14 815*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18 816*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c 817*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL 818*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L 819*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L 820*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L 821*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L 822*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L 823*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L 824*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L 825*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_NC_VMIDS_MULTI 826*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4 827*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8 828*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc 829*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10 830*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14 831*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18 832*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L 833*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L 834*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L 835*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L 836*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L 837*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L 838*b77a9fdfSHawking Zhang //UVD_LMI_LAT_CTRL 839*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0 840*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8 841*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9 842*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa 843*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 844*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10 845*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL 846*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L 847*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L 848*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L 849*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 850*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L 851*b77a9fdfSHawking Zhang //UVD_LMI_LAT_CNTR 852*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 853*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 854*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 855*b77a9fdfSHawking Zhang #define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 856*b77a9fdfSHawking Zhang //UVD_LMI_AVG_LAT_CNTR 857*b77a9fdfSHawking Zhang #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 858*b77a9fdfSHawking Zhang #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 859*b77a9fdfSHawking Zhang #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 860*b77a9fdfSHawking Zhang #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 861*b77a9fdfSHawking Zhang #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 862*b77a9fdfSHawking Zhang #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 863*b77a9fdfSHawking Zhang //UVD_LMI_SPH 864*b77a9fdfSHawking Zhang #define UVD_LMI_SPH__ADDR__SHIFT 0x0 865*b77a9fdfSHawking Zhang #define UVD_LMI_SPH__STS__SHIFT 0x1c 866*b77a9fdfSHawking Zhang #define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e 867*b77a9fdfSHawking Zhang #define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f 868*b77a9fdfSHawking Zhang #define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL 869*b77a9fdfSHawking Zhang #define UVD_LMI_SPH__STS_MASK 0x30000000L 870*b77a9fdfSHawking Zhang #define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L 871*b77a9fdfSHawking Zhang #define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L 872*b77a9fdfSHawking Zhang //UVD_LMI_VCPU_CACHE_VMID 873*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 874*b77a9fdfSHawking Zhang #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 875*b77a9fdfSHawking Zhang //UVD_LMI_CTRL2 876*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 877*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 878*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 879*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 880*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4 881*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 882*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 883*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 884*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 885*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 886*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 887*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 888*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 889*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 890*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19 891*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a 892*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b 893*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L 894*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 895*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 896*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L 897*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L 898*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L 899*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 900*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L 901*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L 902*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L 903*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L 904*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L 905*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L 906*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L 907*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L 908*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L 909*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L 910*b77a9fdfSHawking Zhang //UVD_LMI_URGENT_CTRL 911*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 912*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1 913*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2 914*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8 915*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9 916*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa 917*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10 918*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11 919*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12 920*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18 921*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19 922*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a 923*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 924*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L 925*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL 926*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L 927*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L 928*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L 929*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L 930*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L 931*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L 932*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L 933*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L 934*b77a9fdfSHawking Zhang #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L 935*b77a9fdfSHawking Zhang //UVD_LMI_CTRL 936*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 937*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 938*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 939*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 940*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 941*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 942*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 943*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 944*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 945*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 946*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 947*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 948*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 949*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 950*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 951*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b 952*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__MC_BLK_RST__SHIFT 0x1c 953*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__UMC_BLK_RST__SHIFT 0x1d 954*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__RFU__SHIFT 0x1e 955*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL 956*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L 957*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L 958*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L 959*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L 960*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L 961*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L 962*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L 963*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L 964*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 965*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L 966*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L 967*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L 968*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L 969*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L 970*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L 971*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__MC_BLK_RST_MASK 0x10000000L 972*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__UMC_BLK_RST_MASK 0x20000000L 973*b77a9fdfSHawking Zhang #define UVD_LMI_CTRL__RFU_MASK 0xC0000000L 974*b77a9fdfSHawking Zhang //UVD_LMI_STATUS 975*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 976*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 977*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 978*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 979*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 980*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 981*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 982*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 983*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 984*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 985*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 986*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 987*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 988*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 989*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12 990*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13 991*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14 992*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15 993*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16 994*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L 995*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L 996*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L 997*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L 998*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L 999*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L 1000*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L 1001*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L 1002*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L 1003*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L 1004*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L 1005*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L 1006*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L 1007*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L 1008*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L 1009*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L 1010*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L 1011*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L 1012*b77a9fdfSHawking Zhang #define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L 1013*b77a9fdfSHawking Zhang //UVD_LMI_PERFMON_CTRL 1014*b77a9fdfSHawking Zhang #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 1015*b77a9fdfSHawking Zhang #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 1016*b77a9fdfSHawking Zhang #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 1017*b77a9fdfSHawking Zhang #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L 1018*b77a9fdfSHawking Zhang //UVD_LMI_PERFMON_COUNT_LO 1019*b77a9fdfSHawking Zhang #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 1020*b77a9fdfSHawking Zhang #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 1021*b77a9fdfSHawking Zhang //UVD_LMI_PERFMON_COUNT_HI 1022*b77a9fdfSHawking Zhang #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 1023*b77a9fdfSHawking Zhang #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 1024*b77a9fdfSHawking Zhang //UVD_LMI_ADP_SWAP_CNTL 1025*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 1026*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 1027*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 1028*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 1029*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 1030*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 1031*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 1032*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__ACAP_MC_SWAP__SHIFT 0x14 1033*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 1034*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 1035*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 1036*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L 1037*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L 1038*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L 1039*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L 1040*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L 1041*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L 1042*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L 1043*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__ACAP_MC_SWAP_MASK 0x00300000L 1044*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L 1045*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L 1046*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L 1047*b77a9fdfSHawking Zhang //UVD_LMI_RBC_RB_VMID 1048*b77a9fdfSHawking Zhang #define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 1049*b77a9fdfSHawking Zhang #define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL 1050*b77a9fdfSHawking Zhang //UVD_LMI_RBC_IB_VMID 1051*b77a9fdfSHawking Zhang #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 1052*b77a9fdfSHawking Zhang #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL 1053*b77a9fdfSHawking Zhang //UVD_LMI_MC_CREDITS 1054*b77a9fdfSHawking Zhang #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0 1055*b77a9fdfSHawking Zhang #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8 1056*b77a9fdfSHawking Zhang #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10 1057*b77a9fdfSHawking Zhang #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18 1058*b77a9fdfSHawking Zhang #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL 1059*b77a9fdfSHawking Zhang #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L 1060*b77a9fdfSHawking Zhang #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L 1061*b77a9fdfSHawking Zhang #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L 1062*b77a9fdfSHawking Zhang //UVD_LMI_ADP_IND_INDEX 1063*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_IND_INDEX__INDEX__SHIFT 0x0 1064*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_IND_INDEX__INDEX_MASK 0x00001FFFL 1065*b77a9fdfSHawking Zhang //UVD_LMI_ADP_IND_DATA 1066*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_IND_DATA__DATA__SHIFT 0x0 1067*b77a9fdfSHawking Zhang #define UVD_LMI_ADP_IND_DATA__DATA_MASK 0xFFFFFFFFL 1068*b77a9fdfSHawking Zhang //VCN_RAS_CNTL 1069*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN__SHIFT 0x0 1070*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__MMSCH_FATAL_ERROR_EN__SHIFT 0x1 1071*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN__SHIFT 0x4 1072*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__MMSCH_PMI_EN__SHIFT 0x5 1073*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__VCPU_VCODEC_REARM__SHIFT 0x8 1074*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__MMSCH_REARM__SHIFT 0x9 1075*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN__SHIFT 0xc 1076*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__VCPU_VCODEC_READY__SHIFT 0x10 1077*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__MMSCH_READY__SHIFT 0x11 1078*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK 0x00000001L 1079*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__MMSCH_FATAL_ERROR_EN_MASK 0x00000002L 1080*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK 0x00000010L 1081*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__MMSCH_PMI_EN_MASK 0x00000020L 1082*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK 0x00000100L 1083*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__MMSCH_REARM_MASK 0x00000200L 1084*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK 0x00001000L 1085*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__VCPU_VCODEC_READY_MASK 0x00010000L 1086*b77a9fdfSHawking Zhang #define VCN_RAS_CNTL__MMSCH_READY_MASK 0x00020000L 1087*b77a9fdfSHawking Zhang 1088*b77a9fdfSHawking Zhang 1089*b77a9fdfSHawking Zhang // addressBlock: uvd0_mmsch_dec 1090*b77a9fdfSHawking Zhang //MMSCH_UCODE_ADDR 1091*b77a9fdfSHawking Zhang #define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT 0x2 1092*b77a9fdfSHawking Zhang #define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT 0x1f 1093*b77a9fdfSHawking Zhang #define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFCL 1094*b77a9fdfSHawking Zhang #define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK 0x80000000L 1095*b77a9fdfSHawking Zhang //MMSCH_UCODE_DATA 1096*b77a9fdfSHawking Zhang #define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT 0x0 1097*b77a9fdfSHawking Zhang #define MMSCH_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 1098*b77a9fdfSHawking Zhang //MMSCH_SRAM_ADDR 1099*b77a9fdfSHawking Zhang #define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT 0x2 1100*b77a9fdfSHawking Zhang #define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT 0x1f 1101*b77a9fdfSHawking Zhang #define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK 0x00001FFCL 1102*b77a9fdfSHawking Zhang #define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK 0x80000000L 1103*b77a9fdfSHawking Zhang //MMSCH_SRAM_DATA 1104*b77a9fdfSHawking Zhang #define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT 0x0 1105*b77a9fdfSHawking Zhang #define MMSCH_SRAM_DATA__SRAM_DATA_MASK 0xFFFFFFFFL 1106*b77a9fdfSHawking Zhang //MMSCH_VF_SRAM_OFFSET 1107*b77a9fdfSHawking Zhang #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT 0x2 1108*b77a9fdfSHawking Zhang #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT 0x10 1109*b77a9fdfSHawking Zhang #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK 0x00001FFCL 1110*b77a9fdfSHawking Zhang #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK 0x00FF0000L 1111*b77a9fdfSHawking Zhang //MMSCH_DB_SRAM_OFFSET 1112*b77a9fdfSHawking Zhang #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT 0x2 1113*b77a9fdfSHawking Zhang #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT 0x10 1114*b77a9fdfSHawking Zhang #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT 0x18 1115*b77a9fdfSHawking Zhang #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK 0x00001FFCL 1116*b77a9fdfSHawking Zhang #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK 0x00FF0000L 1117*b77a9fdfSHawking Zhang #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK 0xFF000000L 1118*b77a9fdfSHawking Zhang //MMSCH_CTX_SRAM_OFFSET 1119*b77a9fdfSHawking Zhang #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT 0x2 1120*b77a9fdfSHawking Zhang #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT 0x10 1121*b77a9fdfSHawking Zhang #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK 0x00001FFCL 1122*b77a9fdfSHawking Zhang #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK 0xFFFF0000L 1123*b77a9fdfSHawking Zhang //MMSCH_INTR 1124*b77a9fdfSHawking Zhang #define MMSCH_INTR__INTR__SHIFT 0x0 1125*b77a9fdfSHawking Zhang #define MMSCH_INTR__INTR_MASK 0x00001FFFL 1126*b77a9fdfSHawking Zhang //MMSCH_INTR_ACK 1127*b77a9fdfSHawking Zhang #define MMSCH_INTR_ACK__INTR__SHIFT 0x0 1128*b77a9fdfSHawking Zhang #define MMSCH_INTR_ACK__INTR_MASK 0x00001FFFL 1129*b77a9fdfSHawking Zhang //MMSCH_INTR_STATUS 1130*b77a9fdfSHawking Zhang #define MMSCH_INTR_STATUS__INTR__SHIFT 0x0 1131*b77a9fdfSHawking Zhang #define MMSCH_INTR_STATUS__INTR_MASK 0x00001FFFL 1132*b77a9fdfSHawking Zhang //MMSCH_VF_VMID 1133*b77a9fdfSHawking Zhang #define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0 1134*b77a9fdfSHawking Zhang #define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5 1135*b77a9fdfSHawking Zhang #define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL 1136*b77a9fdfSHawking Zhang #define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L 1137*b77a9fdfSHawking Zhang //MMSCH_VF_CTX_ADDR_LO 1138*b77a9fdfSHawking Zhang #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6 1139*b77a9fdfSHawking Zhang #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L 1140*b77a9fdfSHawking Zhang //MMSCH_VF_CTX_ADDR_HI 1141*b77a9fdfSHawking Zhang #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0 1142*b77a9fdfSHawking Zhang #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL 1143*b77a9fdfSHawking Zhang //MMSCH_VF_CTX_SIZE 1144*b77a9fdfSHawking Zhang #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0 1145*b77a9fdfSHawking Zhang #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL 1146*b77a9fdfSHawking Zhang //MMSCH_VF_GPCOM_ADDR_LO 1147*b77a9fdfSHawking Zhang #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6 1148*b77a9fdfSHawking Zhang #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L 1149*b77a9fdfSHawking Zhang //MMSCH_VF_GPCOM_ADDR_HI 1150*b77a9fdfSHawking Zhang #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0 1151*b77a9fdfSHawking Zhang #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL 1152*b77a9fdfSHawking Zhang //MMSCH_VF_GPCOM_SIZE 1153*b77a9fdfSHawking Zhang #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0 1154*b77a9fdfSHawking Zhang #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL 1155*b77a9fdfSHawking Zhang //MMSCH_VF_MAILBOX_HOST 1156*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0 1157*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL 1158*b77a9fdfSHawking Zhang //MMSCH_VF_MAILBOX_RESP 1159*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0 1160*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 1161*b77a9fdfSHawking Zhang //MMSCH_VF_MAILBOX_0 1162*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX_0__DATA__SHIFT 0x0 1163*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX_0__DATA_MASK 0xFFFFFFFFL 1164*b77a9fdfSHawking Zhang //MMSCH_VF_MAILBOX_0_RESP 1165*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT 0x0 1166*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK 0xFFFFFFFFL 1167*b77a9fdfSHawking Zhang //MMSCH_VF_MAILBOX_1 1168*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX_1__DATA__SHIFT 0x0 1169*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX_1__DATA_MASK 0xFFFFFFFFL 1170*b77a9fdfSHawking Zhang //MMSCH_VF_MAILBOX_1_RESP 1171*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT 0x0 1172*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK 0xFFFFFFFFL 1173*b77a9fdfSHawking Zhang //MMSCH_CNTL 1174*b77a9fdfSHawking Zhang #define MMSCH_CNTL__CLK_EN__SHIFT 0x0 1175*b77a9fdfSHawking Zhang #define MMSCH_CNTL__ED_ENABLE__SHIFT 0x1 1176*b77a9fdfSHawking Zhang #define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5 1177*b77a9fdfSHawking Zhang #define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT 0x9 1178*b77a9fdfSHawking Zhang #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa 1179*b77a9fdfSHawking Zhang #define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 1180*b77a9fdfSHawking Zhang #define MMSCH_CNTL__TIMEOUT_DIS__SHIFT 0x1c 1181*b77a9fdfSHawking Zhang #define MMSCH_CNTL__CLK_EN_MASK 0x00000001L 1182*b77a9fdfSHawking Zhang #define MMSCH_CNTL__ED_ENABLE_MASK 0x00000002L 1183*b77a9fdfSHawking Zhang #define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK 0x000001E0L 1184*b77a9fdfSHawking Zhang #define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK 0x00000200L 1185*b77a9fdfSHawking Zhang #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK 0x00000400L 1186*b77a9fdfSHawking Zhang #define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 1187*b77a9fdfSHawking Zhang #define MMSCH_CNTL__TIMEOUT_DIS_MASK 0x10000000L 1188*b77a9fdfSHawking Zhang //MMSCH_NONCACHE_OFFSET0 1189*b77a9fdfSHawking Zhang #define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT 0x0 1190*b77a9fdfSHawking Zhang #define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL 1191*b77a9fdfSHawking Zhang //MMSCH_NONCACHE_SIZE0 1192*b77a9fdfSHawking Zhang #define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT 0x0 1193*b77a9fdfSHawking Zhang #define MMSCH_NONCACHE_SIZE0__SIZE_MASK 0x00FFFFFFL 1194*b77a9fdfSHawking Zhang //MMSCH_NONCACHE_OFFSET1 1195*b77a9fdfSHawking Zhang #define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT 0x0 1196*b77a9fdfSHawking Zhang #define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL 1197*b77a9fdfSHawking Zhang //MMSCH_NONCACHE_SIZE1 1198*b77a9fdfSHawking Zhang #define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT 0x0 1199*b77a9fdfSHawking Zhang #define MMSCH_NONCACHE_SIZE1__SIZE_MASK 0x00FFFFFFL 1200*b77a9fdfSHawking Zhang //MMSCH_PROC_STATE1 1201*b77a9fdfSHawking Zhang #define MMSCH_PROC_STATE1__PC__SHIFT 0x0 1202*b77a9fdfSHawking Zhang #define MMSCH_PROC_STATE1__PC_MASK 0xFFFFFFFFL 1203*b77a9fdfSHawking Zhang //MMSCH_LAST_MC_ADDR 1204*b77a9fdfSHawking Zhang #define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT 0x0 1205*b77a9fdfSHawking Zhang #define MMSCH_LAST_MC_ADDR__RW__SHIFT 0x1f 1206*b77a9fdfSHawking Zhang #define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK 0x0FFFFFFFL 1207*b77a9fdfSHawking Zhang #define MMSCH_LAST_MC_ADDR__RW_MASK 0x80000000L 1208*b77a9fdfSHawking Zhang //MMSCH_LAST_MEM_ACCESS_HI 1209*b77a9fdfSHawking Zhang #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT 0x0 1210*b77a9fdfSHawking Zhang #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT 0x8 1211*b77a9fdfSHawking Zhang #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT 0xc 1212*b77a9fdfSHawking Zhang #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK 0x00000007L 1213*b77a9fdfSHawking Zhang #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK 0x00000700L 1214*b77a9fdfSHawking Zhang #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK 0x00007000L 1215*b77a9fdfSHawking Zhang //MMSCH_LAST_MEM_ACCESS_LO 1216*b77a9fdfSHawking Zhang #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT 0x0 1217*b77a9fdfSHawking Zhang #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK 0xFFFFFFFFL 1218*b77a9fdfSHawking Zhang //MMSCH_SCRATCH_0 1219*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT 0x0 1220*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL 1221*b77a9fdfSHawking Zhang //MMSCH_SCRATCH_1 1222*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT 0x0 1223*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL 1224*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_SCH_BLOCK_0 1225*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT 0x0 1226*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT 0x4 1227*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT 0x8 1228*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK 0x0000000FL 1229*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK 0x000000F0L 1230*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK 0x0000FF00L 1231*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_CMD_CONTROL_0 1232*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT 0x0 1233*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT 0x4 1234*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5 1235*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT 0x6 1236*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT 0x8 1237*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT 0x10 1238*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK 0x0000000FL 1239*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK 0x00000010L 1240*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 1241*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK 0x00000040L 1242*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK 0x0000FF00L 1243*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 1244*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_CMD_STATUS_0 1245*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT 0x0 1246*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK 0x0000000FL 1247*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_VM_BUSY_STATUS_0 1248*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 1249*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 1250*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_ACTIVE_FCNS_0 1251*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT 0x0 1252*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK 0xFFFFFFFFL 1253*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_ACTIVE_FCN_ID_0 1254*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT 0x0 1255*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT 0x8 1256*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK 0x000000FFL 1257*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK 0x00000F00L 1258*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_DW6_0 1259*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW6_0__DATA__SHIFT 0x0 1260*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW6_0__DATA_MASK 0xFFFFFFFFL 1261*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_DW7_0 1262*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW7_0__DATA__SHIFT 0x0 1263*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW7_0__DATA_MASK 0xFFFFFFFFL 1264*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_DW8_0 1265*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW8_0__DATA__SHIFT 0x0 1266*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW8_0__DATA_MASK 0xFFFFFFFFL 1267*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_SCH_BLOCK_1 1268*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT 0x0 1269*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT 0x4 1270*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT 0x8 1271*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK 0x0000000FL 1272*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK 0x000000F0L 1273*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK 0x0000FF00L 1274*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_CMD_CONTROL_1 1275*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT 0x0 1276*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT 0x4 1277*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 1278*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT 0x6 1279*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT 0x8 1280*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT 0x10 1281*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK 0x0000000FL 1282*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK 0x00000010L 1283*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 1284*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK 0x00000040L 1285*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK 0x0000FF00L 1286*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 1287*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_CMD_STATUS_1 1288*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT 0x0 1289*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK 0x0000000FL 1290*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_VM_BUSY_STATUS_1 1291*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 1292*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 1293*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_ACTIVE_FCNS_1 1294*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT 0x0 1295*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK 0xFFFFFFFFL 1296*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_ACTIVE_FCN_ID_1 1297*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT 0x0 1298*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT 0x8 1299*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK 0x000000FFL 1300*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK 0x00000F00L 1301*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_DW6_1 1302*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW6_1__DATA__SHIFT 0x0 1303*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW6_1__DATA_MASK 0xFFFFFFFFL 1304*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_DW7_1 1305*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW7_1__DATA__SHIFT 0x0 1306*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW7_1__DATA_MASK 0xFFFFFFFFL 1307*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_DW8_1 1308*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW8_1__DATA__SHIFT 0x0 1309*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW8_1__DATA_MASK 0xFFFFFFFFL 1310*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_CNTXT 1311*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT 0x0 1312*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT 0x7 1313*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa 1314*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK 0x0000007FL 1315*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK 0x00000080L 1316*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK 0xFFFFFC00L 1317*b77a9fdfSHawking Zhang //MMSCH_SCRATCH_2 1318*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT 0x0 1319*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_2__SCRATCH_2_MASK 0xFFFFFFFFL 1320*b77a9fdfSHawking Zhang //MMSCH_SCRATCH_3 1321*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT 0x0 1322*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_3__SCRATCH_3_MASK 0xFFFFFFFFL 1323*b77a9fdfSHawking Zhang //MMSCH_SCRATCH_4 1324*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT 0x0 1325*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL 1326*b77a9fdfSHawking Zhang //MMSCH_SCRATCH_5 1327*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT 0x0 1328*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL 1329*b77a9fdfSHawking Zhang //MMSCH_SCRATCH_6 1330*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT 0x0 1331*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_6__SCRATCH_6_MASK 0xFFFFFFFFL 1332*b77a9fdfSHawking Zhang //MMSCH_SCRATCH_7 1333*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT 0x0 1334*b77a9fdfSHawking Zhang #define MMSCH_SCRATCH_7__SCRATCH_7_MASK 0xFFFFFFFFL 1335*b77a9fdfSHawking Zhang //MMSCH_VFID_FIFO_HEAD_0 1336*b77a9fdfSHawking Zhang #define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT 0x0 1337*b77a9fdfSHawking Zhang #define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK 0x0000003FL 1338*b77a9fdfSHawking Zhang //MMSCH_VFID_FIFO_TAIL_0 1339*b77a9fdfSHawking Zhang #define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT 0x0 1340*b77a9fdfSHawking Zhang #define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK 0x0000003FL 1341*b77a9fdfSHawking Zhang //MMSCH_VFID_FIFO_HEAD_1 1342*b77a9fdfSHawking Zhang #define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT 0x0 1343*b77a9fdfSHawking Zhang #define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK 0x0000003FL 1344*b77a9fdfSHawking Zhang //MMSCH_VFID_FIFO_TAIL_1 1345*b77a9fdfSHawking Zhang #define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT 0x0 1346*b77a9fdfSHawking Zhang #define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK 0x0000003FL 1347*b77a9fdfSHawking Zhang //MMSCH_NACK_STATUS 1348*b77a9fdfSHawking Zhang #define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT 0x0 1349*b77a9fdfSHawking Zhang #define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT 0x2 1350*b77a9fdfSHawking Zhang #define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK 0x00000003L 1351*b77a9fdfSHawking Zhang #define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK 0x0000000CL 1352*b77a9fdfSHawking Zhang //MMSCH_VF_MAILBOX0_DATA 1353*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT 0x0 1354*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX0_DATA__DATA_MASK 0xFFFFFFFFL 1355*b77a9fdfSHawking Zhang //MMSCH_VF_MAILBOX1_DATA 1356*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT 0x0 1357*b77a9fdfSHawking Zhang #define MMSCH_VF_MAILBOX1_DATA__DATA_MASK 0xFFFFFFFFL 1358*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_SCH_BLOCK_IP_0 1359*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT 0x0 1360*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT 0x4 1361*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT 0x8 1362*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK 0x0000000FL 1363*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK 0x000000F0L 1364*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK 0x0000FF00L 1365*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_CMD_STATUS_IP_0 1366*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT 0x0 1367*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK 0x0000000FL 1368*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 1369*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT 0x0 1370*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT 0x8 1371*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK 0x000000FFL 1372*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK 0x00000F00L 1373*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_SCH_BLOCK_IP_1 1374*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT 0x0 1375*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT 0x4 1376*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT 0x8 1377*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK 0x0000000FL 1378*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK 0x000000F0L 1379*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK 0x0000FF00L 1380*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_CMD_STATUS_IP_1 1381*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT 0x0 1382*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK 0x0000000FL 1383*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 1384*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT 0x0 1385*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT 0x8 1386*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK 0x000000FFL 1387*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK 0x00000F00L 1388*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_CNTXT_IP 1389*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT 0x0 1390*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT 0x7 1391*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK 0x0000007FL 1392*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK 0x00000080L 1393*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_SCH_BLOCK_2 1394*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT 0x0 1395*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT 0x4 1396*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT 0x8 1397*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK 0x0000000FL 1398*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK 0x000000F0L 1399*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK 0x0000FF00L 1400*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_CMD_CONTROL_2 1401*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT 0x0 1402*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT 0x4 1403*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5 1404*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT 0x6 1405*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT 0x8 1406*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT 0x10 1407*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK 0x0000000FL 1408*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK 0x00000010L 1409*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 1410*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK 0x00000040L 1411*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK 0x0000FF00L 1412*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 1413*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_CMD_STATUS_2 1414*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT 0x0 1415*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK 0x0000000FL 1416*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_VM_BUSY_STATUS_2 1417*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 1418*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 1419*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_ACTIVE_FCNS_2 1420*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT 0x0 1421*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK 0xFFFFFFFFL 1422*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_ACTIVE_FCN_ID_2 1423*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT 0x0 1424*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT 0x8 1425*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK 0x000000FFL 1426*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK 0x00000F00L 1427*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_DW6_2 1428*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW6_2__DATA__SHIFT 0x0 1429*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW6_2__DATA_MASK 0xFFFFFFFFL 1430*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_DW7_2 1431*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW7_2__DATA__SHIFT 0x0 1432*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW7_2__DATA_MASK 0xFFFFFFFFL 1433*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_DW8_2 1434*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW8_2__DATA__SHIFT 0x0 1435*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_DW8_2__DATA_MASK 0xFFFFFFFFL 1436*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_SCH_BLOCK_IP_2 1437*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT 0x0 1438*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT 0x4 1439*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT 0x8 1440*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK 0x0000000FL 1441*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK 0x000000F0L 1442*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK 0x0000FF00L 1443*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_CMD_STATUS_IP_2 1444*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT 0x0 1445*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK 0x0000000FL 1446*b77a9fdfSHawking Zhang //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 1447*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT 0x0 1448*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT 0x8 1449*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK 0x000000FFL 1450*b77a9fdfSHawking Zhang #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK 0x00000F00L 1451*b77a9fdfSHawking Zhang //MMSCH_VFID_FIFO_HEAD_2 1452*b77a9fdfSHawking Zhang #define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT 0x0 1453*b77a9fdfSHawking Zhang #define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK 0x0000003FL 1454*b77a9fdfSHawking Zhang //MMSCH_VFID_FIFO_TAIL_2 1455*b77a9fdfSHawking Zhang #define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT 0x0 1456*b77a9fdfSHawking Zhang #define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK 0x0000003FL 1457*b77a9fdfSHawking Zhang //MMSCH_VM_BUSY_STATUS_0 1458*b77a9fdfSHawking Zhang #define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 1459*b77a9fdfSHawking Zhang #define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 1460*b77a9fdfSHawking Zhang //MMSCH_VM_BUSY_STATUS_1 1461*b77a9fdfSHawking Zhang #define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 1462*b77a9fdfSHawking Zhang #define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 1463*b77a9fdfSHawking Zhang //MMSCH_VM_BUSY_STATUS_2 1464*b77a9fdfSHawking Zhang #define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 1465*b77a9fdfSHawking Zhang #define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 1466*b77a9fdfSHawking Zhang 1467*b77a9fdfSHawking Zhang 1468*b77a9fdfSHawking Zhang // addressBlock: uvd0_uvd_jmi_dec 1469*b77a9fdfSHawking Zhang //UVD_JADP_MCIF_URGENT_CTRL 1470*b77a9fdfSHawking Zhang #define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK__SHIFT 0x0 1471*b77a9fdfSHawking Zhang #define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK__SHIFT 0x6 1472*b77a9fdfSHawking Zhang #define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER__SHIFT 0xb 1473*b77a9fdfSHawking Zhang #define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP__SHIFT 0x11 1474*b77a9fdfSHawking Zhang #define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP__SHIFT 0x15 1475*b77a9fdfSHawking Zhang #define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN__SHIFT 0x19 1476*b77a9fdfSHawking Zhang #define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN__SHIFT 0x1a 1477*b77a9fdfSHawking Zhang #define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK_MASK 0x0000003FL 1478*b77a9fdfSHawking Zhang #define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK_MASK 0x000007C0L 1479*b77a9fdfSHawking Zhang #define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER_MASK 0x0001F800L 1480*b77a9fdfSHawking Zhang #define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP_MASK 0x001E0000L 1481*b77a9fdfSHawking Zhang #define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP_MASK 0x01E00000L 1482*b77a9fdfSHawking Zhang #define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN_MASK 0x02000000L 1483*b77a9fdfSHawking Zhang #define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN_MASK 0x04000000L 1484*b77a9fdfSHawking Zhang //UVD_JMI_URGENT_CTRL 1485*b77a9fdfSHawking Zhang #define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 1486*b77a9fdfSHawking Zhang #define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x4 1487*b77a9fdfSHawking Zhang #define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x10 1488*b77a9fdfSHawking Zhang #define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0x14 1489*b77a9fdfSHawking Zhang #define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 1490*b77a9fdfSHawking Zhang #define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x000000F0L 1491*b77a9fdfSHawking Zhang #define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00010000L 1492*b77a9fdfSHawking Zhang #define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00F00000L 1493*b77a9fdfSHawking Zhang //UVD_JPEG_DEC_PF_CTRL 1494*b77a9fdfSHawking Zhang #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 1495*b77a9fdfSHawking Zhang #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 1496*b77a9fdfSHawking Zhang #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L 1497*b77a9fdfSHawking Zhang #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L 1498*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_PF_CTRL 1499*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS__SHIFT 0x0 1500*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING__SHIFT 0x1 1501*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS_MASK 0x00000001L 1502*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING_MASK 0x00000002L 1503*b77a9fdfSHawking Zhang //UVD_JMI_CTRL 1504*b77a9fdfSHawking Zhang #define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0 1505*b77a9fdfSHawking Zhang #define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1 1506*b77a9fdfSHawking Zhang #define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2 1507*b77a9fdfSHawking Zhang #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8 1508*b77a9fdfSHawking Zhang #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10 1509*b77a9fdfSHawking Zhang #define UVD_JMI_CTRL__CRC_RESET__SHIFT 0x18 1510*b77a9fdfSHawking Zhang #define UVD_JMI_CTRL__CRC_SEL__SHIFT 0x19 1511*b77a9fdfSHawking Zhang #define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L 1512*b77a9fdfSHawking Zhang #define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L 1513*b77a9fdfSHawking Zhang #define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L 1514*b77a9fdfSHawking Zhang #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L 1515*b77a9fdfSHawking Zhang #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L 1516*b77a9fdfSHawking Zhang #define UVD_JMI_CTRL__CRC_RESET_MASK 0x01000000L 1517*b77a9fdfSHawking Zhang #define UVD_JMI_CTRL__CRC_SEL_MASK 0x1E000000L 1518*b77a9fdfSHawking Zhang //UVD_LMI_JRBC_CTRL 1519*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1520*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1521*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 1522*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 1523*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 1524*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 1525*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1526*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1527*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1528*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1529*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 1530*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 1531*b77a9fdfSHawking Zhang //UVD_LMI_JPEG_CTRL 1532*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1533*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1534*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 1535*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 1536*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 1537*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 1538*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1539*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1540*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1541*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1542*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 1543*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 1544*b77a9fdfSHawking Zhang //UVD_JMI_EJRBC_CTRL 1545*b77a9fdfSHawking Zhang #define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1546*b77a9fdfSHawking Zhang #define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1547*b77a9fdfSHawking Zhang #define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 1548*b77a9fdfSHawking Zhang #define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 1549*b77a9fdfSHawking Zhang #define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT 0x14 1550*b77a9fdfSHawking Zhang #define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT 0x16 1551*b77a9fdfSHawking Zhang #define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1552*b77a9fdfSHawking Zhang #define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1553*b77a9fdfSHawking Zhang #define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1554*b77a9fdfSHawking Zhang #define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1555*b77a9fdfSHawking Zhang #define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK 0x00300000L 1556*b77a9fdfSHawking Zhang #define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK 0x00C00000L 1557*b77a9fdfSHawking Zhang //UVD_LMI_EJPEG_CTRL 1558*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1559*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1560*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 1561*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 1562*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT 0x14 1563*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT 0x16 1564*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1565*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1566*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1567*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1568*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK 0x00300000L 1569*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK 0x00C00000L 1570*b77a9fdfSHawking Zhang //UVD_JMI_SCALER_CTRL 1571*b77a9fdfSHawking Zhang #define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1572*b77a9fdfSHawking Zhang #define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1573*b77a9fdfSHawking Zhang #define UVD_JMI_SCALER_CTRL__RD_MAX_BURST__SHIFT 0x4 1574*b77a9fdfSHawking Zhang #define UVD_JMI_SCALER_CTRL__WR_MAX_BURST__SHIFT 0x8 1575*b77a9fdfSHawking Zhang #define UVD_JMI_SCALER_CTRL__RD_SWAP__SHIFT 0x14 1576*b77a9fdfSHawking Zhang #define UVD_JMI_SCALER_CTRL__WR_SWAP__SHIFT 0x16 1577*b77a9fdfSHawking Zhang #define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1578*b77a9fdfSHawking Zhang #define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1579*b77a9fdfSHawking Zhang #define UVD_JMI_SCALER_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1580*b77a9fdfSHawking Zhang #define UVD_JMI_SCALER_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1581*b77a9fdfSHawking Zhang #define UVD_JMI_SCALER_CTRL__RD_SWAP_MASK 0x00300000L 1582*b77a9fdfSHawking Zhang #define UVD_JMI_SCALER_CTRL__WR_SWAP_MASK 0x00C00000L 1583*b77a9fdfSHawking Zhang //JPEG_LMI_DROP 1584*b77a9fdfSHawking Zhang #define JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 1585*b77a9fdfSHawking Zhang #define JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 1586*b77a9fdfSHawking Zhang #define JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 1587*b77a9fdfSHawking Zhang #define JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 1588*b77a9fdfSHawking Zhang #define JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L 1589*b77a9fdfSHawking Zhang #define JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L 1590*b77a9fdfSHawking Zhang #define JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L 1591*b77a9fdfSHawking Zhang #define JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L 1592*b77a9fdfSHawking Zhang //UVD_JMI_EJPEG_DROP 1593*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP__SHIFT 0x0 1594*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP__SHIFT 0x1 1595*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP__SHIFT 0x2 1596*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP__SHIFT 0x3 1597*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP__SHIFT 0x4 1598*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP__SHIFT 0x5 1599*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP_MASK 0x00000001L 1600*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP_MASK 0x00000002L 1601*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP_MASK 0x00000004L 1602*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP_MASK 0x00000008L 1603*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP_MASK 0x00000010L 1604*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP_MASK 0x00000020L 1605*b77a9fdfSHawking Zhang //JPEG_MEMCHECK_CLAMPING 1606*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0xd 1607*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN__SHIFT 0xe 1608*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x16 1609*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN__SHIFT 0x17 1610*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x19 1611*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1a 1612*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f 1613*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00002000L 1614*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN_MASK 0x00004000L 1615*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00400000L 1616*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN_MASK 0x00800000L 1617*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x02000000L 1618*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x04000000L 1619*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L 1620*b77a9fdfSHawking Zhang //UVD_JMI_EJPEG_MEMCHECK_CLAMPING 1621*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x0 1622*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1 1623*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x2 1624*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0x3 1625*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN__SHIFT 0x4 1626*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN__SHIFT 0x5 1627*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f 1628*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x00000001L 1629*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x00000002L 1630*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00000004L 1631*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00000008L 1632*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN_MASK 0x00000010L 1633*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN_MASK 0x00000020L 1634*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L 1635*b77a9fdfSHawking Zhang //UVD_LMI_JRBC_IB_VMID 1636*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1637*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1638*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1639*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1640*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1641*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1642*b77a9fdfSHawking Zhang //UVD_LMI_JRBC_RB_VMID 1643*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1644*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1645*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1646*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1647*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1648*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1649*b77a9fdfSHawking Zhang //UVD_LMI_JPEG_VMID 1650*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 1651*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 1652*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 1653*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 1654*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 1655*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 1656*b77a9fdfSHawking Zhang //UVD_JMI_ENC_JRBC_IB_VMID 1657*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1658*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1659*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1660*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1661*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1662*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1663*b77a9fdfSHawking Zhang //UVD_JMI_ENC_JRBC_RB_VMID 1664*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1665*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1666*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1667*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1668*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1669*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1670*b77a9fdfSHawking Zhang //UVD_JMI_ENC_JPEG_VMID 1671*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT 0x0 1672*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5 1673*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa 1674*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT 0xf 1675*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT 0x13 1676*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT 0x17 1677*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK 0x0000000FL 1678*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK 0x000001E0L 1679*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK 0x00003C00L 1680*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK 0x00078000L 1681*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK 0x00780000L 1682*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK 0x07800000L 1683*b77a9fdfSHawking Zhang //UVD_JMI_EJPEG_RAS_CNTL 1684*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_IH_EN__SHIFT 0x0 1685*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_PMI_EN__SHIFT 0x1 1686*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_REARM__SHIFT 0x2 1687*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_STALL_EN__SHIFT 0x3 1688*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_READY__SHIFT 0x4 1689*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_IH_EN_MASK 0x00000001L 1690*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_PMI_EN_MASK 0x00000002L 1691*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_REARM_MASK 0x00000004L 1692*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_STALL_EN_MASK 0x00000008L 1693*b77a9fdfSHawking Zhang #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_READY_MASK 0x00000010L 1694*b77a9fdfSHawking Zhang //JPEG_MEMCHECK_SAFE_ADDR 1695*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR__SHIFT 0x0 1696*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR_MASK 0xFFFFFFFFL 1697*b77a9fdfSHawking Zhang //JPEG_MEMCHECK_SAFE_ADDR_64BIT 1698*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT__SHIFT 0x0 1699*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT_MASK 0xFFFFFFFFL 1700*b77a9fdfSHawking Zhang //UVD_JMI_LAT_CTRL 1701*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CTRL__SCALE__SHIFT 0x0 1702*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CTRL__MAX_START__SHIFT 0x8 1703*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CTRL__MIN_START__SHIFT 0x9 1704*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CTRL__AVG_START__SHIFT 0xa 1705*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 1706*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CTRL__SKIP__SHIFT 0x10 1707*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CTRL__SCALE_MASK 0x000000FFL 1708*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CTRL__MAX_START_MASK 0x00000100L 1709*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CTRL__MIN_START_MASK 0x00000200L 1710*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CTRL__AVG_START_MASK 0x00000400L 1711*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 1712*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CTRL__SKIP_MASK 0x000F0000L 1713*b77a9fdfSHawking Zhang //UVD_JMI_LAT_CNTR 1714*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 1715*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 1716*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 1717*b77a9fdfSHawking Zhang #define UVD_JMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 1718*b77a9fdfSHawking Zhang //UVD_JMI_AVG_LAT_CNTR 1719*b77a9fdfSHawking Zhang #define UVD_JMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 1720*b77a9fdfSHawking Zhang #define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 1721*b77a9fdfSHawking Zhang #define UVD_JMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 1722*b77a9fdfSHawking Zhang #define UVD_JMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 1723*b77a9fdfSHawking Zhang #define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 1724*b77a9fdfSHawking Zhang #define UVD_JMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 1725*b77a9fdfSHawking Zhang //UVD_JMI_PERFMON_CTRL 1726*b77a9fdfSHawking Zhang #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 1727*b77a9fdfSHawking Zhang #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 1728*b77a9fdfSHawking Zhang #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 1729*b77a9fdfSHawking Zhang #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00000F00L 1730*b77a9fdfSHawking Zhang //UVD_JMI_PERFMON_COUNT_LO 1731*b77a9fdfSHawking Zhang #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 1732*b77a9fdfSHawking Zhang #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 1733*b77a9fdfSHawking Zhang //UVD_JMI_PERFMON_COUNT_HI 1734*b77a9fdfSHawking Zhang #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 1735*b77a9fdfSHawking Zhang #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 1736*b77a9fdfSHawking Zhang //UVD_JMI_CLEAN_STATUS 1737*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN__SHIFT 0x0 1738*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW__SHIFT 0x1 1739*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN__SHIFT 0x2 1740*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW__SHIFT 0x3 1741*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN__SHIFT 0x4 1742*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN__SHIFT 0x5 1743*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN__SHIFT 0x6 1744*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN__SHIFT 0x7 1745*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN__SHIFT 0x8 1746*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN__SHIFT 0x9 1747*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN__SHIFT 0xa 1748*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN__SHIFT 0xb 1749*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN__SHIFT 0xc 1750*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN__SHIFT 0xd 1751*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING__SHIFT 0xe 1752*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN__SHIFT 0xf 1753*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN__SHIFT 0x10 1754*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_MASK 0x00000001L 1755*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW_MASK 0x00000002L 1756*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_MASK 0x00000004L 1757*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW_MASK 0x00000008L 1758*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN_MASK 0x00000010L 1759*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN_MASK 0x00000020L 1760*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN_MASK 0x00000040L 1761*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN_MASK 0x00000080L 1762*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN_MASK 0x00000100L 1763*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN_MASK 0x00000200L 1764*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN_MASK 0x00000400L 1765*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN_MASK 0x00000800L 1766*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN_MASK 0x00001000L 1767*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN_MASK 0x00002000L 1768*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING_MASK 0x00004000L 1769*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN_MASK 0x00008000L 1770*b77a9fdfSHawking Zhang #define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN_MASK 0x00010000L 1771*b77a9fdfSHawking Zhang //UVD_LMI_JPEG_READ_64BIT_BAR_LOW 1772*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1773*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1774*b77a9fdfSHawking Zhang //UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 1775*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1776*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1777*b77a9fdfSHawking Zhang //UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 1778*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1779*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1780*b77a9fdfSHawking Zhang //UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 1781*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1782*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1783*b77a9fdfSHawking Zhang //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1784*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1785*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1786*b77a9fdfSHawking Zhang //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1787*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1788*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1789*b77a9fdfSHawking Zhang //UVD_LMI_JRBC_RB_64BIT_BAR_LOW 1790*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1791*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1792*b77a9fdfSHawking Zhang //UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 1793*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1794*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1795*b77a9fdfSHawking Zhang //UVD_LMI_JRBC_IB_64BIT_BAR_LOW 1796*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1797*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1798*b77a9fdfSHawking Zhang //UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 1799*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1800*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1801*b77a9fdfSHawking Zhang //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 1802*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1803*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1804*b77a9fdfSHawking Zhang //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 1805*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1806*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1807*b77a9fdfSHawking Zhang //UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 1808*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1809*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1810*b77a9fdfSHawking Zhang //UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 1811*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1812*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1813*b77a9fdfSHawking Zhang //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 1814*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1815*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1816*b77a9fdfSHawking Zhang //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 1817*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1818*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1819*b77a9fdfSHawking Zhang //UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 1820*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1821*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1822*b77a9fdfSHawking Zhang //UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 1823*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1824*b77a9fdfSHawking Zhang #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1825*b77a9fdfSHawking Zhang //UVD_JMI_PEL_RD_64BIT_BAR_LOW 1826*b77a9fdfSHawking Zhang #define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1827*b77a9fdfSHawking Zhang #define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1828*b77a9fdfSHawking Zhang //UVD_JMI_PEL_RD_64BIT_BAR_HIGH 1829*b77a9fdfSHawking Zhang #define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1830*b77a9fdfSHawking Zhang #define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1831*b77a9fdfSHawking Zhang //UVD_JMI_BS_WR_64BIT_BAR_LOW 1832*b77a9fdfSHawking Zhang #define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1833*b77a9fdfSHawking Zhang #define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1834*b77a9fdfSHawking Zhang //UVD_JMI_BS_WR_64BIT_BAR_HIGH 1835*b77a9fdfSHawking Zhang #define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1836*b77a9fdfSHawking Zhang #define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1837*b77a9fdfSHawking Zhang //UVD_JMI_SCALAR_RD_64BIT_BAR_LOW 1838*b77a9fdfSHawking Zhang #define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1839*b77a9fdfSHawking Zhang #define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1840*b77a9fdfSHawking Zhang //UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH 1841*b77a9fdfSHawking Zhang #define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1842*b77a9fdfSHawking Zhang #define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1843*b77a9fdfSHawking Zhang //UVD_JMI_SCALAR_WR_64BIT_BAR_LOW 1844*b77a9fdfSHawking Zhang #define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1845*b77a9fdfSHawking Zhang #define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1846*b77a9fdfSHawking Zhang //UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH 1847*b77a9fdfSHawking Zhang #define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1848*b77a9fdfSHawking Zhang #define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1849*b77a9fdfSHawking Zhang //UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1850*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1851*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1852*b77a9fdfSHawking Zhang //UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1853*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1854*b77a9fdfSHawking Zhang #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1855*b77a9fdfSHawking Zhang //UVD_LMI_EJRBC_RB_64BIT_BAR_LOW 1856*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1857*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1858*b77a9fdfSHawking Zhang //UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 1859*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1860*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1861*b77a9fdfSHawking Zhang //UVD_LMI_EJRBC_IB_64BIT_BAR_LOW 1862*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1863*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1864*b77a9fdfSHawking Zhang //UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 1865*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1866*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1867*b77a9fdfSHawking Zhang //UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 1868*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1869*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1870*b77a9fdfSHawking Zhang //UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 1871*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1872*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1873*b77a9fdfSHawking Zhang //UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 1874*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1875*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1876*b77a9fdfSHawking Zhang //UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 1877*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1878*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1879*b77a9fdfSHawking Zhang //UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 1880*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1881*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1882*b77a9fdfSHawking Zhang //UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 1883*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1884*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1885*b77a9fdfSHawking Zhang //UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 1886*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1887*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1888*b77a9fdfSHawking Zhang //UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 1889*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1890*b77a9fdfSHawking Zhang #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1891*b77a9fdfSHawking Zhang //UVD_LMI_JPEG_PREEMPT_VMID 1892*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1893*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1894*b77a9fdfSHawking Zhang //UVD_LMI_ENC_JPEG_PREEMPT_VMID 1895*b77a9fdfSHawking Zhang #define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1896*b77a9fdfSHawking Zhang #define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1897*b77a9fdfSHawking Zhang //UVD_LMI_JPEG2_VMID 1898*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT 0x0 1899*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT 0x4 1900*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK 0x0000000FL 1901*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK 0x000000F0L 1902*b77a9fdfSHawking Zhang //UVD_LMI_JPEG2_READ_64BIT_BAR_LOW 1903*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1904*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1905*b77a9fdfSHawking Zhang //UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 1906*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1907*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1908*b77a9fdfSHawking Zhang //UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 1909*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1910*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1911*b77a9fdfSHawking Zhang //UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 1912*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1913*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1914*b77a9fdfSHawking Zhang //UVD_LMI_JPEG_CTRL2 1915*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT 0x0 1916*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT 0x1 1917*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT 0x4 1918*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT 0x8 1919*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT 0x14 1920*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT 0x16 1921*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK 0x00000001L 1922*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK 0x00000002L 1923*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK 0x000000F0L 1924*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK 0x00000F00L 1925*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK 0x00300000L 1926*b77a9fdfSHawking Zhang #define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK 0x00C00000L 1927*b77a9fdfSHawking Zhang //UVD_JMI_DEC_SWAP_CNTL 1928*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1929*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1930*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1931*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1932*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1933*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1934*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1935*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 1936*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 1937*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1938*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1939*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1940*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1941*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1942*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1943*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1944*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 1945*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 1946*b77a9fdfSHawking Zhang //UVD_JMI_ENC_SWAP_CNTL 1947*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1948*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1949*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1950*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1951*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1952*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1953*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1954*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT 0xe 1955*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT 0x10 1956*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT 0x12 1957*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT 0x14 1958*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT 0x16 1959*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1960*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1961*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1962*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1963*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1964*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1965*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1966*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK 0x0000C000L 1967*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK 0x00030000L 1968*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK 0x000C0000L 1969*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK 0x00300000L 1970*b77a9fdfSHawking Zhang #define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK 0x00C00000L 1971*b77a9fdfSHawking Zhang //UVD_JMI_CNTL 1972*b77a9fdfSHawking Zhang #define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0 1973*b77a9fdfSHawking Zhang #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8 1974*b77a9fdfSHawking Zhang #define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L 1975*b77a9fdfSHawking Zhang #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L 1976*b77a9fdfSHawking Zhang //UVD_JMI_ATOMIC_CNTL 1977*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 1978*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 1979*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 1980*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 1981*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 1982*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb 1983*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L 1984*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL 1985*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L 1986*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L 1987*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L 1988*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L 1989*b77a9fdfSHawking Zhang //UVD_JMI_ATOMIC_CNTL2 1990*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 1991*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 1992*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L 1993*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L 1994*b77a9fdfSHawking Zhang //UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 1995*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1996*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1997*b77a9fdfSHawking Zhang //UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 1998*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1999*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 2000*b77a9fdfSHawking Zhang //UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW 2001*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 2002*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 2003*b77a9fdfSHawking Zhang //UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH 2004*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 2005*b77a9fdfSHawking Zhang #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 2006*b77a9fdfSHawking Zhang //JPEG2_LMI_DROP 2007*b77a9fdfSHawking Zhang #define JPEG2_LMI_DROP__JPEG2_WR_DROP__SHIFT 0x0 2008*b77a9fdfSHawking Zhang #define JPEG2_LMI_DROP__JPEG2_RD_DROP__SHIFT 0x1 2009*b77a9fdfSHawking Zhang #define JPEG2_LMI_DROP__JPEG2_WR_DROP_MASK 0x00000001L 2010*b77a9fdfSHawking Zhang #define JPEG2_LMI_DROP__JPEG2_RD_DROP_MASK 0x00000002L 2011*b77a9fdfSHawking Zhang //UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 2012*b77a9fdfSHawking Zhang #define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 2013*b77a9fdfSHawking Zhang #define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 2014*b77a9fdfSHawking Zhang //UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 2015*b77a9fdfSHawking Zhang #define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 2016*b77a9fdfSHawking Zhang #define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 2017*b77a9fdfSHawking Zhang //UVD_JMI_DEC_SWAP_CNTL2 2018*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT 0x0 2019*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT 0x2 2020*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK 0x00000003L 2021*b77a9fdfSHawking Zhang #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK 0x0000000CL 2022*b77a9fdfSHawking Zhang //UVD_JMI_DJPEG_RAS_CNTL 2023*b77a9fdfSHawking Zhang #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_IH_EN__SHIFT 0x0 2024*b77a9fdfSHawking Zhang #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_PMI_EN__SHIFT 0x1 2025*b77a9fdfSHawking Zhang #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_REARM__SHIFT 0x2 2026*b77a9fdfSHawking Zhang #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_STALL_EN__SHIFT 0x3 2027*b77a9fdfSHawking Zhang #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_READY__SHIFT 0x4 2028*b77a9fdfSHawking Zhang #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_IH_EN_MASK 0x00000001L 2029*b77a9fdfSHawking Zhang #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_PMI_EN_MASK 0x00000002L 2030*b77a9fdfSHawking Zhang #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_REARM_MASK 0x00000004L 2031*b77a9fdfSHawking Zhang #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_STALL_EN_MASK 0x00000008L 2032*b77a9fdfSHawking Zhang #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_READY_MASK 0x00000010L 2033*b77a9fdfSHawking Zhang 2034*b77a9fdfSHawking Zhang 2035*b77a9fdfSHawking Zhang // addressBlock: uvd0_uvd_jpeg_common_dec 2036*b77a9fdfSHawking Zhang //JPEG_SOFT_RESET_STATUS 2037*b77a9fdfSHawking Zhang #define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT 0x0 2038*b77a9fdfSHawking Zhang #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x1 2039*b77a9fdfSHawking Zhang #define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT 0x2 2040*b77a9fdfSHawking Zhang #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x3 2041*b77a9fdfSHawking Zhang #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x4 2042*b77a9fdfSHawking Zhang #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5 2043*b77a9fdfSHawking Zhang #define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK 0x00000001L 2044*b77a9fdfSHawking Zhang #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000002L 2045*b77a9fdfSHawking Zhang #define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK 0x00000004L 2046*b77a9fdfSHawking Zhang #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00000008L 2047*b77a9fdfSHawking Zhang #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00000010L 2048*b77a9fdfSHawking Zhang #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x00000020L 2049*b77a9fdfSHawking Zhang //JPEG_SYS_INT_EN 2050*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT 0x0 2051*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__DJRBC__SHIFT 0x1 2052*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT 0x2 2053*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT 0x3 2054*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT 0x4 2055*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5 2056*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT 0x6 2057*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__DJPEG_RAS_CNTL__SHIFT 0x7 2058*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__EJPEG_RAS_CNTL__SHIFT 0x8 2059*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__DJPEG_CORE_MASK 0x00000001L 2060*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__DJRBC_MASK 0x00000002L 2061*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK 0x00000004L 2062*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK 0x00000008L 2063*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__EJPEG_CORE_MASK 0x00000010L 2064*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__EJRBC_MASK 0x00000020L 2065*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK 0x00000040L 2066*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__DJPEG_RAS_CNTL_MASK 0x00000080L 2067*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_EN__EJPEG_RAS_CNTL_MASK 0x00000100L 2068*b77a9fdfSHawking Zhang //JPEG_SYS_INT_STATUS 2069*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT 0x0 2070*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__DJRBC__SHIFT 0x1 2071*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT 0x2 2072*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT 0x3 2073*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT 0x4 2074*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5 2075*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT 0x6 2076*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__DJPEG_RAS_CNTL__SHIFT 0x7 2077*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__EJPEG_RAS_CNTL__SHIFT 0x8 2078*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK 0x00000001L 2079*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__DJRBC_MASK 0x00000002L 2080*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK 0x00000004L 2081*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK 0x00000008L 2082*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK 0x00000010L 2083*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__EJRBC_MASK 0x00000020L 2084*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK 0x00000040L 2085*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__DJPEG_RAS_CNTL_MASK 0x00000080L 2086*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_STATUS__EJPEG_RAS_CNTL_MASK 0x00000100L 2087*b77a9fdfSHawking Zhang //JPEG_SYS_INT_ACK 2088*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT 0x0 2089*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__DJRBC__SHIFT 0x1 2090*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT 0x2 2091*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT 0x3 2092*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT 0x4 2093*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5 2094*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT 0x6 2095*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__DJPEG_RAS_CNTL__SHIFT 0x7 2096*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__EJPEG_RAS_CNTL__SHIFT 0x8 2097*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK 0x00000001L 2098*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__DJRBC_MASK 0x00000002L 2099*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK 0x00000004L 2100*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK 0x00000008L 2101*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK 0x00000010L 2102*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__EJRBC_MASK 0x00000020L 2103*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK 0x00000040L 2104*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__DJPEG_RAS_CNTL_MASK 0x00000080L 2105*b77a9fdfSHawking Zhang #define JPEG_SYS_INT_ACK__EJPEG_RAS_CNTL_MASK 0x00000100L 2106*b77a9fdfSHawking Zhang //JPEG_MEMCHECK_SYS_INT_EN 2107*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN__SHIFT 0x0 2108*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN__SHIFT 0x1 2109*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN__SHIFT 0x2 2110*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN__SHIFT 0x3 2111*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN__SHIFT 0x4 2112*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN__SHIFT 0x5 2113*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN__SHIFT 0x6 2114*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN__SHIFT 0x7 2115*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN__SHIFT 0x8 2116*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN__SHIFT 0x9 2117*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN__SHIFT 0xa 2118*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN__SHIFT 0xb 2119*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN_MASK 0x00000001L 2120*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN_MASK 0x00000002L 2121*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN_MASK 0x00000004L 2122*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN_MASK 0x00000008L 2123*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN_MASK 0x00000010L 2124*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN_MASK 0x00000020L 2125*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN_MASK 0x00000040L 2126*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN_MASK 0x00000080L 2127*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN_MASK 0x00000100L 2128*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN_MASK 0x00000200L 2129*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN_MASK 0x00000400L 2130*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN_MASK 0x00000800L 2131*b77a9fdfSHawking Zhang //JPEG_MEMCHECK_SYS_INT_STAT 2132*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR__SHIFT 0x0 2133*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR__SHIFT 0x1 2134*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR__SHIFT 0x2 2135*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR__SHIFT 0x3 2136*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR__SHIFT 0x4 2137*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR__SHIFT 0x5 2138*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR__SHIFT 0x6 2139*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR__SHIFT 0x7 2140*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR__SHIFT 0x8 2141*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR__SHIFT 0x9 2142*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR__SHIFT 0xa 2143*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR__SHIFT 0xb 2144*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR__SHIFT 0xc 2145*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR__SHIFT 0xd 2146*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR__SHIFT 0xe 2147*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR__SHIFT 0xf 2148*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR__SHIFT 0x10 2149*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR__SHIFT 0x11 2150*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR__SHIFT 0x12 2151*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR__SHIFT 0x13 2152*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR__SHIFT 0x14 2153*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR__SHIFT 0x15 2154*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR__SHIFT 0x16 2155*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR__SHIFT 0x17 2156*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR_MASK 0x00000001L 2157*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR_MASK 0x00000002L 2158*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR_MASK 0x00000004L 2159*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR_MASK 0x00000008L 2160*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR_MASK 0x00000010L 2161*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR_MASK 0x00000020L 2162*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR_MASK 0x00000040L 2163*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR_MASK 0x00000080L 2164*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR_MASK 0x00000100L 2165*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR_MASK 0x00000200L 2166*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR_MASK 0x00000400L 2167*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR_MASK 0x00000800L 2168*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR_MASK 0x00001000L 2169*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR_MASK 0x00002000L 2170*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR_MASK 0x00004000L 2171*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR_MASK 0x00008000L 2172*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR_MASK 0x00010000L 2173*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR_MASK 0x00020000L 2174*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR_MASK 0x00040000L 2175*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR_MASK 0x00080000L 2176*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR_MASK 0x00100000L 2177*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR_MASK 0x00200000L 2178*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR_MASK 0x00400000L 2179*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR_MASK 0x00800000L 2180*b77a9fdfSHawking Zhang //JPEG_MEMCHECK_SYS_INT_ACK 2181*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR__SHIFT 0x0 2182*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR__SHIFT 0x1 2183*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR__SHIFT 0x2 2184*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR__SHIFT 0x3 2185*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR__SHIFT 0x4 2186*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR__SHIFT 0x5 2187*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR__SHIFT 0x6 2188*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR__SHIFT 0x7 2189*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR__SHIFT 0x8 2190*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR__SHIFT 0x9 2191*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR__SHIFT 0xa 2192*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR__SHIFT 0xb 2193*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR__SHIFT 0xc 2194*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR__SHIFT 0xd 2195*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR__SHIFT 0xe 2196*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR__SHIFT 0xf 2197*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR__SHIFT 0x10 2198*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR__SHIFT 0x11 2199*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR__SHIFT 0x12 2200*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR__SHIFT 0x13 2201*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR__SHIFT 0x14 2202*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR__SHIFT 0x15 2203*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR__SHIFT 0x16 2204*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR__SHIFT 0x17 2205*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR_MASK 0x00000001L 2206*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR_MASK 0x00000002L 2207*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR_MASK 0x00000004L 2208*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR_MASK 0x00000008L 2209*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR_MASK 0x00000010L 2210*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR_MASK 0x00000020L 2211*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR_MASK 0x00000040L 2212*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR_MASK 0x00000080L 2213*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR_MASK 0x00000100L 2214*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR_MASK 0x00000200L 2215*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR_MASK 0x00000400L 2216*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR_MASK 0x00000800L 2217*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR_MASK 0x00001000L 2218*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR_MASK 0x00002000L 2219*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR_MASK 0x00004000L 2220*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR_MASK 0x00008000L 2221*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR_MASK 0x00010000L 2222*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR_MASK 0x00020000L 2223*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR_MASK 0x00040000L 2224*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR_MASK 0x00080000L 2225*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR_MASK 0x00100000L 2226*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR_MASK 0x00200000L 2227*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR_MASK 0x00400000L 2228*b77a9fdfSHawking Zhang #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR_MASK 0x00800000L 2229*b77a9fdfSHawking Zhang //JPEG_MASTINT_EN 2230*b77a9fdfSHawking Zhang #define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 2231*b77a9fdfSHawking Zhang #define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 2232*b77a9fdfSHawking Zhang #define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 2233*b77a9fdfSHawking Zhang #define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 2234*b77a9fdfSHawking Zhang //JPEG_IH_CTRL 2235*b77a9fdfSHawking Zhang #define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 2236*b77a9fdfSHawking Zhang #define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1 2237*b77a9fdfSHawking Zhang #define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 2238*b77a9fdfSHawking Zhang #define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3 2239*b77a9fdfSHawking Zhang #define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7 2240*b77a9fdfSHawking Zhang #define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13 2241*b77a9fdfSHawking Zhang #define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L 2242*b77a9fdfSHawking Zhang #define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L 2243*b77a9fdfSHawking Zhang #define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 2244*b77a9fdfSHawking Zhang #define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L 2245*b77a9fdfSHawking Zhang #define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L 2246*b77a9fdfSHawking Zhang #define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L 2247*b77a9fdfSHawking Zhang //JRBBM_ARB_CTRL 2248*b77a9fdfSHawking Zhang #define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT 0x0 2249*b77a9fdfSHawking Zhang #define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1 2250*b77a9fdfSHawking Zhang #define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x2 2251*b77a9fdfSHawking Zhang #define JRBBM_ARB_CTRL__DJRBC_DROP_MASK 0x00000001L 2252*b77a9fdfSHawking Zhang #define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L 2253*b77a9fdfSHawking Zhang #define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000004L 2254*b77a9fdfSHawking Zhang 2255*b77a9fdfSHawking Zhang 2256*b77a9fdfSHawking Zhang // addressBlock: uvd0_uvd_jpeg_common_sclk_dec 2257*b77a9fdfSHawking Zhang //JPEG_CGC_GATE 2258*b77a9fdfSHawking Zhang #define JPEG_CGC_GATE__JPEG_DEC__SHIFT 0x0 2259*b77a9fdfSHawking Zhang #define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x1 2260*b77a9fdfSHawking Zhang #define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x2 2261*b77a9fdfSHawking Zhang #define JPEG_CGC_GATE__JMCIF__SHIFT 0x3 2262*b77a9fdfSHawking Zhang #define JPEG_CGC_GATE__JRBBM__SHIFT 0x4 2263*b77a9fdfSHawking Zhang #define JPEG_CGC_GATE__JPEG_DEC_MASK 0x00000001L 2264*b77a9fdfSHawking Zhang #define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000002L 2265*b77a9fdfSHawking Zhang #define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000004L 2266*b77a9fdfSHawking Zhang #define JPEG_CGC_GATE__JMCIF_MASK 0x00000008L 2267*b77a9fdfSHawking Zhang #define JPEG_CGC_GATE__JRBBM_MASK 0x00000010L 2268*b77a9fdfSHawking Zhang //JPEG_CGC_CTRL 2269*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 2270*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1 2271*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5 2272*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN__SHIFT 0xa 2273*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN__SHIFT 0xb 2274*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__GATER_DIV_ID__SHIFT 0xc 2275*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT 0x10 2276*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x11 2277*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x12 2278*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x13 2279*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x14 2280*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 2281*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL 2282*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000003E0L 2283*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN_MASK 0x00000400L 2284*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN_MASK 0x00000800L 2285*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__GATER_DIV_ID_MASK 0x00007000L 2286*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 0x00010000L 2287*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00020000L 2288*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x00040000L 2289*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x00080000L 2290*b77a9fdfSHawking Zhang #define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x00100000L 2291*b77a9fdfSHawking Zhang //JPEG_CGC_STATUS 2292*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT 0x0 2293*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT 0x1 2294*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x2 2295*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x3 2296*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x4 2297*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5 2298*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x6 2299*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x7 2300*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x8 2301*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK 0x00000001L 2302*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK 0x00000002L 2303*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000004L 2304*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000008L 2305*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00000010L 2306*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00000020L 2307*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00000040L 2308*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00000080L 2309*b77a9fdfSHawking Zhang #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00000100L 2310*b77a9fdfSHawking Zhang //JPEG_COMN_CGC_MEM_CTRL 2311*b77a9fdfSHawking Zhang #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0 2312*b77a9fdfSHawking Zhang #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1 2313*b77a9fdfSHawking Zhang #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2 2314*b77a9fdfSHawking Zhang #define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 2315*b77a9fdfSHawking Zhang #define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 2316*b77a9fdfSHawking Zhang #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L 2317*b77a9fdfSHawking Zhang #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L 2318*b77a9fdfSHawking Zhang #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L 2319*b77a9fdfSHawking Zhang #define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L 2320*b77a9fdfSHawking Zhang #define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L 2321*b77a9fdfSHawking Zhang //JPEG_DEC_CGC_MEM_CTRL 2322*b77a9fdfSHawking Zhang #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT 0x0 2323*b77a9fdfSHawking Zhang #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT 0x1 2324*b77a9fdfSHawking Zhang #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT 0x2 2325*b77a9fdfSHawking Zhang #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK 0x00000001L 2326*b77a9fdfSHawking Zhang #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK 0x00000002L 2327*b77a9fdfSHawking Zhang #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK 0x00000004L 2328*b77a9fdfSHawking Zhang //JPEG2_DEC_CGC_MEM_CTRL 2329*b77a9fdfSHawking Zhang #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x0 2330*b77a9fdfSHawking Zhang #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x1 2331*b77a9fdfSHawking Zhang #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0x2 2332*b77a9fdfSHawking Zhang #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000001L 2333*b77a9fdfSHawking Zhang #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000002L 2334*b77a9fdfSHawking Zhang #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000004L 2335*b77a9fdfSHawking Zhang //JPEG_ENC_CGC_MEM_CTRL 2336*b77a9fdfSHawking Zhang #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0 2337*b77a9fdfSHawking Zhang #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1 2338*b77a9fdfSHawking Zhang #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2 2339*b77a9fdfSHawking Zhang #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L 2340*b77a9fdfSHawking Zhang #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L 2341*b77a9fdfSHawking Zhang #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L 2342*b77a9fdfSHawking Zhang //JPEG_SOFT_RESET2 2343*b77a9fdfSHawking Zhang #define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 2344*b77a9fdfSHawking Zhang #define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 2345*b77a9fdfSHawking Zhang //JPEG_PERF_BANK_CONF 2346*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0 2347*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8 2348*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10 2349*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL 2350*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L 2351*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L 2352*b77a9fdfSHawking Zhang //JPEG_PERF_BANK_EVENT_SEL 2353*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0 2354*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8 2355*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10 2356*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18 2357*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL 2358*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L 2359*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L 2360*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L 2361*b77a9fdfSHawking Zhang //JPEG_PERF_BANK_COUNT0 2362*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0 2363*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL 2364*b77a9fdfSHawking Zhang //JPEG_PERF_BANK_COUNT1 2365*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0 2366*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL 2367*b77a9fdfSHawking Zhang //JPEG_PERF_BANK_COUNT2 2368*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0 2369*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL 2370*b77a9fdfSHawking Zhang //JPEG_PERF_BANK_COUNT3 2371*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0 2372*b77a9fdfSHawking Zhang #define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL 2373*b77a9fdfSHawking Zhang 2374*b77a9fdfSHawking Zhang 2375*b77a9fdfSHawking Zhang // addressBlock: uvd0_uvd_jpeg_enc_dec 2376*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_INT_EN 2377*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT 0x0 2378*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT 0x1 2379*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT 0x2 2380*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT 0x3 2381*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT 0x4 2382*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT 0x5 2383*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT 0x6 2384*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK 0x00000001L 2385*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK 0x00000002L 2386*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK 0x00000004L 2387*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK 0x00000008L 2388*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK 0x00000010L 2389*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK 0x00000020L 2390*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK 0x00000040L 2391*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_INT_STATUS 2392*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT 0x0 2393*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT 0x1 2394*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT 0x2 2395*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT 0x3 2396*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT 0x4 2397*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT 0x5 2398*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT 0x6 2399*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK 0x00000001L 2400*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK 0x00000002L 2401*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK 0x00000004L 2402*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK 0x00000008L 2403*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK 0x00000010L 2404*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK 0x00000020L 2405*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK 0x00000040L 2406*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_ENGINE_CNTL 2407*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT 0x0 2408*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT 0x1 2409*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT 0x2 2410*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT 0x3 2411*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT 0x4 2412*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT 0x9 2413*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK 0x00000001L 2414*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK 0x00000002L 2415*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK 0x00000004L 2416*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK 0x00000008L 2417*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK 0x00000010L 2418*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK 0x00000200L 2419*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_SCRATCH1 2420*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT 0x0 2421*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 2422*b77a9fdfSHawking Zhang 2423*b77a9fdfSHawking Zhang 2424*b77a9fdfSHawking Zhang // addressBlock: uvd0_uvd_jpeg_enc_sclk_dec 2425*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_SPS_INFO 2426*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT__SHIFT 0x0 2427*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT__SHIFT 0x3 2428*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422__SHIFT 0x4 2429*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT_MASK 0x00000007L 2430*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT_MASK 0x00000008L 2431*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422_MASK 0x00000010L 2432*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_SPS_INFO1 2433*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH__SHIFT 0x0 2434*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT__SHIFT 0x10 2435*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH_MASK 0x0000FFFFL 2436*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT_MASK 0xFFFF0000L 2437*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_TBL_SIZE 2438*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE__SHIFT 0x6 2439*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE_MASK 0x00000FC0L 2440*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_TBL_CNTL 2441*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL__SHIFT 0x0 2442*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE__SHIFT 0x1 2443*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE__SHIFT 0x2 2444*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN__SHIFT 0x4 2445*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL_MASK 0x00000001L 2446*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE_MASK 0x00000002L 2447*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE_MASK 0x0000000CL 2448*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN_MASK 0x00000010L 2449*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_MC_REQ_CNTL 2450*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK__SHIFT 0x0 2451*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK_MASK 0x0000003FL 2452*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_STATUS 2453*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT 0x0 2454*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT 0x1 2455*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT 0x2 2456*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT 0x3 2457*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK 0x00000001L 2458*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK 0x00000002L 2459*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK 0x00000004L 2460*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK 0x00000008L 2461*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_PITCH 2462*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT 0x0 2463*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT 0x10 2464*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PITCH__PITCH_Y_MASK 0x00000FFFL 2465*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PITCH__PITCH_UV_MASK 0x0FFF0000L 2466*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_LUMA_BASE 2467*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT 0x0 2468*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK 0xFFFFFFFFL 2469*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_CHROMAU_BASE 2470*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT 0x0 2471*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK 0xFFFFFFFFL 2472*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_CHROMAV_BASE 2473*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT 0x0 2474*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK 0xFFFFFFFFL 2475*b77a9fdfSHawking Zhang //JPEG_ENC_Y_GFX10_TILING_SURFACE 2476*b77a9fdfSHawking Zhang #define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 2477*b77a9fdfSHawking Zhang #define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 2478*b77a9fdfSHawking Zhang //JPEG_ENC_UV_GFX10_TILING_SURFACE 2479*b77a9fdfSHawking Zhang #define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 2480*b77a9fdfSHawking Zhang #define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 2481*b77a9fdfSHawking Zhang //JPEG_ENC_GFX10_ADDR_CONFIG 2482*b77a9fdfSHawking Zhang #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 2483*b77a9fdfSHawking Zhang #define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 2484*b77a9fdfSHawking Zhang #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 2485*b77a9fdfSHawking Zhang #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 2486*b77a9fdfSHawking Zhang #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 2487*b77a9fdfSHawking Zhang #define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 2488*b77a9fdfSHawking Zhang #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 2489*b77a9fdfSHawking Zhang #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 2490*b77a9fdfSHawking Zhang //JPEG_ENC_ADDR_MODE 2491*b77a9fdfSHawking Zhang #define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 2492*b77a9fdfSHawking Zhang #define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 2493*b77a9fdfSHawking Zhang #define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 2494*b77a9fdfSHawking Zhang #define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 2495*b77a9fdfSHawking Zhang #define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 2496*b77a9fdfSHawking Zhang #define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 2497*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_GPCOM_CMD 2498*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT 0x1 2499*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK 0x0000000EL 2500*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_GPCOM_DATA0 2501*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT 0x0 2502*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 2503*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_GPCOM_DATA1 2504*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT 0x0 2505*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 2506*b77a9fdfSHawking Zhang //UVD_JPEG_TBL_DAT0 2507*b77a9fdfSHawking Zhang #define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0__SHIFT 0x0 2508*b77a9fdfSHawking Zhang #define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0_MASK 0xFFFFFFFFL 2509*b77a9fdfSHawking Zhang //UVD_JPEG_TBL_DAT1 2510*b77a9fdfSHawking Zhang #define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32__SHIFT 0x0 2511*b77a9fdfSHawking Zhang #define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32_MASK 0xFFFFFFFFL 2512*b77a9fdfSHawking Zhang //UVD_JPEG_TBL_IDX 2513*b77a9fdfSHawking Zhang #define UVD_JPEG_TBL_IDX__TBL_IDX__SHIFT 0x0 2514*b77a9fdfSHawking Zhang #define UVD_JPEG_TBL_IDX__TBL_IDX_MASK 0x000000FFL 2515*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_CGC_CNTL 2516*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT 0x0 2517*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK 0x00000001L 2518*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_SCRATCH0 2519*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 2520*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 2521*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_SOFT_RST 2522*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT 0x0 2523*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT 0x10 2524*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK 0x00000001L 2525*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 2526*b77a9fdfSHawking Zhang 2527*b77a9fdfSHawking Zhang 2528*b77a9fdfSHawking Zhang // addressBlock: uvd0_uvd_jrbc_dec 2529*b77a9fdfSHawking Zhang //UVD_JRBC_RB_WPTR 2530*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 2531*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 2532*b77a9fdfSHawking Zhang //UVD_JRBC_RB_CNTL 2533*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 2534*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 2535*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 2536*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 2537*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 2538*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 2539*b77a9fdfSHawking Zhang //UVD_JRBC_IB_SIZE 2540*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 2541*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 2542*b77a9fdfSHawking Zhang //UVD_JRBC_URGENT_CNTL 2543*b77a9fdfSHawking Zhang #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 2544*b77a9fdfSHawking Zhang #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 2545*b77a9fdfSHawking Zhang //UVD_JRBC_RB_REF_DATA 2546*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 2547*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 2548*b77a9fdfSHawking Zhang //UVD_JRBC_RB_COND_RD_TIMER 2549*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 2550*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 2551*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 2552*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 2553*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 2554*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 2555*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 2556*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 2557*b77a9fdfSHawking Zhang //UVD_JRBC_SOFT_RESET 2558*b77a9fdfSHawking Zhang #define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 2559*b77a9fdfSHawking Zhang #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 2560*b77a9fdfSHawking Zhang #define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 2561*b77a9fdfSHawking Zhang #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 2562*b77a9fdfSHawking Zhang //UVD_JRBC_STATUS 2563*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 2564*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 2565*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 2566*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 2567*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 2568*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 2569*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 2570*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 2571*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 2572*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 2573*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 2574*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 2575*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 2576*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 2577*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 2578*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 2579*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 2580*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 2581*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 2582*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 2583*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 2584*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 2585*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 2586*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 2587*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 2588*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 2589*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 2590*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 2591*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 2592*b77a9fdfSHawking Zhang #define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 2593*b77a9fdfSHawking Zhang //UVD_JRBC_RB_RPTR 2594*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 2595*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 2596*b77a9fdfSHawking Zhang //UVD_JRBC_RB_BUF_STATUS 2597*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 2598*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 2599*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 2600*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 2601*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 2602*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 2603*b77a9fdfSHawking Zhang //UVD_JRBC_IB_BUF_STATUS 2604*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 2605*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 2606*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 2607*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 2608*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 2609*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 2610*b77a9fdfSHawking Zhang //UVD_JRBC_IB_SIZE_UPDATE 2611*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 2612*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 2613*b77a9fdfSHawking Zhang //UVD_JRBC_IB_COND_RD_TIMER 2614*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 2615*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 2616*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 2617*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 2618*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 2619*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 2620*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 2621*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 2622*b77a9fdfSHawking Zhang //UVD_JRBC_IB_REF_DATA 2623*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 2624*b77a9fdfSHawking Zhang #define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 2625*b77a9fdfSHawking Zhang //UVD_JPEG_PREEMPT_CMD 2626*b77a9fdfSHawking Zhang #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 2627*b77a9fdfSHawking Zhang #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 2628*b77a9fdfSHawking Zhang #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 2629*b77a9fdfSHawking Zhang #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 2630*b77a9fdfSHawking Zhang #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 2631*b77a9fdfSHawking Zhang #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 2632*b77a9fdfSHawking Zhang //UVD_JPEG_PREEMPT_FENCE_DATA0 2633*b77a9fdfSHawking Zhang #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 2634*b77a9fdfSHawking Zhang #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 2635*b77a9fdfSHawking Zhang //UVD_JPEG_PREEMPT_FENCE_DATA1 2636*b77a9fdfSHawking Zhang #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 2637*b77a9fdfSHawking Zhang #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 2638*b77a9fdfSHawking Zhang //UVD_JRBC_RB_SIZE 2639*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 2640*b77a9fdfSHawking Zhang #define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 2641*b77a9fdfSHawking Zhang //UVD_JRBC_SCRATCH0 2642*b77a9fdfSHawking Zhang #define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 2643*b77a9fdfSHawking Zhang #define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 2644*b77a9fdfSHawking Zhang 2645*b77a9fdfSHawking Zhang 2646*b77a9fdfSHawking Zhang // addressBlock: uvd0_uvd_jrbc_enc_dec 2647*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_RB_WPTR 2648*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT 0x4 2649*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 2650*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_RB_CNTL 2651*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 2652*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 2653*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 2654*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 2655*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 2656*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 2657*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_IB_SIZE 2658*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT 0x4 2659*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 2660*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_URGENT_CNTL 2661*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 2662*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 2663*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_RB_REF_DATA 2664*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT 0x0 2665*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 2666*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_RB_COND_RD_TIMER 2667*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 2668*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 2669*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 2670*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 2671*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 2672*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 2673*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 2674*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 2675*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_SOFT_RESET 2676*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT 0x0 2677*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 2678*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_SOFT_RESET__RESET_MASK 0x00000001L 2679*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 2680*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_STATUS 2681*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT 0x0 2682*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT 0x1 2683*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 2684*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 2685*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 2686*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 2687*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 2688*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 2689*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 2690*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 2691*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 2692*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT 0xb 2693*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 2694*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__INT_EN__SHIFT 0x10 2695*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT 0x11 2696*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK 0x00000001L 2697*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK 0x00000002L 2698*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 2699*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 2700*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 2701*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 2702*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 2703*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 2704*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 2705*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 2706*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 2707*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 2708*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 2709*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__INT_EN_MASK 0x00010000L 2710*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_STATUS__INT_ACK_MASK 0x00020000L 2711*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_RB_RPTR 2712*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT 0x4 2713*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 2714*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_RB_BUF_STATUS 2715*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 2716*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 2717*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 2718*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 2719*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 2720*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 2721*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_IB_BUF_STATUS 2722*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 2723*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 2724*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 2725*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 2726*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 2727*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 2728*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_IB_SIZE_UPDATE 2729*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 2730*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 2731*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_IB_COND_RD_TIMER 2732*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 2733*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 2734*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 2735*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 2736*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 2737*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 2738*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 2739*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 2740*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_IB_REF_DATA 2741*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT 0x0 2742*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 2743*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_PREEMPT_CMD 2744*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 2745*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 2746*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 2747*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 2748*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 2749*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 2750*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_PREEMPT_FENCE_DATA0 2751*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 2752*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 2753*b77a9fdfSHawking Zhang //UVD_JPEG_ENC_PREEMPT_FENCE_DATA1 2754*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 2755*b77a9fdfSHawking Zhang #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 2756*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_RB_SIZE 2757*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT 0x4 2758*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 2759*b77a9fdfSHawking Zhang //UVD_JRBC_ENC_SCRATCH0 2760*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 2761*b77a9fdfSHawking Zhang #define UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 2762*b77a9fdfSHawking Zhang 2763*b77a9fdfSHawking Zhang 2764*b77a9fdfSHawking Zhang // addressBlock: uvd0_uvd_mpcdec 2765*b77a9fdfSHawking Zhang //UVD_MP_SWAP_CNTL 2766*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 2767*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 2768*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 2769*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 2770*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 2771*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 2772*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 2773*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 2774*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 2775*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 2776*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 2777*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 2778*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 2779*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 2780*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 2781*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 2782*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L 2783*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL 2784*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L 2785*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L 2786*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L 2787*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L 2788*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L 2789*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L 2790*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L 2791*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L 2792*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L 2793*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L 2794*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L 2795*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L 2796*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L 2797*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L 2798*b77a9fdfSHawking Zhang //UVD_MP_SWAP_CNTL2 2799*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP__SHIFT 0x0 2800*b77a9fdfSHawking Zhang #define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP_MASK 0x00000003L 2801*b77a9fdfSHawking Zhang //UVD_MPC_LUMA_SRCH 2802*b77a9fdfSHawking Zhang #define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0 2803*b77a9fdfSHawking Zhang #define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL 2804*b77a9fdfSHawking Zhang //UVD_MPC_LUMA_HIT 2805*b77a9fdfSHawking Zhang #define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0 2806*b77a9fdfSHawking Zhang #define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL 2807*b77a9fdfSHawking Zhang //UVD_MPC_LUMA_HITPEND 2808*b77a9fdfSHawking Zhang #define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0 2809*b77a9fdfSHawking Zhang #define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 2810*b77a9fdfSHawking Zhang //UVD_MPC_CHROMA_SRCH 2811*b77a9fdfSHawking Zhang #define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0 2812*b77a9fdfSHawking Zhang #define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL 2813*b77a9fdfSHawking Zhang //UVD_MPC_CHROMA_HIT 2814*b77a9fdfSHawking Zhang #define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0 2815*b77a9fdfSHawking Zhang #define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL 2816*b77a9fdfSHawking Zhang //UVD_MPC_CHROMA_HITPEND 2817*b77a9fdfSHawking Zhang #define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0 2818*b77a9fdfSHawking Zhang #define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 2819*b77a9fdfSHawking Zhang //UVD_MPC_CNTL 2820*b77a9fdfSHawking Zhang #define UVD_MPC_CNTL__BLK_RST__SHIFT 0x0 2821*b77a9fdfSHawking Zhang #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 2822*b77a9fdfSHawking Zhang #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 2823*b77a9fdfSHawking Zhang #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 2824*b77a9fdfSHawking Zhang #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 2825*b77a9fdfSHawking Zhang #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13 2826*b77a9fdfSHawking Zhang #define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14 2827*b77a9fdfSHawking Zhang #define UVD_MPC_CNTL__BLK_RST_MASK 0x00000001L 2828*b77a9fdfSHawking Zhang #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L 2829*b77a9fdfSHawking Zhang #define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L 2830*b77a9fdfSHawking Zhang #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L 2831*b77a9fdfSHawking Zhang #define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L 2832*b77a9fdfSHawking Zhang #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L 2833*b77a9fdfSHawking Zhang #define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00100000L 2834*b77a9fdfSHawking Zhang //UVD_MPC_PITCH 2835*b77a9fdfSHawking Zhang #define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0 2836*b77a9fdfSHawking Zhang #define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL 2837*b77a9fdfSHawking Zhang //UVD_MPC_SET_MUXA0 2838*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 2839*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 2840*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 2841*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 2842*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 2843*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL 2844*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L 2845*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L 2846*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L 2847*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L 2848*b77a9fdfSHawking Zhang //UVD_MPC_SET_MUXA1 2849*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 2850*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 2851*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 2852*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL 2853*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L 2854*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L 2855*b77a9fdfSHawking Zhang //UVD_MPC_SET_MUXB0 2856*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 2857*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 2858*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 2859*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 2860*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 2861*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL 2862*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L 2863*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L 2864*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L 2865*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L 2866*b77a9fdfSHawking Zhang //UVD_MPC_SET_MUXB1 2867*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 2868*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 2869*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 2870*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL 2871*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L 2872*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L 2873*b77a9fdfSHawking Zhang //UVD_MPC_SET_MUX 2874*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 2875*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 2876*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 2877*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L 2878*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L 2879*b77a9fdfSHawking Zhang #define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L 2880*b77a9fdfSHawking Zhang //UVD_MPC_SET_ALU 2881*b77a9fdfSHawking Zhang #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 2882*b77a9fdfSHawking Zhang #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 2883*b77a9fdfSHawking Zhang #define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L 2884*b77a9fdfSHawking Zhang #define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L 2885*b77a9fdfSHawking Zhang //UVD_MPC_PERF0 2886*b77a9fdfSHawking Zhang #define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0 2887*b77a9fdfSHawking Zhang #define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL 2888*b77a9fdfSHawking Zhang //UVD_MPC_PERF1 2889*b77a9fdfSHawking Zhang #define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0 2890*b77a9fdfSHawking Zhang #define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL 2891*b77a9fdfSHawking Zhang //UVD_MPC_IND_INDEX 2892*b77a9fdfSHawking Zhang #define UVD_MPC_IND_INDEX__INDEX__SHIFT 0x0 2893*b77a9fdfSHawking Zhang #define UVD_MPC_IND_INDEX__INDEX_MASK 0x000001FFL 2894*b77a9fdfSHawking Zhang //UVD_MPC_IND_DATA 2895*b77a9fdfSHawking Zhang #define UVD_MPC_IND_DATA__DATA__SHIFT 0x0 2896*b77a9fdfSHawking Zhang #define UVD_MPC_IND_DATA__DATA_MASK 0xFFFFFFFFL 2897*b77a9fdfSHawking Zhang 2898*b77a9fdfSHawking Zhang 2899*b77a9fdfSHawking Zhang // addressBlock: uvd0_uvd_pg_dec 2900*b77a9fdfSHawking Zhang //UVD_PGFSM_CONFIG 2901*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 2902*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2 2903*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4 2904*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6 2905*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8 2906*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 0xa 2907*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 0xc 2908*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe 2909*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10 2910*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12 2911*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT 0x14 2912*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16 2913*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L 2914*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL 2915*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L 2916*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L 2917*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L 2918*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK 0x00000C00L 2919*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK 0x00003000L 2920*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L 2921*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L 2922*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L 2923*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK 0x00300000L 2924*b77a9fdfSHawking Zhang #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L 2925*b77a9fdfSHawking Zhang //UVD_PGFSM_STATUS 2926*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0 2927*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2 2928*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4 2929*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6 2930*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8 2931*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 0xa 2932*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 0xc 2933*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe 2934*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10 2935*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12 2936*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14 2937*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16 2938*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L 2939*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL 2940*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L 2941*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L 2942*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L 2943*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK 0x00000C00L 2944*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK 0x00003000L 2945*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L 2946*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L 2947*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L 2948*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK 0x00300000L 2949*b77a9fdfSHawking Zhang #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L 2950*b77a9fdfSHawking Zhang //UVD_POWER_STATUS 2951*b77a9fdfSHawking Zhang #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 2952*b77a9fdfSHawking Zhang #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 2953*b77a9fdfSHawking Zhang #define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 2954*b77a9fdfSHawking Zhang #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 2955*b77a9fdfSHawking Zhang #define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 2956*b77a9fdfSHawking Zhang #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb 2957*b77a9fdfSHawking Zhang #define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f 2958*b77a9fdfSHawking Zhang #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L 2959*b77a9fdfSHawking Zhang #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L 2960*b77a9fdfSHawking Zhang #define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L 2961*b77a9fdfSHawking Zhang #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L 2962*b77a9fdfSHawking Zhang #define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L 2963*b77a9fdfSHawking Zhang #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L 2964*b77a9fdfSHawking Zhang #define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L 2965*b77a9fdfSHawking Zhang //UVD_PG_IND_INDEX 2966*b77a9fdfSHawking Zhang #define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0 2967*b77a9fdfSHawking Zhang #define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL 2968*b77a9fdfSHawking Zhang //UVD_PG_IND_DATA 2969*b77a9fdfSHawking Zhang #define UVD_PG_IND_DATA__DATA__SHIFT 0x0 2970*b77a9fdfSHawking Zhang #define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL 2971*b77a9fdfSHawking Zhang //CC_UVD_HARVESTING 2972*b77a9fdfSHawking Zhang #define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0 2973*b77a9fdfSHawking Zhang #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 2974*b77a9fdfSHawking Zhang #define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L 2975*b77a9fdfSHawking Zhang #define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 2976*b77a9fdfSHawking Zhang //UVD_JPEG_POWER_STATUS 2977*b77a9fdfSHawking Zhang #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0 2978*b77a9fdfSHawking Zhang #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4 2979*b77a9fdfSHawking Zhang #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8 2980*b77a9fdfSHawking Zhang #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9 2981*b77a9fdfSHawking Zhang #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f 2982*b77a9fdfSHawking Zhang #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L 2983*b77a9fdfSHawking Zhang #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L 2984*b77a9fdfSHawking Zhang #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L 2985*b77a9fdfSHawking Zhang #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L 2986*b77a9fdfSHawking Zhang #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L 2987*b77a9fdfSHawking Zhang //UVD_DPG_LMA_CTL 2988*b77a9fdfSHawking Zhang #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 2989*b77a9fdfSHawking Zhang #define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 2990*b77a9fdfSHawking Zhang #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 2991*b77a9fdfSHawking Zhang #define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 2992*b77a9fdfSHawking Zhang #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 2993*b77a9fdfSHawking Zhang #define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L 2994*b77a9fdfSHawking Zhang #define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L 2995*b77a9fdfSHawking Zhang #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L 2996*b77a9fdfSHawking Zhang #define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L 2997*b77a9fdfSHawking Zhang #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L 2998*b77a9fdfSHawking Zhang //UVD_DPG_LMA_DATA 2999*b77a9fdfSHawking Zhang #define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0 3000*b77a9fdfSHawking Zhang #define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL 3001*b77a9fdfSHawking Zhang //UVD_DPG_LMA_MASK 3002*b77a9fdfSHawking Zhang #define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0 3003*b77a9fdfSHawking Zhang #define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL 3004*b77a9fdfSHawking Zhang //UVD_DPG_PAUSE 3005*b77a9fdfSHawking Zhang #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 3006*b77a9fdfSHawking Zhang #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 3007*b77a9fdfSHawking Zhang #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 3008*b77a9fdfSHawking Zhang #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 3009*b77a9fdfSHawking Zhang #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L 3010*b77a9fdfSHawking Zhang #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L 3011*b77a9fdfSHawking Zhang #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L 3012*b77a9fdfSHawking Zhang #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L 3013*b77a9fdfSHawking Zhang //UVD_SCRATCH1 3014*b77a9fdfSHawking Zhang #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 3015*b77a9fdfSHawking Zhang #define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL 3016*b77a9fdfSHawking Zhang //UVD_SCRATCH2 3017*b77a9fdfSHawking Zhang #define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 3018*b77a9fdfSHawking Zhang #define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL 3019*b77a9fdfSHawking Zhang //UVD_SCRATCH3 3020*b77a9fdfSHawking Zhang #define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 3021*b77a9fdfSHawking Zhang #define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL 3022*b77a9fdfSHawking Zhang //UVD_SCRATCH4 3023*b77a9fdfSHawking Zhang #define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 3024*b77a9fdfSHawking Zhang #define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL 3025*b77a9fdfSHawking Zhang //UVD_SCRATCH5 3026*b77a9fdfSHawking Zhang #define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 3027*b77a9fdfSHawking Zhang #define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL 3028*b77a9fdfSHawking Zhang //UVD_SCRATCH6 3029*b77a9fdfSHawking Zhang #define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 3030*b77a9fdfSHawking Zhang #define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL 3031*b77a9fdfSHawking Zhang //UVD_SCRATCH7 3032*b77a9fdfSHawking Zhang #define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 3033*b77a9fdfSHawking Zhang #define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL 3034*b77a9fdfSHawking Zhang //UVD_SCRATCH8 3035*b77a9fdfSHawking Zhang #define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 3036*b77a9fdfSHawking Zhang #define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL 3037*b77a9fdfSHawking Zhang //UVD_SCRATCH9 3038*b77a9fdfSHawking Zhang #define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 3039*b77a9fdfSHawking Zhang #define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL 3040*b77a9fdfSHawking Zhang //UVD_SCRATCH10 3041*b77a9fdfSHawking Zhang #define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 3042*b77a9fdfSHawking Zhang #define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL 3043*b77a9fdfSHawking Zhang //UVD_SCRATCH11 3044*b77a9fdfSHawking Zhang #define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 3045*b77a9fdfSHawking Zhang #define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL 3046*b77a9fdfSHawking Zhang //UVD_SCRATCH12 3047*b77a9fdfSHawking Zhang #define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 3048*b77a9fdfSHawking Zhang #define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL 3049*b77a9fdfSHawking Zhang //UVD_SCRATCH13 3050*b77a9fdfSHawking Zhang #define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 3051*b77a9fdfSHawking Zhang #define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL 3052*b77a9fdfSHawking Zhang //UVD_SCRATCH14 3053*b77a9fdfSHawking Zhang #define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 3054*b77a9fdfSHawking Zhang #define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL 3055*b77a9fdfSHawking Zhang //UVD_FREE_COUNTER_REG 3056*b77a9fdfSHawking Zhang #define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0 3057*b77a9fdfSHawking Zhang #define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL 3058*b77a9fdfSHawking Zhang //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 3059*b77a9fdfSHawking Zhang #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3060*b77a9fdfSHawking Zhang #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3061*b77a9fdfSHawking Zhang //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 3062*b77a9fdfSHawking Zhang #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3063*b77a9fdfSHawking Zhang #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3064*b77a9fdfSHawking Zhang //UVD_DPG_VCPU_CACHE_OFFSET0 3065*b77a9fdfSHawking Zhang #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 3066*b77a9fdfSHawking Zhang #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL 3067*b77a9fdfSHawking Zhang //UVD_DPG_LMI_VCPU_CACHE_VMID 3068*b77a9fdfSHawking Zhang #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 3069*b77a9fdfSHawking Zhang #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 3070*b77a9fdfSHawking Zhang //UVD_PF_STATUS 3071*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0 3072*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1 3073*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2 3074*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3 3075*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4 3076*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5 3077*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6 3078*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7 3079*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8 3080*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9 3081*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa 3082*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb 3083*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc 3084*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd 3085*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe 3086*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf 3087*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10 3088*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11 3089*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12 3090*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L 3091*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L 3092*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L 3093*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L 3094*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L 3095*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L 3096*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L 3097*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L 3098*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L 3099*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L 3100*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L 3101*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L 3102*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L 3103*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L 3104*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L 3105*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L 3106*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L 3107*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L 3108*b77a9fdfSHawking Zhang #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L 3109*b77a9fdfSHawking Zhang //UVD_FW_VERSION 3110*b77a9fdfSHawking Zhang #define UVD_FW_VERSION__FW_VERSION__SHIFT 0x0 3111*b77a9fdfSHawking Zhang #define UVD_FW_VERSION__FW_VERSION_MASK 0xFFFFFFFFL 3112*b77a9fdfSHawking Zhang //UVD_DPG_CLK_EN_VCPU_REPORT 3113*b77a9fdfSHawking Zhang #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0 3114*b77a9fdfSHawking Zhang #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1 3115*b77a9fdfSHawking Zhang #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L 3116*b77a9fdfSHawking Zhang #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL 3117*b77a9fdfSHawking Zhang //UVD_GFX8_ADDR_CONFIG 3118*b77a9fdfSHawking Zhang #define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 3119*b77a9fdfSHawking Zhang #define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 3120*b77a9fdfSHawking Zhang //UVD_GFX10_ADDR_CONFIG 3121*b77a9fdfSHawking Zhang #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 3122*b77a9fdfSHawking Zhang #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 3123*b77a9fdfSHawking Zhang #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 3124*b77a9fdfSHawking Zhang #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 3125*b77a9fdfSHawking Zhang #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 3126*b77a9fdfSHawking Zhang #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 3127*b77a9fdfSHawking Zhang #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 3128*b77a9fdfSHawking Zhang #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 3129*b77a9fdfSHawking Zhang //UVD_GPCNT2_CNTL 3130*b77a9fdfSHawking Zhang #define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0 3131*b77a9fdfSHawking Zhang #define UVD_GPCNT2_CNTL__START__SHIFT 0x1 3132*b77a9fdfSHawking Zhang #define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2 3133*b77a9fdfSHawking Zhang #define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L 3134*b77a9fdfSHawking Zhang #define UVD_GPCNT2_CNTL__START_MASK 0x00000002L 3135*b77a9fdfSHawking Zhang #define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L 3136*b77a9fdfSHawking Zhang //UVD_GPCNT2_TARGET_LOWER 3137*b77a9fdfSHawking Zhang #define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0 3138*b77a9fdfSHawking Zhang #define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 3139*b77a9fdfSHawking Zhang //UVD_GPCNT2_STATUS_LOWER 3140*b77a9fdfSHawking Zhang #define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0 3141*b77a9fdfSHawking Zhang #define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 3142*b77a9fdfSHawking Zhang //UVD_GPCNT2_TARGET_UPPER 3143*b77a9fdfSHawking Zhang #define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0 3144*b77a9fdfSHawking Zhang #define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 3145*b77a9fdfSHawking Zhang //UVD_GPCNT2_STATUS_UPPER 3146*b77a9fdfSHawking Zhang #define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0 3147*b77a9fdfSHawking Zhang #define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 3148*b77a9fdfSHawking Zhang //UVD_GPCNT3_CNTL 3149*b77a9fdfSHawking Zhang #define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0 3150*b77a9fdfSHawking Zhang #define UVD_GPCNT3_CNTL__START__SHIFT 0x1 3151*b77a9fdfSHawking Zhang #define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2 3152*b77a9fdfSHawking Zhang #define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3 3153*b77a9fdfSHawking Zhang #define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa 3154*b77a9fdfSHawking Zhang #define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L 3155*b77a9fdfSHawking Zhang #define UVD_GPCNT3_CNTL__START_MASK 0x00000002L 3156*b77a9fdfSHawking Zhang #define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L 3157*b77a9fdfSHawking Zhang #define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L 3158*b77a9fdfSHawking Zhang #define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L 3159*b77a9fdfSHawking Zhang //UVD_GPCNT3_TARGET_LOWER 3160*b77a9fdfSHawking Zhang #define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0 3161*b77a9fdfSHawking Zhang #define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 3162*b77a9fdfSHawking Zhang //UVD_GPCNT3_STATUS_LOWER 3163*b77a9fdfSHawking Zhang #define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0 3164*b77a9fdfSHawking Zhang #define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 3165*b77a9fdfSHawking Zhang //UVD_GPCNT3_TARGET_UPPER 3166*b77a9fdfSHawking Zhang #define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0 3167*b77a9fdfSHawking Zhang #define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 3168*b77a9fdfSHawking Zhang //UVD_GPCNT3_STATUS_UPPER 3169*b77a9fdfSHawking Zhang #define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0 3170*b77a9fdfSHawking Zhang #define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 3171*b77a9fdfSHawking Zhang //UVD_VCLK_DS_CNTL 3172*b77a9fdfSHawking Zhang #define UVD_VCLK_DS_CNTL__VCLK_DS_EN__SHIFT 0x0 3173*b77a9fdfSHawking Zhang #define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS__SHIFT 0x4 3174*b77a9fdfSHawking Zhang #define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 3175*b77a9fdfSHawking Zhang #define UVD_VCLK_DS_CNTL__VCLK_DS_EN_MASK 0x00000001L 3176*b77a9fdfSHawking Zhang #define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS_MASK 0x00000010L 3177*b77a9fdfSHawking Zhang #define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L 3178*b77a9fdfSHawking Zhang //UVD_DCLK_DS_CNTL 3179*b77a9fdfSHawking Zhang #define UVD_DCLK_DS_CNTL__DCLK_DS_EN__SHIFT 0x0 3180*b77a9fdfSHawking Zhang #define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS__SHIFT 0x4 3181*b77a9fdfSHawking Zhang #define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 3182*b77a9fdfSHawking Zhang #define UVD_DCLK_DS_CNTL__DCLK_DS_EN_MASK 0x00000001L 3183*b77a9fdfSHawking Zhang #define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS_MASK 0x00000010L 3184*b77a9fdfSHawking Zhang #define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L 3185*b77a9fdfSHawking Zhang //UVD_RAS_VCPU_VCODEC_STATUS 3186*b77a9fdfSHawking Zhang #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF__SHIFT 0x0 3187*b77a9fdfSHawking Zhang #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF__SHIFT 0x1f 3188*b77a9fdfSHawking Zhang #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF_MASK 0x7FFFFFFFL 3189*b77a9fdfSHawking Zhang #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF_MASK 0x80000000L 3190*b77a9fdfSHawking Zhang //UVD_RAS_MMSCH_FATAL_ERROR 3191*b77a9fdfSHawking Zhang #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF__SHIFT 0x0 3192*b77a9fdfSHawking Zhang #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF__SHIFT 0x1f 3193*b77a9fdfSHawking Zhang #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF_MASK 0x7FFFFFFFL 3194*b77a9fdfSHawking Zhang #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF_MASK 0x80000000L 3195*b77a9fdfSHawking Zhang //UVD_RAS_JPEG0_STATUS 3196*b77a9fdfSHawking Zhang #define UVD_RAS_JPEG0_STATUS__POISONED_VF__SHIFT 0x0 3197*b77a9fdfSHawking Zhang #define UVD_RAS_JPEG0_STATUS__POISONED_PF__SHIFT 0x1f 3198*b77a9fdfSHawking Zhang #define UVD_RAS_JPEG0_STATUS__POISONED_VF_MASK 0x7FFFFFFFL 3199*b77a9fdfSHawking Zhang #define UVD_RAS_JPEG0_STATUS__POISONED_PF_MASK 0x80000000L 3200*b77a9fdfSHawking Zhang //UVD_RAS_JPEG1_STATUS 3201*b77a9fdfSHawking Zhang #define UVD_RAS_JPEG1_STATUS__POISONED_VF__SHIFT 0x0 3202*b77a9fdfSHawking Zhang #define UVD_RAS_JPEG1_STATUS__POISONED_PF__SHIFT 0x1f 3203*b77a9fdfSHawking Zhang #define UVD_RAS_JPEG1_STATUS__POISONED_VF_MASK 0x7FFFFFFFL 3204*b77a9fdfSHawking Zhang #define UVD_RAS_JPEG1_STATUS__POISONED_PF_MASK 0x80000000L 3205*b77a9fdfSHawking Zhang //UVD_RAS_CNTL_PMI_ARB 3206*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__STAT_VCPU_VCODEC__SHIFT 0x0 3207*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__ACK_VCPU_VCODEC__SHIFT 0x1 3208*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__STAT_MMSCH__SHIFT 0x2 3209*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__ACK_MMSCH__SHIFT 0x3 3210*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG0__SHIFT 0x4 3211*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG0__SHIFT 0x5 3212*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG1__SHIFT 0x6 3213*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG1__SHIFT 0x7 3214*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__STAT_VCPU_VCODEC_MASK 0x00000001L 3215*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__ACK_VCPU_VCODEC_MASK 0x00000002L 3216*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__STAT_MMSCH_MASK 0x00000004L 3217*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__ACK_MMSCH_MASK 0x00000008L 3218*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG0_MASK 0x00000010L 3219*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG0_MASK 0x00000020L 3220*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG1_MASK 0x00000040L 3221*b77a9fdfSHawking Zhang #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG1_MASK 0x00000080L 3222*b77a9fdfSHawking Zhang 3223*b77a9fdfSHawking Zhang 3224*b77a9fdfSHawking Zhang // addressBlock: uvd0_uvd_rbcdec 3225*b77a9fdfSHawking Zhang //UVD_RBC_IB_SIZE 3226*b77a9fdfSHawking Zhang #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 3227*b77a9fdfSHawking Zhang #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 3228*b77a9fdfSHawking Zhang //UVD_RBC_IB_SIZE_UPDATE 3229*b77a9fdfSHawking Zhang #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 3230*b77a9fdfSHawking Zhang #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 3231*b77a9fdfSHawking Zhang //UVD_RBC_RB_CNTL 3232*b77a9fdfSHawking Zhang #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 3233*b77a9fdfSHawking Zhang #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 3234*b77a9fdfSHawking Zhang #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 3235*b77a9fdfSHawking Zhang #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 3236*b77a9fdfSHawking Zhang #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 3237*b77a9fdfSHawking Zhang #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 3238*b77a9fdfSHawking Zhang #define UVD_RBC_RB_CNTL__BLK_RST__SHIFT 0x1d 3239*b77a9fdfSHawking Zhang #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL 3240*b77a9fdfSHawking Zhang #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L 3241*b77a9fdfSHawking Zhang #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L 3242*b77a9fdfSHawking Zhang #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L 3243*b77a9fdfSHawking Zhang #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L 3244*b77a9fdfSHawking Zhang #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L 3245*b77a9fdfSHawking Zhang #define UVD_RBC_RB_CNTL__BLK_RST_MASK 0x20000000L 3246*b77a9fdfSHawking Zhang //UVD_RBC_RB_RPTR_ADDR 3247*b77a9fdfSHawking Zhang #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 3248*b77a9fdfSHawking Zhang #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL 3249*b77a9fdfSHawking Zhang //UVD_RBC_RB_RPTR 3250*b77a9fdfSHawking Zhang #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 3251*b77a9fdfSHawking Zhang #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 3252*b77a9fdfSHawking Zhang //UVD_RBC_RB_WPTR 3253*b77a9fdfSHawking Zhang #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 3254*b77a9fdfSHawking Zhang #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 3255*b77a9fdfSHawking Zhang //UVD_RBC_VCPU_ACCESS 3256*b77a9fdfSHawking Zhang #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0 3257*b77a9fdfSHawking Zhang #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L 3258*b77a9fdfSHawking Zhang //UVD_FW_SEMAPHORE_CNTL 3259*b77a9fdfSHawking Zhang #define UVD_FW_SEMAPHORE_CNTL__START__SHIFT 0x0 3260*b77a9fdfSHawking Zhang #define UVD_FW_SEMAPHORE_CNTL__BUSY__SHIFT 0x8 3261*b77a9fdfSHawking Zhang #define UVD_FW_SEMAPHORE_CNTL__PASS__SHIFT 0x9 3262*b77a9fdfSHawking Zhang #define UVD_FW_SEMAPHORE_CNTL__START_MASK 0x00000001L 3263*b77a9fdfSHawking Zhang #define UVD_FW_SEMAPHORE_CNTL__BUSY_MASK 0x00000100L 3264*b77a9fdfSHawking Zhang #define UVD_FW_SEMAPHORE_CNTL__PASS_MASK 0x00000200L 3265*b77a9fdfSHawking Zhang //UVD_RBC_READ_REQ_URGENT_CNTL 3266*b77a9fdfSHawking Zhang #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 3267*b77a9fdfSHawking Zhang #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 3268*b77a9fdfSHawking Zhang //UVD_RBC_RB_WPTR_CNTL 3269*b77a9fdfSHawking Zhang #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 3270*b77a9fdfSHawking Zhang #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL 3271*b77a9fdfSHawking Zhang //UVD_RBC_WPTR_STATUS 3272*b77a9fdfSHawking Zhang #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4 3273*b77a9fdfSHawking Zhang #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L 3274*b77a9fdfSHawking Zhang //UVD_RBC_WPTR_POLL_CNTL 3275*b77a9fdfSHawking Zhang #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0 3276*b77a9fdfSHawking Zhang #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 3277*b77a9fdfSHawking Zhang #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL 3278*b77a9fdfSHawking Zhang #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 3279*b77a9fdfSHawking Zhang //UVD_RBC_WPTR_POLL_ADDR 3280*b77a9fdfSHawking Zhang #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2 3281*b77a9fdfSHawking Zhang #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL 3282*b77a9fdfSHawking Zhang //UVD_SEMA_CMD 3283*b77a9fdfSHawking Zhang #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 3284*b77a9fdfSHawking Zhang #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 3285*b77a9fdfSHawking Zhang #define UVD_SEMA_CMD__MODE__SHIFT 0x6 3286*b77a9fdfSHawking Zhang #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 3287*b77a9fdfSHawking Zhang #define UVD_SEMA_CMD__VMID__SHIFT 0x8 3288*b77a9fdfSHawking Zhang #define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL 3289*b77a9fdfSHawking Zhang #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L 3290*b77a9fdfSHawking Zhang #define UVD_SEMA_CMD__MODE_MASK 0x00000040L 3291*b77a9fdfSHawking Zhang #define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L 3292*b77a9fdfSHawking Zhang #define UVD_SEMA_CMD__VMID_MASK 0x00000F00L 3293*b77a9fdfSHawking Zhang //UVD_SEMA_ADDR_LOW 3294*b77a9fdfSHawking Zhang #define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0 3295*b77a9fdfSHawking Zhang #define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL 3296*b77a9fdfSHawking Zhang //UVD_SEMA_ADDR_HIGH 3297*b77a9fdfSHawking Zhang #define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0 3298*b77a9fdfSHawking Zhang #define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL 3299*b77a9fdfSHawking Zhang //UVD_ENGINE_CNTL 3300*b77a9fdfSHawking Zhang #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 3301*b77a9fdfSHawking Zhang #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 3302*b77a9fdfSHawking Zhang #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2 3303*b77a9fdfSHawking Zhang #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L 3304*b77a9fdfSHawking Zhang #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L 3305*b77a9fdfSHawking Zhang #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L 3306*b77a9fdfSHawking Zhang //UVD_SEMA_TIMEOUT_STATUS 3307*b77a9fdfSHawking Zhang #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 3308*b77a9fdfSHawking Zhang #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 3309*b77a9fdfSHawking Zhang #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 3310*b77a9fdfSHawking Zhang #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 3311*b77a9fdfSHawking Zhang #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L 3312*b77a9fdfSHawking Zhang #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L 3313*b77a9fdfSHawking Zhang #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L 3314*b77a9fdfSHawking Zhang #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L 3315*b77a9fdfSHawking Zhang //UVD_SEMA_CNTL 3316*b77a9fdfSHawking Zhang #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 3317*b77a9fdfSHawking Zhang #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 3318*b77a9fdfSHawking Zhang #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L 3319*b77a9fdfSHawking Zhang #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L 3320*b77a9fdfSHawking Zhang //UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 3321*b77a9fdfSHawking Zhang #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 3322*b77a9fdfSHawking Zhang #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 3323*b77a9fdfSHawking Zhang #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 3324*b77a9fdfSHawking Zhang #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L 3325*b77a9fdfSHawking Zhang #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL 3326*b77a9fdfSHawking Zhang #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 3327*b77a9fdfSHawking Zhang //UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 3328*b77a9fdfSHawking Zhang #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 3329*b77a9fdfSHawking Zhang #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 3330*b77a9fdfSHawking Zhang #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 3331*b77a9fdfSHawking Zhang #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L 3332*b77a9fdfSHawking Zhang #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL 3333*b77a9fdfSHawking Zhang #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 3334*b77a9fdfSHawking Zhang //UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 3335*b77a9fdfSHawking Zhang #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 3336*b77a9fdfSHawking Zhang #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 3337*b77a9fdfSHawking Zhang #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 3338*b77a9fdfSHawking Zhang #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L 3339*b77a9fdfSHawking Zhang #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL 3340*b77a9fdfSHawking Zhang #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 3341*b77a9fdfSHawking Zhang //UVD_JOB_START 3342*b77a9fdfSHawking Zhang #define UVD_JOB_START__JOB_START__SHIFT 0x0 3343*b77a9fdfSHawking Zhang #define UVD_JOB_START__JOB_START_MASK 0x00000001L 3344*b77a9fdfSHawking Zhang //UVD_RBC_BUF_STATUS 3345*b77a9fdfSHawking Zhang #define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 3346*b77a9fdfSHawking Zhang #define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8 3347*b77a9fdfSHawking Zhang #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 3348*b77a9fdfSHawking Zhang #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13 3349*b77a9fdfSHawking Zhang #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16 3350*b77a9fdfSHawking Zhang #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19 3351*b77a9fdfSHawking Zhang #define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL 3352*b77a9fdfSHawking Zhang #define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L 3353*b77a9fdfSHawking Zhang #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L 3354*b77a9fdfSHawking Zhang #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L 3355*b77a9fdfSHawking Zhang #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L 3356*b77a9fdfSHawking Zhang #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L 3357*b77a9fdfSHawking Zhang //UVD_RBC_SWAP_CNTL 3358*b77a9fdfSHawking Zhang #define UVD_RBC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 3359*b77a9fdfSHawking Zhang #define UVD_RBC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 3360*b77a9fdfSHawking Zhang #define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 3361*b77a9fdfSHawking Zhang #define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 3362*b77a9fdfSHawking Zhang #define UVD_RBC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 3363*b77a9fdfSHawking Zhang #define UVD_RBC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 3364*b77a9fdfSHawking Zhang #define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L 3365*b77a9fdfSHawking Zhang #define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L 3366*b77a9fdfSHawking Zhang 3367*b77a9fdfSHawking Zhang 3368*b77a9fdfSHawking Zhang // addressBlock: uvd0_uvddec 3369*b77a9fdfSHawking Zhang //UVD_STATUS 3370*b77a9fdfSHawking Zhang #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 3371*b77a9fdfSHawking Zhang #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 3372*b77a9fdfSHawking Zhang #define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 3373*b77a9fdfSHawking Zhang #define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f 3374*b77a9fdfSHawking Zhang #define UVD_STATUS__RBC_BUSY_MASK 0x00000001L 3375*b77a9fdfSHawking Zhang #define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL 3376*b77a9fdfSHawking Zhang #define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L 3377*b77a9fdfSHawking Zhang #define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L 3378*b77a9fdfSHawking Zhang //UVD_ENC_PIPE_BUSY 3379*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 3380*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 3381*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 3382*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 3383*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 3384*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 3385*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 3386*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 3387*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 3388*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa 3389*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 3390*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 3391*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 3392*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 3393*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 3394*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 3395*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 3396*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 3397*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 3398*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 3399*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a 3400*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b 3401*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c 3402*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d 3403*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e 3404*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L 3405*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L 3406*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L 3407*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L 3408*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L 3409*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L 3410*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L 3411*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L 3412*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L 3413*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L 3414*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L 3415*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L 3416*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L 3417*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L 3418*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L 3419*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L 3420*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L 3421*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L 3422*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L 3423*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L 3424*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L 3425*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L 3426*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L 3427*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L 3428*b77a9fdfSHawking Zhang #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L 3429*b77a9fdfSHawking Zhang //UVD_FW_POWER_STATUS 3430*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDF_PWR_OFF__SHIFT 0x0 3431*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDC_PWR_OFF__SHIFT 0x1 3432*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDB_PWR_OFF__SHIFT 0x2 3433*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDIL_PWR_OFF__SHIFT 0x3 3434*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDIR_PWR_OFF__SHIFT 0x4 3435*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF__SHIFT 0x5 3436*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF__SHIFT 0x6 3437*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDE_PWR_OFF__SHIFT 0x7 3438*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDW_PWR_OFF__SHIFT 0x8 3439*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDF_PWR_OFF_MASK 0x00000001L 3440*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDC_PWR_OFF_MASK 0x00000002L 3441*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDB_PWR_OFF_MASK 0x00000004L 3442*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDIL_PWR_OFF_MASK 0x00000008L 3443*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDIR_PWR_OFF_MASK 0x00000010L 3444*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF_MASK 0x00000020L 3445*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF_MASK 0x00000040L 3446*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDE_PWR_OFF_MASK 0x00000080L 3447*b77a9fdfSHawking Zhang #define UVD_FW_POWER_STATUS__UVDW_PWR_OFF_MASK 0x00000100L 3448*b77a9fdfSHawking Zhang //UVD_CNTL 3449*b77a9fdfSHawking Zhang #define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 3450*b77a9fdfSHawking Zhang #define UVD_CNTL__SUVD_EN__SHIFT 0x13 3451*b77a9fdfSHawking Zhang #define UVD_CNTL__CABAC_MB_ACC__SHIFT 0x1c 3452*b77a9fdfSHawking Zhang #define UVD_CNTL__LRBBM_SAFE_SYNC_DIS__SHIFT 0x1f 3453*b77a9fdfSHawking Zhang #define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L 3454*b77a9fdfSHawking Zhang #define UVD_CNTL__SUVD_EN_MASK 0x00080000L 3455*b77a9fdfSHawking Zhang #define UVD_CNTL__CABAC_MB_ACC_MASK 0x10000000L 3456*b77a9fdfSHawking Zhang #define UVD_CNTL__LRBBM_SAFE_SYNC_DIS_MASK 0x80000000L 3457*b77a9fdfSHawking Zhang //UVD_SOFT_RESET 3458*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 3459*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 3460*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 3461*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 3462*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 3463*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 3464*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 3465*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 3466*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9 3467*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 3468*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 3469*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 3470*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 3471*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 3472*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 3473*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 3474*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 3475*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 3476*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 3477*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 3478*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 3479*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 3480*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 3481*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 3482*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 3483*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 3484*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 3485*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 3486*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 3487*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 3488*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 3489*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L 3490*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L 3491*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L 3492*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L 3493*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L 3494*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L 3495*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L 3496*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L 3497*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L 3498*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L 3499*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L 3500*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L 3501*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L 3502*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L 3503*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L 3504*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L 3505*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L 3506*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L 3507*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L 3508*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L 3509*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L 3510*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L 3511*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L 3512*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L 3513*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L 3514*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L 3515*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L 3516*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L 3517*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L 3518*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L 3519*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L 3520*b77a9fdfSHawking Zhang //UVD_SOFT_RESET2 3521*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 3522*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10 3523*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11 3524*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 3525*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L 3526*b77a9fdfSHawking Zhang #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L 3527*b77a9fdfSHawking Zhang //UVD_MMSCH_SOFT_RESET 3528*b77a9fdfSHawking Zhang #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0 3529*b77a9fdfSHawking Zhang #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1 3530*b77a9fdfSHawking Zhang #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f 3531*b77a9fdfSHawking Zhang #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L 3532*b77a9fdfSHawking Zhang #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L 3533*b77a9fdfSHawking Zhang #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L 3534*b77a9fdfSHawking Zhang //UVD_WIG_CTRL 3535*b77a9fdfSHawking Zhang #define UVD_WIG_CTRL__AVM_SOFT_RESET__SHIFT 0x0 3536*b77a9fdfSHawking Zhang #define UVD_WIG_CTRL__ACAP_SOFT_RESET__SHIFT 0x1 3537*b77a9fdfSHawking Zhang #define UVD_WIG_CTRL__WIG_SOFT_RESET__SHIFT 0x2 3538*b77a9fdfSHawking Zhang #define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON__SHIFT 0x3 3539*b77a9fdfSHawking Zhang #define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON__SHIFT 0x4 3540*b77a9fdfSHawking Zhang #define UVD_WIG_CTRL__AVM_SOFT_RESET_MASK 0x00000001L 3541*b77a9fdfSHawking Zhang #define UVD_WIG_CTRL__ACAP_SOFT_RESET_MASK 0x00000002L 3542*b77a9fdfSHawking Zhang #define UVD_WIG_CTRL__WIG_SOFT_RESET_MASK 0x00000004L 3543*b77a9fdfSHawking Zhang #define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON_MASK 0x00000008L 3544*b77a9fdfSHawking Zhang #define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON_MASK 0x00000010L 3545*b77a9fdfSHawking Zhang //UVD_CGC_GATE 3546*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__SYS__SHIFT 0x0 3547*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__UDEC__SHIFT 0x1 3548*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 3549*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__REGS__SHIFT 0x3 3550*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__RBC__SHIFT 0x4 3551*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 3552*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 3553*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__IDCT__SHIFT 0x7 3554*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__MPRD__SHIFT 0x8 3555*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__MPC__SHIFT 0x9 3556*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__LBSI__SHIFT 0xa 3557*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 3558*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 3559*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 3560*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 3561*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 3562*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 3563*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__WCB__SHIFT 0x11 3564*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__VCPU__SHIFT 0x12 3565*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__MMSCH__SHIFT 0x14 3566*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__SYS_MASK 0x00000001L 3567*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__UDEC_MASK 0x00000002L 3568*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__MPEG2_MASK 0x00000004L 3569*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__REGS_MASK 0x00000008L 3570*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__RBC_MASK 0x00000010L 3571*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L 3572*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L 3573*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__IDCT_MASK 0x00000080L 3574*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__MPRD_MASK 0x00000100L 3575*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__MPC_MASK 0x00000200L 3576*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__LBSI_MASK 0x00000400L 3577*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__LRBBM_MASK 0x00000800L 3578*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L 3579*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L 3580*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L 3581*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L 3582*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L 3583*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__WCB_MASK 0x00020000L 3584*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__VCPU_MASK 0x00040000L 3585*b77a9fdfSHawking Zhang #define UVD_CGC_GATE__MMSCH_MASK 0x00100000L 3586*b77a9fdfSHawking Zhang //UVD_CGC_STATUS 3587*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 3588*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 3589*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 3590*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 3591*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 3592*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 3593*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 3594*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 3595*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 3596*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 3597*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 3598*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 3599*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 3600*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 3601*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 3602*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 3603*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 3604*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 3605*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 3606*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 3607*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 3608*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 3609*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 3610*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 3611*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 3612*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 3613*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 3614*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b 3615*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c 3616*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d 3617*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 3618*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L 3619*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L 3620*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L 3621*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L 3622*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L 3623*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L 3624*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L 3625*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L 3626*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L 3627*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L 3628*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L 3629*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L 3630*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L 3631*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L 3632*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L 3633*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L 3634*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L 3635*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L 3636*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L 3637*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L 3638*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L 3639*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L 3640*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L 3641*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L 3642*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L 3643*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L 3644*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L 3645*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L 3646*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L 3647*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L 3648*b77a9fdfSHawking Zhang #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L 3649*b77a9fdfSHawking Zhang //UVD_CGC_CTRL 3650*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 3651*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 3652*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 3653*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 3654*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 3655*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 3656*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 3657*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 3658*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 3659*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 3660*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 3661*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 3662*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 3663*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 3664*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 3665*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 3666*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 3667*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 3668*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 3669*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 3670*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 3671*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 3672*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f 3673*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 3674*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 3675*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L 3676*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L 3677*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L 3678*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L 3679*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L 3680*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L 3681*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L 3682*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L 3683*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L 3684*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L 3685*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L 3686*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L 3687*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L 3688*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L 3689*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L 3690*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L 3691*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L 3692*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L 3693*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L 3694*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L 3695*b77a9fdfSHawking Zhang #define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L 3696*b77a9fdfSHawking Zhang //UVD_CGC_UDEC_STATUS 3697*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 3698*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 3699*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 3700*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 3701*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 3702*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 3703*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 3704*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 3705*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 3706*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 3707*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 3708*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 3709*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 3710*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 3711*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 3712*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L 3713*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L 3714*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L 3715*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L 3716*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L 3717*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L 3718*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L 3719*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L 3720*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L 3721*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L 3722*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L 3723*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L 3724*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L 3725*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L 3726*b77a9fdfSHawking Zhang #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L 3727*b77a9fdfSHawking Zhang //UVD_SUVD_CGC_GATE 3728*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 3729*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 3730*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 3731*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 3732*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 3733*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 3734*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 3735*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 3736*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 3737*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 3738*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 3739*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 3740*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 3741*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 3742*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 3743*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf 3744*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 3745*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 3746*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 3747*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 3748*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 3749*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 3750*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 3751*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 3752*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 3753*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 3754*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L 3755*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L 3756*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L 3757*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L 3758*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L 3759*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 3760*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 3761*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 3762*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 3763*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 3764*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 3765*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 3766*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 3767*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 3768*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 3769*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L 3770*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L 3771*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 3772*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 3773*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L 3774*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 3775*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 3776*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 3777*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 3778*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 3779*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L 3780*b77a9fdfSHawking Zhang //UVD_SUVD_CGC_STATUS 3781*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 3782*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 3783*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 3784*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 3785*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 3786*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 3787*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 3788*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 3789*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 3790*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 3791*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 3792*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 3793*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 3794*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 3795*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe 3796*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf 3797*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 3798*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 3799*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 3800*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 3801*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 3802*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 3803*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 3804*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 3805*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 3806*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 3807*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a 3808*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b 3809*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c 3810*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L 3811*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L 3812*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L 3813*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L 3814*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L 3815*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L 3816*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L 3817*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L 3818*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L 3819*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L 3820*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L 3821*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L 3822*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L 3823*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L 3824*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L 3825*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L 3826*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L 3827*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L 3828*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L 3829*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L 3830*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L 3831*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L 3832*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L 3833*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L 3834*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L 3835*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L 3836*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L 3837*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L 3838*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L 3839*b77a9fdfSHawking Zhang //UVD_SUVD_CGC_CTRL 3840*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 3841*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 3842*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 3843*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 3844*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 3845*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 3846*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 3847*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 3848*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 3849*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 3850*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 3851*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 3852*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 3853*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 3854*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 3855*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 3856*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 3857*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 3858*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 3859*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 3860*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 3861*b77a9fdfSHawking Zhang #define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 3862*b77a9fdfSHawking Zhang //UVD_GPCOM_VCPU_CMD 3863*b77a9fdfSHawking Zhang #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 3864*b77a9fdfSHawking Zhang #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 3865*b77a9fdfSHawking Zhang #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 3866*b77a9fdfSHawking Zhang #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L 3867*b77a9fdfSHawking Zhang #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL 3868*b77a9fdfSHawking Zhang #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L 3869*b77a9fdfSHawking Zhang //UVD_GPCOM_VCPU_DATA0 3870*b77a9fdfSHawking Zhang #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 3871*b77a9fdfSHawking Zhang #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL 3872*b77a9fdfSHawking Zhang //UVD_GPCOM_VCPU_DATA1 3873*b77a9fdfSHawking Zhang #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 3874*b77a9fdfSHawking Zhang #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL 3875*b77a9fdfSHawking Zhang //UVD_GPCOM_SYS_CMD 3876*b77a9fdfSHawking Zhang #define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 3877*b77a9fdfSHawking Zhang #define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 3878*b77a9fdfSHawking Zhang #define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f 3879*b77a9fdfSHawking Zhang #define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L 3880*b77a9fdfSHawking Zhang #define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL 3881*b77a9fdfSHawking Zhang #define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L 3882*b77a9fdfSHawking Zhang //UVD_GPCOM_SYS_DATA0 3883*b77a9fdfSHawking Zhang #define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 3884*b77a9fdfSHawking Zhang #define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL 3885*b77a9fdfSHawking Zhang //UVD_GPCOM_SYS_DATA1 3886*b77a9fdfSHawking Zhang #define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 3887*b77a9fdfSHawking Zhang #define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL 3888*b77a9fdfSHawking Zhang //UVD_VCPU_INT_EN 3889*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 3890*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 3891*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 3892*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3 3893*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4 3894*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5 3895*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 3896*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7 3897*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9 3898*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa 3899*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb 3900*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc 3901*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SUVD_EN__SHIFT 0xf 3902*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10 3903*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11 3904*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12 3905*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN__SHIFT 0x16 3906*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 3907*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18 3908*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19 3909*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a 3910*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b 3911*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 3912*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 3913*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e 3914*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f 3915*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 3916*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 3917*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 3918*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L 3919*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L 3920*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L 3921*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 3922*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L 3923*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L 3924*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L 3925*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L 3926*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L 3927*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SUVD_EN_MASK 0x00008000L 3928*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L 3929*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L 3930*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L 3931*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK 0x00400000L 3932*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 3933*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L 3934*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L 3935*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L 3936*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L 3937*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 3938*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 3939*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L 3940*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L 3941*b77a9fdfSHawking Zhang //UVD_VCPU_INT_STATUS 3942*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 3943*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 3944*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 3945*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT__SHIFT 0x3 3946*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SW_RB1_INT__SHIFT 0x4 3947*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SW_RB2_INT__SHIFT 0x5 3948*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 3949*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SW_RB3_INT__SHIFT 0x7 3950*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SW_RB4_INT__SHIFT 0x9 3951*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SW_RB5_INT__SHIFT 0xa 3952*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__LBSI_INT__SHIFT 0xb 3953*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__UDEC_INT__SHIFT 0xc 3954*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SUVD_INT__SHIFT 0xf 3955*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__RPTR_WR_INT__SHIFT 0x10 3956*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__JOB_START_INT__SHIFT 0x11 3957*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__NJ_PF_INT__SHIFT 0x12 3958*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__GPCOM_INT__SHIFT 0x14 3959*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__RASCNTL_VCPU_VCODEC_INT__SHIFT 0x15 3960*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 3961*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__IDCT_INT__SHIFT 0x18 3962*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__MPRD_INT__SHIFT 0x19 3963*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__AVM_INT__SHIFT 0x1a 3964*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 3965*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__MIF_HWINT__SHIFT 0x1c 3966*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 3967*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT__SHIFT 0x1e 3968*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT__SHIFT 0x1f 3969*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 3970*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 3971*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 3972*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT_MASK 0x00000008L 3973*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SW_RB1_INT_MASK 0x00000010L 3974*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SW_RB2_INT_MASK 0x00000020L 3975*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 3976*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SW_RB3_INT_MASK 0x00000080L 3977*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SW_RB4_INT_MASK 0x00000200L 3978*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SW_RB5_INT_MASK 0x00000400L 3979*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__LBSI_INT_MASK 0x00000800L 3980*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__UDEC_INT_MASK 0x00001000L 3981*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SUVD_INT_MASK 0x00008000L 3982*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__RPTR_WR_INT_MASK 0x00010000L 3983*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__JOB_START_INT_MASK 0x00020000L 3984*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__NJ_PF_INT_MASK 0x00040000L 3985*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__GPCOM_INT_MASK 0x00100000L 3986*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__RASCNTL_VCPU_VCODEC_INT_MASK 0x00200000L 3987*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 3988*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__IDCT_INT_MASK 0x01000000L 3989*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__MPRD_INT_MASK 0x02000000L 3990*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__AVM_INT_MASK 0x04000000L 3991*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 3992*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__MIF_HWINT_MASK 0x10000000L 3993*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 3994*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT_MASK 0x40000000L 3995*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT_MASK 0x80000000L 3996*b77a9fdfSHawking Zhang //UVD_VCPU_INT_ACK 3997*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 3998*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 3999*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 4000*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3 4001*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4 4002*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5 4003*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 4004*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7 4005*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9 4006*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa 4007*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb 4008*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc 4009*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SUVD_ACK__SHIFT 0xf 4010*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10 4011*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11 4012*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12 4013*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__RASCNTL_VCPU_VCODEC_ACK__SHIFT 0x16 4014*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 4015*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18 4016*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19 4017*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a 4018*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 4019*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 4020*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 4021*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e 4022*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f 4023*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 4024*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 4025*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 4026*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L 4027*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L 4028*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L 4029*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 4030*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L 4031*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L 4032*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L 4033*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L 4034*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L 4035*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SUVD_ACK_MASK 0x00008000L 4036*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L 4037*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L 4038*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L 4039*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__RASCNTL_VCPU_VCODEC_ACK_MASK 0x00400000L 4040*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 4041*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L 4042*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L 4043*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L 4044*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 4045*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 4046*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 4047*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L 4048*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L 4049*b77a9fdfSHawking Zhang //UVD_VCPU_INT_ROUTE 4050*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0 4051*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1 4052*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2 4053*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L 4054*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L 4055*b77a9fdfSHawking Zhang #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L 4056*b77a9fdfSHawking Zhang //UVD_DRV_FW_MSG 4057*b77a9fdfSHawking Zhang #define UVD_DRV_FW_MSG__MSG__SHIFT 0x0 4058*b77a9fdfSHawking Zhang #define UVD_DRV_FW_MSG__MSG_MASK 0xFFFFFFFFL 4059*b77a9fdfSHawking Zhang //UVD_FW_DRV_MSG_ACK 4060*b77a9fdfSHawking Zhang #define UVD_FW_DRV_MSG_ACK__ACK__SHIFT 0x0 4061*b77a9fdfSHawking Zhang #define UVD_FW_DRV_MSG_ACK__ACK_MASK 0x00000001L 4062*b77a9fdfSHawking Zhang //UVD_SUVD_INT_EN 4063*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN__SHIFT 0x0 4064*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SRE_ERR_INT_EN__SHIFT 0x5 4065*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN__SHIFT 0x6 4066*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SIT_ERR_INT_EN__SHIFT 0xb 4067*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN__SHIFT 0xc 4068*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SMP_ERR_INT_EN__SHIFT 0x11 4069*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN__SHIFT 0x12 4070*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SCM_ERR_INT_EN__SHIFT 0x17 4071*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN__SHIFT 0x18 4072*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SDB_ERR_INT_EN__SHIFT 0x1d 4073*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN_MASK 0x0000001FL 4074*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SRE_ERR_INT_EN_MASK 0x00000020L 4075*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN_MASK 0x000007C0L 4076*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SIT_ERR_INT_EN_MASK 0x00000800L 4077*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN_MASK 0x0001F000L 4078*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SMP_ERR_INT_EN_MASK 0x00020000L 4079*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN_MASK 0x007C0000L 4080*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SCM_ERR_INT_EN_MASK 0x00800000L 4081*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN_MASK 0x1F000000L 4082*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_EN__SDB_ERR_INT_EN_MASK 0x20000000L 4083*b77a9fdfSHawking Zhang //UVD_SUVD_INT_STATUS 4084*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SRE_FUNC_INT__SHIFT 0x0 4085*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SRE_ERR_INT__SHIFT 0x5 4086*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SIT_FUNC_INT__SHIFT 0x6 4087*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SIT_ERR_INT__SHIFT 0xb 4088*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SMP_FUNC_INT__SHIFT 0xc 4089*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SMP_ERR_INT__SHIFT 0x11 4090*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SCM_FUNC_INT__SHIFT 0x12 4091*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SCM_ERR_INT__SHIFT 0x17 4092*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SDB_FUNC_INT__SHIFT 0x18 4093*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SDB_ERR_INT__SHIFT 0x1d 4094*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SRE_FUNC_INT_MASK 0x0000001FL 4095*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SRE_ERR_INT_MASK 0x00000020L 4096*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SIT_FUNC_INT_MASK 0x000007C0L 4097*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SIT_ERR_INT_MASK 0x00000800L 4098*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SMP_FUNC_INT_MASK 0x0001F000L 4099*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SMP_ERR_INT_MASK 0x00020000L 4100*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SCM_FUNC_INT_MASK 0x007C0000L 4101*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SCM_ERR_INT_MASK 0x00800000L 4102*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SDB_FUNC_INT_MASK 0x1F000000L 4103*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_STATUS__SDB_ERR_INT_MASK 0x20000000L 4104*b77a9fdfSHawking Zhang //UVD_SUVD_INT_ACK 4105*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK__SHIFT 0x0 4106*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK__SHIFT 0x5 4107*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK__SHIFT 0x6 4108*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK__SHIFT 0xb 4109*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK__SHIFT 0xc 4110*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK__SHIFT 0x11 4111*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK__SHIFT 0x12 4112*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK__SHIFT 0x17 4113*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK__SHIFT 0x18 4114*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK__SHIFT 0x1d 4115*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK_MASK 0x0000001FL 4116*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK_MASK 0x00000020L 4117*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK_MASK 0x000007C0L 4118*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK_MASK 0x00000800L 4119*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK_MASK 0x0001F000L 4120*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK_MASK 0x00020000L 4121*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK_MASK 0x007C0000L 4122*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK_MASK 0x00800000L 4123*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK_MASK 0x1F000000L 4124*b77a9fdfSHawking Zhang #define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK_MASK 0x20000000L 4125*b77a9fdfSHawking Zhang //UVD_ENC_VCPU_INT_EN 4126*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0 4127*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1 4128*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2 4129*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L 4130*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L 4131*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L 4132*b77a9fdfSHawking Zhang //UVD_ENC_VCPU_INT_STATUS 4133*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT__SHIFT 0x0 4134*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT__SHIFT 0x1 4135*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT__SHIFT 0x2 4136*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT_MASK 0x00000001L 4137*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT_MASK 0x00000002L 4138*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT_MASK 0x00000004L 4139*b77a9fdfSHawking Zhang //UVD_ENC_VCPU_INT_ACK 4140*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0 4141*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1 4142*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2 4143*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L 4144*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L 4145*b77a9fdfSHawking Zhang #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L 4146*b77a9fdfSHawking Zhang //UVD_MASTINT_EN 4147*b77a9fdfSHawking Zhang #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 4148*b77a9fdfSHawking Zhang #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 4149*b77a9fdfSHawking Zhang #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 4150*b77a9fdfSHawking Zhang #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 4151*b77a9fdfSHawking Zhang #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 4152*b77a9fdfSHawking Zhang #define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L 4153*b77a9fdfSHawking Zhang #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L 4154*b77a9fdfSHawking Zhang #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x00FFFFF0L 4155*b77a9fdfSHawking Zhang //UVD_SYS_INT_EN 4156*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 4157*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 4158*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 4159*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3 4160*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 4161*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb 4162*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc 4163*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__SUVD_EN__SHIFT 0xf 4164*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10 4165*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 4166*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18 4167*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19 4168*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN__SHIFT 0x1a 4169*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b 4170*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 4171*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 4172*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f 4173*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 4174*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 4175*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 4176*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L 4177*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 4178*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L 4179*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L 4180*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__SUVD_EN_MASK 0x00008000L 4181*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L 4182*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 4183*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L 4184*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L 4185*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK 0x04000000L 4186*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L 4187*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 4188*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 4189*b77a9fdfSHawking Zhang #define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L 4190*b77a9fdfSHawking Zhang //UVD_SYS_INT_STATUS 4191*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 4192*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 4193*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 4194*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3 4195*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 4196*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb 4197*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc 4198*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__SUVD_INT__SHIFT 0xf 4199*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10 4200*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12 4201*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 4202*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18 4203*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19 4204*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 4205*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c 4206*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 4207*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__RASCNTL_VCPU_VCODEC_INT__SHIFT 0x1e 4208*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f 4209*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 4210*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 4211*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 4212*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L 4213*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 4214*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L 4215*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L 4216*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__SUVD_INT_MASK 0x00008000L 4217*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L 4218*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L 4219*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 4220*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L 4221*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L 4222*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 4223*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L 4224*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 4225*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__RASCNTL_VCPU_VCODEC_INT_MASK 0x40000000L 4226*b77a9fdfSHawking Zhang #define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L 4227*b77a9fdfSHawking Zhang //UVD_SYS_INT_ACK 4228*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 4229*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 4230*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 4231*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3 4232*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 4233*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb 4234*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc 4235*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__SUVD_ACK__SHIFT 0xf 4236*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10 4237*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 4238*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18 4239*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19 4240*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 4241*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 4242*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 4243*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__RASCNTL_VCPU_VCODEC_ACK__SHIFT 0x1e 4244*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f 4245*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 4246*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 4247*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 4248*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L 4249*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 4250*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L 4251*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L 4252*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__SUVD_ACK_MASK 0x00008000L 4253*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L 4254*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 4255*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L 4256*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L 4257*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 4258*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 4259*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 4260*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__RASCNTL_VCPU_VCODEC_ACK_MASK 0x40000000L 4261*b77a9fdfSHawking Zhang #define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L 4262*b77a9fdfSHawking Zhang //UVD_JOB_DONE 4263*b77a9fdfSHawking Zhang #define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0 4264*b77a9fdfSHawking Zhang #define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L 4265*b77a9fdfSHawking Zhang //UVD_CBUF_ID 4266*b77a9fdfSHawking Zhang #define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0 4267*b77a9fdfSHawking Zhang #define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL 4268*b77a9fdfSHawking Zhang //UVD_CONTEXT_ID 4269*b77a9fdfSHawking Zhang #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 4270*b77a9fdfSHawking Zhang #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL 4271*b77a9fdfSHawking Zhang //UVD_CONTEXT_ID2 4272*b77a9fdfSHawking Zhang #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 4273*b77a9fdfSHawking Zhang #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL 4274*b77a9fdfSHawking Zhang //UVD_NO_OP 4275*b77a9fdfSHawking Zhang #define UVD_NO_OP__NO_OP__SHIFT 0x0 4276*b77a9fdfSHawking Zhang #define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL 4277*b77a9fdfSHawking Zhang //UVD_RB_BASE_LO 4278*b77a9fdfSHawking Zhang #define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 4279*b77a9fdfSHawking Zhang #define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 4280*b77a9fdfSHawking Zhang //UVD_RB_BASE_HI 4281*b77a9fdfSHawking Zhang #define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 4282*b77a9fdfSHawking Zhang #define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 4283*b77a9fdfSHawking Zhang //UVD_RB_SIZE 4284*b77a9fdfSHawking Zhang #define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 4285*b77a9fdfSHawking Zhang #define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 4286*b77a9fdfSHawking Zhang //UVD_RB_RPTR 4287*b77a9fdfSHawking Zhang #define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 4288*b77a9fdfSHawking Zhang #define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 4289*b77a9fdfSHawking Zhang //UVD_RB_WPTR 4290*b77a9fdfSHawking Zhang #define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 4291*b77a9fdfSHawking Zhang #define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 4292*b77a9fdfSHawking Zhang //UVD_RB_BASE_LO2 4293*b77a9fdfSHawking Zhang #define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 4294*b77a9fdfSHawking Zhang #define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L 4295*b77a9fdfSHawking Zhang //UVD_RB_BASE_HI2 4296*b77a9fdfSHawking Zhang #define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 4297*b77a9fdfSHawking Zhang #define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL 4298*b77a9fdfSHawking Zhang //UVD_RB_SIZE2 4299*b77a9fdfSHawking Zhang #define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 4300*b77a9fdfSHawking Zhang #define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L 4301*b77a9fdfSHawking Zhang //UVD_RB_RPTR2 4302*b77a9fdfSHawking Zhang #define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 4303*b77a9fdfSHawking Zhang #define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L 4304*b77a9fdfSHawking Zhang //UVD_RB_WPTR2 4305*b77a9fdfSHawking Zhang #define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 4306*b77a9fdfSHawking Zhang #define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L 4307*b77a9fdfSHawking Zhang //UVD_RB_BASE_LO3 4308*b77a9fdfSHawking Zhang #define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 4309*b77a9fdfSHawking Zhang #define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L 4310*b77a9fdfSHawking Zhang //UVD_RB_BASE_HI3 4311*b77a9fdfSHawking Zhang #define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 4312*b77a9fdfSHawking Zhang #define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL 4313*b77a9fdfSHawking Zhang //UVD_RB_SIZE3 4314*b77a9fdfSHawking Zhang #define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 4315*b77a9fdfSHawking Zhang #define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L 4316*b77a9fdfSHawking Zhang //UVD_RB_RPTR3 4317*b77a9fdfSHawking Zhang #define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 4318*b77a9fdfSHawking Zhang #define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L 4319*b77a9fdfSHawking Zhang //UVD_RB_WPTR3 4320*b77a9fdfSHawking Zhang #define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 4321*b77a9fdfSHawking Zhang #define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L 4322*b77a9fdfSHawking Zhang //UVD_RB_BASE_LO4 4323*b77a9fdfSHawking Zhang #define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 4324*b77a9fdfSHawking Zhang #define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L 4325*b77a9fdfSHawking Zhang //UVD_RB_BASE_HI4 4326*b77a9fdfSHawking Zhang #define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 4327*b77a9fdfSHawking Zhang #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL 4328*b77a9fdfSHawking Zhang //UVD_RB_SIZE4 4329*b77a9fdfSHawking Zhang #define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 4330*b77a9fdfSHawking Zhang #define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L 4331*b77a9fdfSHawking Zhang //UVD_RB_RPTR4 4332*b77a9fdfSHawking Zhang #define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 4333*b77a9fdfSHawking Zhang #define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L 4334*b77a9fdfSHawking Zhang //UVD_RB_WPTR4 4335*b77a9fdfSHawking Zhang #define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 4336*b77a9fdfSHawking Zhang #define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L 4337*b77a9fdfSHawking Zhang //UVD_OUT_RB_BASE_LO 4338*b77a9fdfSHawking Zhang #define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 4339*b77a9fdfSHawking Zhang #define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 4340*b77a9fdfSHawking Zhang //UVD_OUT_RB_BASE_HI 4341*b77a9fdfSHawking Zhang #define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 4342*b77a9fdfSHawking Zhang #define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 4343*b77a9fdfSHawking Zhang //UVD_OUT_RB_SIZE 4344*b77a9fdfSHawking Zhang #define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4 4345*b77a9fdfSHawking Zhang #define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 4346*b77a9fdfSHawking Zhang //UVD_OUT_RB_RPTR 4347*b77a9fdfSHawking Zhang #define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4 4348*b77a9fdfSHawking Zhang #define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 4349*b77a9fdfSHawking Zhang //UVD_OUT_RB_WPTR 4350*b77a9fdfSHawking Zhang #define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4 4351*b77a9fdfSHawking Zhang #define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 4352*b77a9fdfSHawking Zhang //UVD_IOV_MAILBOX 4353*b77a9fdfSHawking Zhang #define UVD_IOV_MAILBOX__MAILBOX__SHIFT 0x0 4354*b77a9fdfSHawking Zhang #define UVD_IOV_MAILBOX__MAILBOX_MASK 0xFFFFFFFFL 4355*b77a9fdfSHawking Zhang //UVD_IOV_MAILBOX_RESP 4356*b77a9fdfSHawking Zhang #define UVD_IOV_MAILBOX_RESP__RESP__SHIFT 0x0 4357*b77a9fdfSHawking Zhang #define UVD_IOV_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 4358*b77a9fdfSHawking Zhang //UVD_RB_ARB_CTRL 4359*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0 4360*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1 4361*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2 4362*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3 4363*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4 4364*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5 4365*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6 4366*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7 4367*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8 4368*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L 4369*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L 4370*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L 4371*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L 4372*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L 4373*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L 4374*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L 4375*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L 4376*b77a9fdfSHawking Zhang #define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L 4377*b77a9fdfSHawking Zhang //UVD_CTX_INDEX 4378*b77a9fdfSHawking Zhang #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 4379*b77a9fdfSHawking Zhang #define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL 4380*b77a9fdfSHawking Zhang //UVD_CTX_DATA 4381*b77a9fdfSHawking Zhang #define UVD_CTX_DATA__DATA__SHIFT 0x0 4382*b77a9fdfSHawking Zhang #define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL 4383*b77a9fdfSHawking Zhang //UVD_CXW_WR 4384*b77a9fdfSHawking Zhang #define UVD_CXW_WR__DAT__SHIFT 0x0 4385*b77a9fdfSHawking Zhang #define UVD_CXW_WR__STAT__SHIFT 0x1f 4386*b77a9fdfSHawking Zhang #define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL 4387*b77a9fdfSHawking Zhang #define UVD_CXW_WR__STAT_MASK 0x80000000L 4388*b77a9fdfSHawking Zhang //UVD_CXW_WR_INT_ID 4389*b77a9fdfSHawking Zhang #define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0 4390*b77a9fdfSHawking Zhang #define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL 4391*b77a9fdfSHawking Zhang //UVD_CXW_WR_INT_CTX_ID 4392*b77a9fdfSHawking Zhang #define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0 4393*b77a9fdfSHawking Zhang #define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL 4394*b77a9fdfSHawking Zhang //UVD_CXW_INT_ID 4395*b77a9fdfSHawking Zhang #define UVD_CXW_INT_ID__ID__SHIFT 0x0 4396*b77a9fdfSHawking Zhang #define UVD_CXW_INT_ID__ID_MASK 0x000000FFL 4397*b77a9fdfSHawking Zhang //UVD_MPEG2_ERROR 4398*b77a9fdfSHawking Zhang #define UVD_MPEG2_ERROR__STATUS__SHIFT 0x0 4399*b77a9fdfSHawking Zhang #define UVD_MPEG2_ERROR__STATUS_MASK 0xFFFFFFFFL 4400*b77a9fdfSHawking Zhang //UVD_TOP_CTRL 4401*b77a9fdfSHawking Zhang #define UVD_TOP_CTRL__STANDARD__SHIFT 0x0 4402*b77a9fdfSHawking Zhang #define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4 4403*b77a9fdfSHawking Zhang #define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL 4404*b77a9fdfSHawking Zhang #define UVD_TOP_CTRL__STD_VERSION_MASK 0x000000F0L 4405*b77a9fdfSHawking Zhang //UVD_YBASE 4406*b77a9fdfSHawking Zhang #define UVD_YBASE__DUM__SHIFT 0x0 4407*b77a9fdfSHawking Zhang #define UVD_YBASE__DUM_MASK 0xFFFFFFFFL 4408*b77a9fdfSHawking Zhang //UVD_UVBASE 4409*b77a9fdfSHawking Zhang #define UVD_UVBASE__DUM__SHIFT 0x0 4410*b77a9fdfSHawking Zhang #define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL 4411*b77a9fdfSHawking Zhang //UVD_PITCH 4412*b77a9fdfSHawking Zhang #define UVD_PITCH__DUM__SHIFT 0x0 4413*b77a9fdfSHawking Zhang #define UVD_PITCH__DUM_MASK 0xFFFFFFFFL 4414*b77a9fdfSHawking Zhang //UVD_WIDTH 4415*b77a9fdfSHawking Zhang #define UVD_WIDTH__DUM__SHIFT 0x0 4416*b77a9fdfSHawking Zhang #define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL 4417*b77a9fdfSHawking Zhang //UVD_HEIGHT 4418*b77a9fdfSHawking Zhang #define UVD_HEIGHT__DUM__SHIFT 0x0 4419*b77a9fdfSHawking Zhang #define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL 4420*b77a9fdfSHawking Zhang //UVD_PICCOUNT 4421*b77a9fdfSHawking Zhang #define UVD_PICCOUNT__DUM__SHIFT 0x0 4422*b77a9fdfSHawking Zhang #define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL 4423*b77a9fdfSHawking Zhang //UVD_MPRD_INITIAL_XY 4424*b77a9fdfSHawking Zhang #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X__SHIFT 0x0 4425*b77a9fdfSHawking Zhang #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y__SHIFT 0x10 4426*b77a9fdfSHawking Zhang #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X_MASK 0x00000FFFL 4427*b77a9fdfSHawking Zhang #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y_MASK 0x0FFF0000L 4428*b77a9fdfSHawking Zhang //UVD_MPEG2_CTRL 4429*b77a9fdfSHawking Zhang #define UVD_MPEG2_CTRL__EN__SHIFT 0x0 4430*b77a9fdfSHawking Zhang #define UVD_MPEG2_CTRL__TRICK_MODE__SHIFT 0x1 4431*b77a9fdfSHawking Zhang #define UVD_MPEG2_CTRL__NUM_MB_PER_JOB__SHIFT 0x10 4432*b77a9fdfSHawking Zhang #define UVD_MPEG2_CTRL__EN_MASK 0x00000001L 4433*b77a9fdfSHawking Zhang #define UVD_MPEG2_CTRL__TRICK_MODE_MASK 0x00000002L 4434*b77a9fdfSHawking Zhang #define UVD_MPEG2_CTRL__NUM_MB_PER_JOB_MASK 0xFFFF0000L 4435*b77a9fdfSHawking Zhang //UVD_MB_CTL_BUF_BASE 4436*b77a9fdfSHawking Zhang #define UVD_MB_CTL_BUF_BASE__BASE__SHIFT 0x0 4437*b77a9fdfSHawking Zhang #define UVD_MB_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL 4438*b77a9fdfSHawking Zhang //UVD_PIC_CTL_BUF_BASE 4439*b77a9fdfSHawking Zhang #define UVD_PIC_CTL_BUF_BASE__BASE__SHIFT 0x0 4440*b77a9fdfSHawking Zhang #define UVD_PIC_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL 4441*b77a9fdfSHawking Zhang //UVD_DXVA_BUF_SIZE 4442*b77a9fdfSHawking Zhang #define UVD_DXVA_BUF_SIZE__PIC_SIZE__SHIFT 0x0 4443*b77a9fdfSHawking Zhang #define UVD_DXVA_BUF_SIZE__MB_SIZE__SHIFT 0x10 4444*b77a9fdfSHawking Zhang #define UVD_DXVA_BUF_SIZE__PIC_SIZE_MASK 0x0000FFFFL 4445*b77a9fdfSHawking Zhang #define UVD_DXVA_BUF_SIZE__MB_SIZE_MASK 0xFFFF0000L 4446*b77a9fdfSHawking Zhang //UVD_SCRATCH_NP 4447*b77a9fdfSHawking Zhang #define UVD_SCRATCH_NP__DATA__SHIFT 0x0 4448*b77a9fdfSHawking Zhang #define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL 4449*b77a9fdfSHawking Zhang //UVD_CLK_SWT_HANDSHAKE 4450*b77a9fdfSHawking Zhang #define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE__SHIFT 0x0 4451*b77a9fdfSHawking Zhang #define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT__SHIFT 0x8 4452*b77a9fdfSHawking Zhang #define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE_MASK 0x00000003L 4453*b77a9fdfSHawking Zhang #define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT_MASK 0x00000300L 4454*b77a9fdfSHawking Zhang //UVD_VERSION 4455*b77a9fdfSHawking Zhang #define UVD_VERSION__MINOR_VERSION__SHIFT 0x0 4456*b77a9fdfSHawking Zhang #define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 4457*b77a9fdfSHawking Zhang #define UVD_VERSION__INSTANCE_ID__SHIFT 0x1c 4458*b77a9fdfSHawking Zhang #define UVD_VERSION__MINOR_VERSION_MASK 0x0000FFFFL 4459*b77a9fdfSHawking Zhang #define UVD_VERSION__MAJOR_VERSION_MASK 0x0FFF0000L 4460*b77a9fdfSHawking Zhang #define UVD_VERSION__INSTANCE_ID_MASK 0xF0000000L 4461*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH0 4462*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 4463*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL 4464*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH1 4465*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 4466*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL 4467*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH2 4468*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 4469*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL 4470*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH3 4471*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 4472*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL 4473*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH4 4474*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 4475*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL 4476*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH5 4477*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 4478*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL 4479*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH6 4480*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 4481*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL 4482*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH7 4483*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 4484*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL 4485*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH8 4486*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 4487*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL 4488*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH9 4489*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 4490*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL 4491*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH10 4492*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 4493*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL 4494*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH11 4495*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 4496*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL 4497*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH12 4498*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 4499*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL 4500*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH13 4501*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 4502*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL 4503*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH14 4504*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 4505*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL 4506*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH15 4507*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 4508*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL 4509*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH16 4510*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 4511*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL 4512*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH17 4513*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 4514*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL 4515*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH18 4516*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 4517*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL 4518*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH19 4519*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 4520*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL 4521*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH20 4522*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 4523*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL 4524*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH21 4525*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 4526*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL 4527*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH22 4528*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 4529*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL 4530*b77a9fdfSHawking Zhang //UVD_GP_SCRATCH23 4531*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 4532*b77a9fdfSHawking Zhang #define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL 4533*b77a9fdfSHawking Zhang 4534*b77a9fdfSHawking Zhang 4535*b77a9fdfSHawking Zhang #endif 4536