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Searched refs:UVD_MPC_SET_MUX__SET_0__SHIFT (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h634 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
H A Duvd_4_0_sh_mask.h529 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x00000000 macro
H A Duvd_3_1_sh_mask.h510 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 macro
H A Duvd_4_2_sh_mask.h514 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 macro
H A Duvd_6_0_sh_mask.h548 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 macro
H A Duvd_5_0_sh_mask.h546 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1141 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2882 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2647 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h2874 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3955 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h4205 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4248 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c803 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v4_0_3_start_dpg_mode()
1131 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v4_0_3_start()
H A Dvcn_v2_0.c858 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v2_0_start_dpg_mode()
991 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v2_0_start()
H A Dvcn_v4_0.c977 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v4_0_start_dpg_mode()
1116 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v4_0_start()
H A Dvcn_v1_0.c843 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v1_0_start_spg_mode()
1026 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v1_0_start_dpg_mode()
H A Dvcn_v2_5.c883 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v2_5_start_dpg_mode()
1037 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v2_5_start()
H A Dvcn_v3_0.c1006 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v3_0_start_dpg_mode()
1170 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v3_0_start()