Home
last modified time | relevance | path

Searched refs:UVD_CGC_GATE__UDEC_RE_MASK (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v6_0.c653 UVD_CGC_GATE__UDEC_RE_MASK |
686 UVD_CGC_GATE__UDEC_RE_MASK |
1310 UVD_CGC_GATE__UDEC_RE_MASK | in uvd_v6_0_enable_clock_gating()
1398 UVD_CGC_GATE__UDEC_RE_MASK |
H A Duvd_v5_0.c653 UVD_CGC_GATE__UDEC_RE_MASK | in uvd_v5_0_enable_clock_gating()
740 UVD_CGC_GATE__UDEC_RE_MASK |
H A Duvd_v7_0.c1684 UVD_CGC_GATE__UDEC_RE_MASK |
H A Dvcn_v2_0.c520 | UVD_CGC_GATE__UDEC_RE_MASK in vcn_v2_0_disable_clock_gating()
H A Dvcn_v4_0.c689 | UVD_CGC_GATE__UDEC_RE_MASK in vcn_v4_0_disable_clock_gating()
H A Dvcn_v1_0.c495 | UVD_CGC_GATE__UDEC_RE_MASK in vcn_v1_0_disable_clock_gating()
H A Dvcn_v2_5.c603 | UVD_CGC_GATE__UDEC_RE_MASK in vcn_v2_5_disable_clock_gating()
H A Dvcn_v3_0.c725 | UVD_CGC_GATE__UDEC_RE_MASK in vcn_v3_0_disable_clock_gating()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h409 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Duvd_4_0_sh_mask.h111 #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L macro
H A Duvd_3_1_sh_mask.h147 #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 macro
H A Duvd_4_2_sh_mask.h147 #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 macro
H A Duvd_6_0_sh_mask.h161 #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 macro
H A Duvd_5_0_sh_mask.h159 #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h837 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Dvcn_2_5_sh_mask.h1907 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1856 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3578 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2637 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Dvcn_4_0_0_sh_mask.h72 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Dvcn_4_0_3_sh_mask.h72 #define UVD_CGC_GATE__UDEC_RE_MASK … macro