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Searched refs:UVD_CGC_CTRL__UDEC_RE_MODE_MASK (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h444 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro
H A Duvd_4_0_sh_mask.h72 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L macro
H A Duvd_4_2_sh_mask.h227 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 macro
H A Duvd_3_1_sh_mask.h227 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 macro
H A Duvd_6_0_sh_mask.h251 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 macro
H A Duvd_5_0_sh_mask.h249 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c531 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v2_0_disable_clock_gating()
607 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | in vcn_v2_0_clock_gating_dpg_mode()
668 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v2_0_enable_clock_gating()
H A Dvcn_v4_0.c702 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v4_0_disable_clock_gating()
787 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | in vcn_v4_0_disable_clock_gating_dpg_mode()
845 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v4_0_enable_clock_gating()
H A Dvcn_v1_0.c506 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v1_0_disable_clock_gating()
606 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v1_0_enable_clock_gating()
664 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | in vcn_v1_0_clock_gating_dpg_mode()
H A Duvd_v5_0.c691 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | in uvd_v5_0_set_sw_clock_gating()
H A Dvcn_v2_5.c617 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v2_5_disable_clock_gating()
694 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | in vcn_v2_5_clock_gating_dpg_mode()
756 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v2_5_enable_clock_gating()
H A Dvcn_v3_0.c739 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v3_0_disable_clock_gating()
838 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | in vcn_v3_0_clock_gating_dpg_mode()
897 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK in vcn_v3_0_enable_clock_gating()
H A Duvd_v6_0.c1348 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | in uvd_v6_0_set_sw_clock_gating()
H A Duvd_v7_0.c1632 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h937 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro
H A Dvcn_2_5_sh_mask.h2005 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1956 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3676 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2735 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro
H A Dvcn_4_0_0_sh_mask.h113 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro
H A Dvcn_4_0_3_sh_mask.h113 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK … macro