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Searched refs:UVD_CGC_CTRL__MPC_MODE_MASK (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h458 #define UVD_CGC_CTRL__MPC_MODE_MASK … macro
H A Duvd_4_0_sh_mask.h48 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L macro
H A Duvd_3_1_sh_mask.h255 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 macro
H A Duvd_4_2_sh_mask.h255 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 macro
H A Duvd_6_0_sh_mask.h279 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 macro
H A Duvd_5_0_sh_mask.h277 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c573 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v4_0_3_disable_clock_gating()
647 UVD_CGC_CTRL__MPC_MODE_MASK | in vcn_v4_0_3_disable_clock_gating_dpg_mode()
700 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v4_0_3_enable_clock_gating()
H A Dvcn_v2_0.c545 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v2_0_disable_clock_gating()
621 UVD_CGC_CTRL__MPC_MODE_MASK | in vcn_v2_0_clock_gating_dpg_mode()
682 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v2_0_enable_clock_gating()
H A Dvcn_v4_0.c716 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v4_0_disable_clock_gating()
801 UVD_CGC_CTRL__MPC_MODE_MASK | in vcn_v4_0_disable_clock_gating_dpg_mode()
859 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v4_0_enable_clock_gating()
H A Dvcn_v1_0.c520 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v1_0_disable_clock_gating()
620 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v1_0_enable_clock_gating()
678 UVD_CGC_CTRL__MPC_MODE_MASK | in vcn_v1_0_clock_gating_dpg_mode()
H A Dvcn_v2_5.c631 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v2_5_disable_clock_gating()
708 UVD_CGC_CTRL__MPC_MODE_MASK | in vcn_v2_5_clock_gating_dpg_mode()
770 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v2_5_enable_clock_gating()
H A Duvd_v5_0.c705 UVD_CGC_CTRL__MPC_MODE_MASK | in uvd_v5_0_set_sw_clock_gating()
H A Dvcn_v3_0.c753 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v3_0_disable_clock_gating()
852 UVD_CGC_CTRL__MPC_MODE_MASK | in vcn_v3_0_clock_gating_dpg_mode()
911 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v3_0_enable_clock_gating()
H A Duvd_v6_0.c1362 UVD_CGC_CTRL__MPC_MODE_MASK | in uvd_v6_0_set_sw_clock_gating()
H A Duvd_v7_0.c1646 UVD_CGC_CTRL__MPC_MODE_MASK |
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h951 #define UVD_CGC_CTRL__MPC_MODE_MASK … macro
H A Dvcn_2_5_sh_mask.h2019 #define UVD_CGC_CTRL__MPC_MODE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1970 #define UVD_CGC_CTRL__MPC_MODE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3690 #define UVD_CGC_CTRL__MPC_MODE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2749 #define UVD_CGC_CTRL__MPC_MODE_MASK … macro
H A Dvcn_4_0_0_sh_mask.h127 #define UVD_CGC_CTRL__MPC_MODE_MASK … macro
H A Dvcn_4_0_3_sh_mask.h127 #define UVD_CGC_CTRL__MPC_MODE_MASK … macro