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Searched refs:REG (Results 1 – 25 of 336) sorted by relevance

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/openbmc/linux/drivers/net/ethernet/mscc/
H A Dvsc7514_regs.c154 REG(QS_XTR_RD, 0x000008),
160 REG(QS_INJ_WR, 0x00002c),
222 REG(REW_PPT, 0x000680),
383 REG(DEV_CLOCK_CFG, 0x0),
384 REG(DEV_PORT_MISC, 0x4),
385 REG(DEV_EVENTS, 0x8),
386 REG(DEV_EEE_CFG, 0xc),
401 REG(PCS1G_CFG, 0x48),
403 REG(PCS1G_SD_CFG, 0x50),
406 REG(PCS1G_LB_CFG, 0x5c),
[all …]
/openbmc/linux/tools/perf/arch/csky/util/
H A Dunwind-libdw.c16 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
23 dwarf_regs[0] = REG(A0); in libdw__arch_set_initial_registers()
24 dwarf_regs[1] = REG(A1); in libdw__arch_set_initial_registers()
25 dwarf_regs[2] = REG(A2); in libdw__arch_set_initial_registers()
26 dwarf_regs[3] = REG(A3); in libdw__arch_set_initial_registers()
37 dwarf_regs[14] = REG(SP); in libdw__arch_set_initial_registers()
38 dwarf_regs[15] = REG(LR); in libdw__arch_set_initial_registers()
55 dwarf_regs[32] = REG(PC); in libdw__arch_set_initial_registers()
57 dwarf_regs[0] = REG(SP); in libdw__arch_set_initial_registers()
59 dwarf_regs[2] = REG(A0); in libdw__arch_set_initial_registers()
[all …]
/openbmc/linux/drivers/net/dsa/ocelot/
H A Dseville_vsc9953.c43 REG(ANA_ADVLEARN, 0x00b500),
44 REG(ANA_VLANMASK, 0x00b504),
46 REG(ANA_ANAGEFIL, 0x00b50c),
47 REG(ANA_ANEVENTS, 0x00b510),
52 REG(ANA_AUTOAGE, 0x00b530),
55 REG(ANA_AGENCTRL, 0x00b53c),
58 REG(ANA_FLOODING, 0x00b548),
146 REG(QS_XTR_RD, 0x000008),
407 REG(DEV_CLOCK_CFG, 0x0),
408 REG(DEV_PORT_MISC, 0x4),
[all …]
H A Dfelix_vsc9959.c49 REG(ANA_ADVLEARN, 0x0089a0),
50 REG(ANA_VLANMASK, 0x0089a4),
52 REG(ANA_ANAGEFIL, 0x0089ac),
53 REG(ANA_ANEVENTS, 0x0089b0),
58 REG(ANA_AUTOAGE, 0x0089d0),
61 REG(ANA_AGENCTRL, 0x0089dc),
64 REG(ANA_FLOODING, 0x0089e8),
463 REG(DEV_CLOCK_CFG, 0x0),
464 REG(DEV_PORT_MISC, 0x4),
465 REG(DEV_EVENTS, 0x8),
[all …]
/openbmc/linux/tools/perf/arch/s390/util/
H A Dunwind-libdw.c17 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
26 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
27 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
28 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
29 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
30 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
31 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
32 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
33 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
34 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers()
[all …]
/openbmc/linux/tools/perf/arch/arm64/util/
H A Dunwind-libdw.c14 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
20 dwarf_regs[0] = REG(X0); in libdw__arch_set_initial_registers()
21 dwarf_regs[1] = REG(X1); in libdw__arch_set_initial_registers()
22 dwarf_regs[2] = REG(X2); in libdw__arch_set_initial_registers()
23 dwarf_regs[3] = REG(X3); in libdw__arch_set_initial_registers()
24 dwarf_regs[4] = REG(X4); in libdw__arch_set_initial_registers()
25 dwarf_regs[5] = REG(X5); in libdw__arch_set_initial_registers()
26 dwarf_regs[6] = REG(X6); in libdw__arch_set_initial_registers()
27 dwarf_regs[7] = REG(X7); in libdw__arch_set_initial_registers()
28 dwarf_regs[8] = REG(X8); in libdw__arch_set_initial_registers()
[all …]
/openbmc/linux/tools/perf/arch/loongarch/util/
H A Dunwind-libdw.c16 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
23 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
24 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
25 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
26 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
27 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
28 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
29 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
30 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers()
31 dwarf_regs[9] = REG(R9); in libdw__arch_set_initial_registers()
[all …]
/openbmc/linux/tools/perf/arch/riscv/util/
H A Dunwind-libdw.c16 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
23 dwarf_regs[1] = REG(RA); in libdw__arch_set_initial_registers()
24 dwarf_regs[2] = REG(SP); in libdw__arch_set_initial_registers()
25 dwarf_regs[3] = REG(GP); in libdw__arch_set_initial_registers()
26 dwarf_regs[4] = REG(TP); in libdw__arch_set_initial_registers()
27 dwarf_regs[5] = REG(T0); in libdw__arch_set_initial_registers()
28 dwarf_regs[6] = REG(T1); in libdw__arch_set_initial_registers()
29 dwarf_regs[7] = REG(T2); in libdw__arch_set_initial_registers()
30 dwarf_regs[8] = REG(S0); in libdw__arch_set_initial_registers()
31 dwarf_regs[9] = REG(S1); in libdw__arch_set_initial_registers()
[all …]
/openbmc/linux/tools/perf/arch/powerpc/util/
H A Dunwind-libdw.c23 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
29 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
30 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
31 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
32 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
33 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
34 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
35 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
36 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
37 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers()
[all …]
/openbmc/linux/drivers/net/ethernet/apple/
H A Dmace.h12 REG(rcvfifo); /* receive FIFO */
13 REG(xmtfifo); /* transmit FIFO */
22 REG(pr); /* poll register */
31 REG(reg19);
34 REG(reg22);
35 REG(reg23);
37 REG(reg25);
40 REG(reg28);
41 REG(utr); /* user test reg */
42 REG(reg30);
[all …]
/openbmc/linux/tools/perf/arch/x86/util/
H A Dunwind-libdw.c15 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
22 dwarf_regs[0] = REG(AX); in libdw__arch_set_initial_registers()
23 dwarf_regs[1] = REG(CX); in libdw__arch_set_initial_registers()
24 dwarf_regs[2] = REG(DX); in libdw__arch_set_initial_registers()
25 dwarf_regs[3] = REG(BX); in libdw__arch_set_initial_registers()
26 dwarf_regs[4] = REG(SP); in libdw__arch_set_initial_registers()
27 dwarf_regs[5] = REG(BP); in libdw__arch_set_initial_registers()
28 dwarf_regs[6] = REG(SI); in libdw__arch_set_initial_registers()
29 dwarf_regs[7] = REG(DI); in libdw__arch_set_initial_registers()
30 dwarf_regs[8] = REG(IP); in libdw__arch_set_initial_registers()
[all …]
/openbmc/qemu/target/sh4/
H A Dtranslate.c558 tcg_gen_mov_i32(REG(B11_8), REG(B7_4)); in _decode_opc()
693 tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4)); in _decode_opc()
720 tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4)); in _decode_opc()
853 tcg_gen_neg_i32(REG(B11_8), REG(B7_4)); in _decode_opc()
866 tcg_gen_not_i32(REG(B11_8), REG(B7_4)); in _decode_opc()
869 tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4)); in _decode_opc()
916 tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4)); in _decode_opc()
951 tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4)); in _decode_opc()
1131 tcg_gen_andi_i32(REG(0), REG(0), B7_0); in _decode_opc()
1244 tcg_gen_ori_i32(REG(0), REG(0), B7_0); in _decode_opc()
[all …]
/openbmc/linux/drivers/regulator/
H A Drn5t618-regulator.c25 #define REG(rid, ereg, emask, vreg, vmask, min, max, step) \ macro
45 REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
46 REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
47 REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
48 REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500),
50 REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
51 REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
52 REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000),
53 REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
54 REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000),
[all …]
/openbmc/linux/drivers/gpu/drm/tidss/
H A Dtidss_dispc_regs.h55 #define REG(r) (dispc_common_regmap[r ## _OFF]) macro
57 #define DSS_REVISION REG(DSS_REVISION)
58 #define DSS_SYSCONFIG REG(DSS_SYSCONFIG)
59 #define DSS_SYSSTATUS REG(DSS_SYSSTATUS)
60 #define DISPC_IRQ_EOI REG(DISPC_IRQ_EOI)
62 #define DISPC_IRQSTATUS REG(DISPC_IRQSTATUS)
69 #define WB_IRQENABLE REG(WB_IRQENABLE)
70 #define WB_IRQSTATUS REG(WB_IRQSTATUS)
75 #define DSS_CBA_CFG REG(DSS_CBA_CFG)
91 #define DISPC_MSS_VP1 REG(DISPC_MSS_VP1)
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_lrc.c110 REG(0x034),
111 REG(0x030),
112 REG(0x038),
113 REG(0x03c),
114 REG(0x168),
115 REG(0x140),
116 REG(0x110),
117 REG(0x11c),
118 REG(0x114),
119 REG(0x118),
[all …]
/openbmc/u-boot/drivers/video/
H A Dtda19988.c19 #define REG(page, addr) (((page) << 8) | (addr)) macro
27 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
35 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
36 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
55 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
56 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
94 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
99 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
100 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
101 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
H A Dhw_translate_dcn10.c51 #define REG(reg_name)\ macro
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
180 case REG(DC_GPIO_DDC6_A): in offset_to_id()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/
H A Dhw_translate_dce120.c51 #define REG(reg_name)\ macro
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
180 case REG(DC_GPIO_DDC6_A): in offset_to_id()
[all …]
/openbmc/u-boot/drivers/i2c/
H A Ddavinci_i2c.c34 REG(&(i2c_base->i2c_con)) = 0;\
81 REG(&(i2c_base->i2c_drr)); in _flush_rx()
97 REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll)); in _davinci_i2c_setspeed()
106 REG(&(i2c_base->i2c_con)) = 0; in _davinci_i2c_init()
113 REG(&(i2c_base->i2c_cnt)) = 0; in _davinci_i2c_init()
217 REG(&(i2c_base->i2c_cnt)) = 0; in _davinci_i2c_read()
218 REG(&(i2c_base->i2c_con)) = 0; in _davinci_i2c_read()
299 REG(&(i2c_base->i2c_cnt)) = 0; in _davinci_i2c_write()
300 REG(&(i2c_base->i2c_con)) = 0; in _davinci_i2c_write()
312 REG(&(i2c_base->i2c_con)) = 0; in _davinci_i2c_probe_chip()
[all …]
/openbmc/linux/tools/perf/arch/arm/util/
H A Dunwind-libdw.c14 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
20 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
21 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
22 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
23 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
24 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
25 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
26 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
27 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
28 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers()
[all …]
/openbmc/linux/arch/m68k/lib/
H A Dmulsi3.S67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
76 #define a1 REG (a1)
[all …]
H A Dumodsi3.S67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
76 #define a1 REG (a1)
[all …]
H A Dmodsi3.S69 #define d0 REG (d0)
70 #define d1 REG (d1)
71 #define d2 REG (d2)
72 #define d3 REG (d3)
73 #define d4 REG (d4)
74 #define d5 REG (d5)
75 #define d6 REG (d6)
76 #define d7 REG (d7)
77 #define a0 REG (a0)
78 #define a1 REG (a1)
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dasm.h14 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
15 brz,PREDICT REG, DEST
17 brz,a,PREDICT REG, DEST
18 #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \ argument
19 brnz,PREDICT REG, DEST
21 brnz,a,PREDICT REG, DEST
27 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
28 cmp REG, 0; \
31 cmp REG, 0; \
34 cmp REG, 0; \
[all …]
H A Dtrap_block.h120 #define __GET_CPUID(REG) \ argument
123 srlx REG, 17, REG; \
124 and REG, 0x1f, REG; \
131 srlx REG, 17, REG; \
132 and REG, 0x3ff, REG; \
136 srlx REG, 17, REG; \
137 and REG, 0x1f, REG; \
141 sllx REG, 9, REG; \
142 or REG, 0xd0, REG; \
143 lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
[all …]

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