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Searched refs:REG (Results 1 – 25 of 52) sorted by relevance

123

/openbmc/qemu/target/sh4/
H A Dtranslate.c354 #define REG(x) cpu_gregs[(x) ^ ctx->gbank] macro
496 tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); in _decode_opc()
497 tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, in _decode_opc()
504 tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4); in _decode_opc()
505 tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, in _decode_opc()
523 tcg_gen_movi_i32(REG(B11_8), B7_0s); in _decode_opc()
529 tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, in _decode_opc()
537 tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, in _decode_opc()
542 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s); in _decode_opc()
559 tcg_gen_mov_i32(REG(B11_8), REG(B7_4)); in _decode_opc()
[all …]
/openbmc/u-boot/drivers/video/
H A Dtda19988.c19 #define REG(page, addr) (((page) << 8) | (addr)) macro
27 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
28 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
35 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
36 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
39 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
40 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
44 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
48 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
49 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
[all …]
/openbmc/u-boot/drivers/i2c/
H A Ddavinci_i2c.c34 REG(&(i2c_base->i2c_con)) = 0;\
43 REG(&(i2c_base->i2c_stat)) = 0xffff; in _wait_for_bus()
46 stat = REG(&(i2c_base->i2c_stat)); in _wait_for_bus()
48 REG(&(i2c_base->i2c_stat)) = 0xffff; in _wait_for_bus()
52 REG(&(i2c_base->i2c_stat)) = stat; in _wait_for_bus()
56 REG(&(i2c_base->i2c_stat)) = 0xffff; in _wait_for_bus()
66 stat = REG(&(i2c_base->i2c_stat)); in _poll_i2c_irq()
71 REG(&(i2c_base->i2c_stat)) = 0xffff; in _poll_i2c_irq()
78 if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY)) in _flush_rx()
81 REG(&(i2c_base->i2c_drr)); in _flush_rx()
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/
H A Dpsc.c129 if (REG(PSC_PDSTAT1) & 0x1f) in dsp_on()
132 REG(PSC_GBLCTL) |= 0x01; in dsp_on()
133 REG(PSC_PDCTL1) |= 0x01; in dsp_on()
134 REG(PSC_PDCTL1) &= ~0x100; in dsp_on()
135 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; in dsp_on()
136 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; in dsp_on()
137 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; in dsp_on()
138 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; in dsp_on()
139 REG(PSC_PTCMD) = 0x02; in dsp_on()
142 if (REG(PSC_EPCPR) & 0x02) in dsp_on()
[all …]
H A Ddm644x.c28 REG(UART0_PWREMU_MGMT) = 0x00006001; in davinci_enable_uart0()
31 REG(PINMUX1) |= PINMUX1_UART0; in davinci_enable_uart0()
42 REG(VDD3P3V_PWDN) = 0; in davinci_enable_emac()
45 REG(PINMUX0) |= PINMUX0_EMACEN; in davinci_enable_emac()
55 REG(PINMUX1) |= PINMUX1_I2C; in davinci_enable_i2c()
66 REG(PSC_SILVER_BULLET) = 0; in davinci_errata_workarounds()
79 REG(VBPR) = 0x20; in davinci_errata_workarounds()
H A Ddm355.c17 REG(UART0_PWREMU_MGMT) = 0x00006001; in davinci_enable_uart0()
27 REG(PINMUX3) |= (1 << 20) | (1 << 19); in davinci_enable_i2c()
/openbmc/qemu/tests/tcg/i386/
H A Dtest-i386-adcox.c10 #define REG uint64_t macro
12 #define REG uint32_t macro
15 void test_adox_adcx(uint32_t in_c, uint32_t in_o, REG adcx_operand, REG adox_operand) in test_adox_adcx()
17 REG flags; in test_adox_adcx()
18 REG out_adcx, out_adox; in test_adox_adcx()
32 : "r" ((REG) - 1), "0" (flags), "1" (out_adcx), "2" (out_adox)); in test_adox_adcx()
40 void test_adcx_adox(uint32_t in_c, uint32_t in_o, REG adcx_operand, REG adox_operand) in test_adcx_adox()
42 REG flags; in test_adcx_adox()
43 REG out_adcx, out_adox; in test_adcx_adox()
57 : "r" ((REG)-1)); in test_adcx_adox()
/openbmc/qemu/tests/tcg/s390x/
H A Dex-relative-long.c27 #define REG 0x1234567887654321 macro
37 F(cgfrl, REG, MEM, 2) \
38 F(cghrl, REG, MEM, 2) \
39 F(cgrl, REG, MEM, 2) \
40 F(chrl, REG, MEM, 1) \
41 F(clgfrl, REG, MEM, 2) \
42 F(clghrl, REG, MEM, 2) \
43 F(clgrl, REG, MEM, 1) \
44 F(clhrl, REG, MEM, 2) \
45 F(clrl, REG, MEM, 1) \
[all …]
/openbmc/qemu/target/tricore/
H A Dhelper.c153 #define FIELD_GETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \ argument
157 return FIELD_EX32(env->REG, REG, FIELD ## _ ## FEATURE); \
159 return FIELD_EX32(env->REG, REG, FIELD ## _13); \
162 #define FIELD_GETTER(NAME, REG, FIELD) \ argument
165 return FIELD_EX32(env->REG, REG, FIELD); \
168 #define FIELD_SETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \ argument
172 env->REG = FIELD_DP32(env->REG, REG, FIELD ## _ ## FEATURE, val); \
174 env->REG = FIELD_DP32(env->REG, REG, FIELD ## _13, val); \
177 #define FIELD_SETTER(NAME, REG, FIELD) \ argument
180 env->REG = FIELD_DP32(env->REG, REG, FIELD, val); \
/openbmc/qemu/linux-headers/asm-loongarch/
H A Dkvm.h92 #define LOONGARCH_REG_64(TYPE, REG) (TYPE | KVM_REG_SIZE_U64 | (REG << LOONGARCH_REG_SHIFT)) argument
93 #define KVM_IOC_CSRID(REG) LOONGARCH_REG_64(KVM_REG_LOONGARCH_CSR, REG) argument
94 #define KVM_IOC_CPUCFG(REG) LOONGARCH_REG_64(KVM_REG_LOONGARCH_CPUCFG, REG) argument
/openbmc/qemu/target/hexagon/
H A Dmacros.h200 #define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \ argument
201 REG = ((WIDTH) ? deposit64(REG, (OFFSET), (WIDTH), (INVAL)) : REG)
427 #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM) argument
428 #define fEA_RRs(REG, REG2, SCALE) \ argument
432 tcg_gen_add_tl(EA, REG, tmp); \
434 #define fEA_IRs(IMM, REG, SCALE) \ argument
436 tcg_gen_shli_tl(EA, REG, SCALE); \
440 #define fEA_RI(REG, IMM) \ argument
442 EA = REG + IMM; \
444 #define fEA_RRs(REG, REG2, SCALE) \ argument
[all …]
/openbmc/qemu/target/hexagon/idef-parser/
H A Dmacros.h.inc107 #define fEA_RI(REG, IMM) (EA = REG + IMM)
108 #define fEA_RRs(REG, REG2, SCALE) (EA = REG + (REG2 << SCALE))
109 #define fEA_IRs(IMM, REG, SCALE) (EA = IMM + (REG << SCALE))
111 #define fEA_REG(REG) (EA = REG)
112 #define fEA_BREVR(REG) (EA = fbrev(REG))
114 #define fPM_I(REG, IMM) (REG = REG + IMM)
115 #define fPM_M(REG, MVAL) (REG = REG + MVAL)
/openbmc/qemu/target/loongarch/
H A Dcpu.h55 #define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE) argument
56 #define SET_FP_CAUSE(REG, V) \ argument
58 (REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \
60 #define UPDATE_FP_CAUSE(REG, V) \ argument
62 (REG) |= FIELD_DP32(0, FCSR0, CAUSE, V); \
65 #define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES) argument
66 #define SET_FP_ENABLES(REG, V) \ argument
68 (REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \
71 #define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS) argument
72 #define SET_FP_FLAGS(REG, V) \ argument
[all …]
/openbmc/qemu/hw/net/
H A Dnpcm7xx_emc.c59 #define REG(name) case REG_ ## name: return #name; in emc_reg_name() macro
61 REG(CAMCMR) in emc_reg_name()
62 REG(CAMEN) in emc_reg_name()
63 REG(TXDLSA) in emc_reg_name()
64 REG(RXDLSA) in emc_reg_name()
65 REG(MCMDR) in emc_reg_name()
66 REG(MIID) in emc_reg_name()
67 REG(MIIDA) in emc_reg_name()
68 REG(FFTCR) in emc_reg_name()
69 REG(TSDR) in emc_reg_name()
[all …]
/openbmc/u-boot/lib/dhry/
H A Ddhry_2.c45 #ifndef REG
46 #define REG macro
120 REG One_Fifty Int_Index;
121 REG One_Fifty Int_Loc;
168 REG One_Thirty Int_Loc;
H A Ddhry_1.c71 #ifndef REG
73 #define REG macro
99 void Proc_1 (REG Rec_Pointer Ptr_Val_Par);
116 REG One_Fifty Int_2_Loc; in dhry()
118 REG char Ch_Index; in dhry()
327 void Proc_1 (REG Rec_Pointer Ptr_Val_Par) in Proc_1()
330 REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; in Proc_1()
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-benchmark/dhrystone/dhrystone-2.1/
H A Ddhrystone-c89.patch52 +void Proc_1 (REG Rec_Pointer Ptr_Val_Par);
94 +void Proc_1 (REG Rec_Pointer Ptr_Val_Par)
97 -REG Rec_Pointer Ptr_Val_Par;
100 REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;
101 @@ -318,12 +320,10 @@ REG Rec_Pointer Ptr_Val_Par;
212 REG One_Fifty Int_Index;
213 REG One_Fifty Int_Loc;
228 REG One_Thirty Int_Loc;
/openbmc/u-boot/include/
H A Dsym53c8xx.h222 #define REG(r) (r) macro
388 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
391 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
394 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
460 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
463 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dap.h20 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) argument
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dpinmux-common.c95 #define REG(pin) _R(0x3000 + ((pin) * 4)) macro
97 #define MUX_REG(pin) REG(pin)
100 #define PULL_REG(pin) REG(pin)
103 #define TRI_REG(pin) REG(pin)
234 u32 *reg = REG(pin); in pinmux_set_io()
256 u32 *reg = REG(pin); in pinmux_set_lock()
283 u32 *reg = REG(pin); in pinmux_set_od()
308 u32 *reg = REG(pin); in pinmux_set_ioreset()
333 u32 *reg = REG(pin); in pinmux_set_rcv_sel()
358 u32 *reg = REG(pin); in pinmux_set_e_io_hv()
[all …]
H A Dcpu.h31 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) argument
/openbmc/qemu/tests/qtest/
H A Dtpm-util.h20 #define TIS_REG(LOCTY, REG) \ argument
21 (tpm_tis_base_addr + ((LOCTY) << 12) + REG)
/openbmc/u-boot/drivers/net/
H A Dmcfmii.c31 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ argument
32 (REG & 0x1f) << 18))
33 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ argument
34 (REG & 0x1f) << 18) | (VAL & 0xffff))
/openbmc/qemu/target/hexagon/imported/
H A Dmacros.def71 …REG = ((REG) & ~(((fCONSTLL(1)<<(WIDTH))-1)<<(OFFSET))) | (((INVAL) & ((fCONSTLL(1)<<(WIDTH))-1)) …
870 do { EA=REG+IMM; fDOCHKPAGECROSS(REG,EA); } while (0),
876 do { EA=REG+(REG2<<SCALE); fDOCHKPAGECROSS(REG,EA); } while (0),
882 do { EA=IMM+(REG<<SCALE); fDOCHKPAGECROSS(IMM,EA); } while (0),
894 EA=REG,
900 EA=fbrev(REG),
912 do { REG = REG + IMM; } while (0),
918 do { REG = REG + MVAL; } while (0),
924 do { fcirc_add(REG,siV,MuV); } while (0),
930 do { fcirc_add(REG,VAL,MuV); } while (0),
[all …]
/openbmc/qemu/target/hexagon/mmvec/
H A Dmacros.h70 #define fGETQBITS(REG, WIDTH, MASK, BITNO) \ argument
71 ((MASK) & (REG.w[(BITNO) >> 5] >> ((BITNO) & 0x1f)))
72 #define fGETQBIT(REG, BITNO) fGETQBITS(REG, 1, 1, BITNO) argument
96 #define fSETQBITS(REG, WIDTH, MASK, BITNO, VAL) \ argument
99 REG.w[(BITNO) >> 5] &= ~((MASK) << ((BITNO) & 0x1f)); \
100 REG.w[(BITNO) >> 5] |= (((__TMP) & (MASK)) << ((BITNO) & 0x1f)); \
102 #define fSETQBIT(REG, BITNO, VAL) fSETQBITS(REG, 1, 1, BITNO, VAL) argument

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