1/*
2 *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
3 *
4 *  This program is free software; you can redistribute it and/or modify
5 *  it under the terms of the GNU General Public License as published by
6 *  the Free Software Foundation; either version 2 of the License, or
7 *  (at your option) any later version.
8 *
9 *  This program is distributed in the hope that it will be useful,
10 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
11 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 *  GNU General Public License for more details.
13 *
14 *  You should have received a copy of the GNU General Public License
15 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18DEF_MACRO(
19    LIKELY,    /* NAME */
20    __builtin_expect((X),1), /* BEH */
21    ()    /* attribs */
22)
23
24DEF_MACRO(
25    UNLIKELY,    /* NAME */
26    __builtin_expect((X),0), /* BEH */
27    ()    /* attribs */
28)
29
30DEF_MACRO(
31    CANCEL, /* macro name */
32    {if (thread->last_pkt) thread->last_pkt->slot_cancelled |= (1<<insn->slot); return;} , /* behavior */
33    (A_CONDEXEC)
34)
35
36DEF_MACRO(
37    LOAD_CANCEL, /* macro name */
38    {mem_general_load_cancelled(thread,EA,insn);CANCEL;} , /* behavior */
39    (A_CONDEXEC)
40)
41
42DEF_MACRO(
43    STORE_CANCEL, /* macro name */
44    {mem_general_store_cancelled(thread,EA,insn);CANCEL;} , /* behavior */
45    (A_CONDEXEC)
46)
47
48DEF_MACRO(
49    fMAX, /* macro name */
50    (((A) > (B)) ? (A) : (B)), /* behavior */
51    /* optional attributes */
52)
53
54DEF_MACRO(
55    fMIN, /* macro name */
56    (((A) < (B)) ? (A) : (B)), /* behavior */
57    /* optional attributes */
58)
59
60DEF_MACRO(
61    fABS, /* macro name */
62    (((A)<0)?(-(A)):(A)), /* behavior */
63    /* optional attributes */
64)
65
66
67/* Bit insert */
68DEF_MACRO(
69    fINSERT_BITS,
70        {
71            REG = ((REG) & ~(((fCONSTLL(1)<<(WIDTH))-1)<<(OFFSET))) | (((INVAL) & ((fCONSTLL(1)<<(WIDTH))-1)) << (OFFSET));
72        },
73    /* attribs */
74)
75
76/* Bit extract */
77DEF_MACRO(
78    fEXTRACTU_BITS,
79    (fZXTN(WIDTH,32,(INREG >> OFFSET))),
80    /* attribs */
81)
82
83DEF_MACRO(
84    fEXTRACTU_BIDIR,
85    (fZXTN(WIDTH,32,fBIDIR_LSHIFTR((INREG),(OFFSET),4_8))),
86    /* attribs */
87)
88
89DEF_MACRO(
90    fEXTRACTU_RANGE,
91    (fZXTN((HIBIT-LOWBIT+1),32,(INREG >> LOWBIT))),
92    /* attribs */
93)
94
95
96DEF_MACRO(
97    fINSERT_RANGE,
98        {
99            int offset=LOWBIT;
100            int width=HIBIT-LOWBIT+1;
101            /* clear bits where new bits go */
102            INREG &= ~(((fCONSTLL(1)<<width)-1)<<offset);
103            /* OR in new bits */
104            INREG |= ((INVAL & ((fCONSTLL(1)<<width)-1)) << offset);
105        },
106    /* attribs */
107)
108
109
110DEF_MACRO(
111    f8BITSOF,
112    ( (VAL) ? 0xff : 0x00),
113    /* attribs */
114)
115
116DEF_MACRO(
117    fLSBOLD,
118    ((VAL) & 1),
119    ()
120)
121
122DEF_MACRO(
123    fLSBNEW,
124    predlog_read(thread,PNUM),
125    ()
126)
127
128DEF_MACRO(
129    fLSBNEW0,
130    predlog_read(thread,0),
131    ()
132)
133
134DEF_MACRO(
135    fLSBNEW1,
136    predlog_read(thread,1),
137    ()
138)
139
140DEF_MACRO(
141    fLSBOLDNOT,
142    (!fLSBOLD(VAL)),
143    ()
144)
145
146DEF_MACRO(
147    fLSBNEWNOT,
148    (!fLSBNEW(PNUM)),
149    ()
150)
151
152DEF_MACRO(
153    fLSBNEW0NOT,
154    (!fLSBNEW0),
155    ()
156)
157
158DEF_MACRO(
159    fLSBNEW1NOT,
160    (!fLSBNEW1),
161    ()
162)
163
164DEF_MACRO(
165    fNEWREG,
166    ({if (newvalue_missing(thread,RNUM) ||
167      IS_CANCELLED(insn->new_value_producer_slot)) CANCEL; reglog_read(thread,RNUM);}),
168    (A_DOTNEWVALUE,A_RESTRICT_SLOT0ONLY)
169)
170// Store new with a missing newvalue or cancelled goes out as a zero byte store in V65
171// take advantage of the fact that reglog_read returns zero for not valid rnum
172DEF_MACRO(
173    fNEWREG_ST,
174    ({if (newvalue_missing(thread,RNUM) ||
175      IS_CANCELLED(insn->new_value_producer_slot)) { STORE_ZERO; RNUM = -1; }; reglog_read(thread,RNUM);}),
176    (A_DOTNEWVALUE,A_RESTRICT_SLOT0ONLY)
177)
178
179DEF_MACRO(
180    fVSATUVALN,
181    ({ ((VAL) < 0) ? 0 : ((1LL<<(N))-1);}),
182    ()
183)
184
185DEF_MACRO(
186    fSATUVALN,
187    ({fSET_OVERFLOW(); ((VAL) < 0) ? 0 : ((1LL<<(N))-1);}),
188    ()
189)
190
191DEF_MACRO(
192    fSATVALN,
193    ({fSET_OVERFLOW(); ((VAL) < 0) ? (-(1LL<<((N)-1))) : ((1LL<<((N)-1))-1);}),
194    ()
195)
196
197DEF_MACRO(
198    fVSATVALN,
199    ({((VAL) < 0) ? (-(1LL<<((N)-1))) : ((1LL<<((N)-1))-1);}),
200    ()
201)
202
203DEF_MACRO(
204    fZXTN, /* macro name */
205    ((VAL) & ((1LL<<(N))-1)),
206    /* attribs */
207)
208
209DEF_MACRO(
210    fSXTN, /* macro name */
211    ((fZXTN(N,M,VAL) ^ (1LL<<((N)-1))) - (1LL<<((N)-1))),
212    /* attribs */
213)
214
215DEF_MACRO(
216    fSATN,
217    ((fSXTN(N,64,VAL) == (VAL)) ? (VAL) : fSATVALN(N,VAL)),
218    ()
219)
220DEF_MACRO(
221    fVSATN,
222    ((fSXTN(N,64,VAL) == (VAL)) ? (VAL) : fVSATVALN(N,VAL)),
223    ()
224)
225
226DEF_MACRO(
227    fADDSAT64,
228    {
229        size8u_t __a = fCAST8u(A);
230        size8u_t __b = fCAST8u(B);
231        size8u_t __sum = __a + __b;
232        size8u_t __xor = __a ^ __b;
233        const size8u_t __mask = 0x8000000000000000ULL;
234        if (__xor & __mask) {
235            /* Opposite signs, OK */
236            DST = __sum;
237        } else if ((__a ^ __sum) & __mask) {
238            /* Signs mismatch */
239            if (__sum & __mask) {
240                /* overflowed to negative, make max pos */
241                DST=0x7FFFFFFFFFFFFFFFLL; fSET_OVERFLOW();
242            } else {
243                /* overflowed to positive, make max neg */
244                DST=0x8000000000000000LL; fSET_OVERFLOW();
245            }
246        } else {
247            /* signs did not mismatch, OK */
248            DST = __sum;
249        }
250    },
251    ()
252)
253
254DEF_MACRO(
255    fVSATUN,
256    ((fZXTN(N,64,VAL) == (VAL)) ? (VAL) : fVSATUVALN(N,VAL)),
257    ()
258)
259
260DEF_MACRO(
261    fSATUN,
262    ((fZXTN(N,64,VAL) == (VAL)) ? (VAL) : fSATUVALN(N,VAL)),
263    ()
264)
265
266DEF_MACRO(
267    fSATH,
268    (fSATN(16,VAL)),
269    ()
270)
271
272
273DEF_MACRO(
274    fSATUH,
275    (fSATUN(16,VAL)),
276    ()
277)
278
279DEF_MACRO(
280    fVSATH,
281    (fVSATN(16,VAL)),
282    ()
283)
284
285DEF_MACRO(
286    fVSATUH,
287    (fVSATUN(16,VAL)),
288    ()
289)
290
291
292DEF_MACRO(
293    fSATUB,
294    (fSATUN(8,VAL)),
295    ()
296)
297DEF_MACRO(
298    fSATB,
299    (fSATN(8,VAL)),
300    ()
301)
302
303
304DEF_MACRO(
305    fVSATUB,
306    (fVSATUN(8,VAL)),
307    ()
308)
309DEF_MACRO(
310    fVSATB,
311    (fVSATN(8,VAL)),
312    ()
313)
314
315
316
317
318/*************************************/
319/* immediate extension               */
320/*************************************/
321
322DEF_MACRO(
323    fIMMEXT,
324    (IMM = IMM),
325    (A_EXTENDABLE)
326)
327
328DEF_MACRO(
329    fMUST_IMMEXT,
330    fIMMEXT(IMM),
331    (A_EXTENDABLE)
332)
333
334DEF_MACRO(
335    fPCALIGN,
336    IMM=(IMM & ~PCALIGN_MASK),
337    (A_EXTENDABLE)
338)
339
340/*************************************/
341/* Read and Write Implicit Regs      */
342/*************************************/
343
344DEF_MACRO(
345    fREAD_IREG, /* read modifier register */
346    (fSXTN(11,64,(((VAL) & 0xf0000000)>>21) | ((VAL>>17)&0x7f) )),          /* behavior */
347    ()
348)
349
350DEF_MACRO(
351    fREAD_LR, /* read link register */
352    (READ_RREG(REG_LR)),          /* behavior */
353    ()
354)
355
356DEF_MACRO(
357    fWRITE_LR, /* write lr */
358    WRITE_RREG(REG_LR,A),          /* behavior */
359    (A_IMPLICIT_WRITES_LR)
360)
361
362DEF_MACRO(
363    fWRITE_FP, /* write sp */
364    WRITE_RREG(REG_FP,A),          /* behavior */
365    (A_IMPLICIT_WRITES_FP)
366)
367
368DEF_MACRO(
369    fWRITE_SP, /* write sp */
370    WRITE_RREG(REG_SP,A),          /* behavior */
371    (A_IMPLICIT_WRITES_SP)
372)
373
374DEF_MACRO(
375    fREAD_SP, /* read stack pointer */
376    (READ_RREG(REG_SP)),          /* behavior */
377    ()
378)
379
380DEF_MACRO(
381    fREAD_CSREG, /* read  CS register */
382    (READ_RREG(REG_CSA+N)),          /* behavior */
383    ()
384)
385
386DEF_MACRO(
387    fREAD_LC0, /* read loop count */
388    (READ_RREG(REG_LC0)),          /* behavior */
389    ()
390)
391
392DEF_MACRO(
393    fREAD_LC1, /* read loop count */
394    (READ_RREG(REG_LC1)),          /* behavior */
395    ()
396)
397
398DEF_MACRO(
399    fREAD_SA0, /* read start addr */
400    (READ_RREG(REG_SA0)),          /* behavior */
401    ()
402)
403
404DEF_MACRO(
405    fREAD_SA1, /* read start addr */
406    (READ_RREG(REG_SA1)),          /* behavior */
407    ()
408)
409
410
411DEF_MACRO(
412    fREAD_FP, /* read frame pointer */
413    (READ_RREG(REG_FP)),          /* behavior */
414    ()
415)
416
417DEF_MACRO(
418    fREAD_GP, /* read global pointer */
419    (insn->extension_valid ? 0 : READ_RREG(REG_GP)),          /* behavior */
420    ()
421)
422
423DEF_MACRO(
424    fREAD_PC, /* read PC */
425    (READ_RREG(REG_PC)),          /* behavior */
426    ()
427)
428
429DEF_MACRO(
430    fREAD_NPC, /* read next PC */
431    (thread->next_PC & (0xfffffffe)),          /* behavior */
432    ()
433)
434
435DEF_MACRO(
436    fREAD_P0, /* read Predicate 0 */
437    (READ_PREG(0)),          /* behavior */
438    ()
439)
440
441DEF_MACRO(
442    fREAD_P3, /* read Predicate 3 */
443    (READ_PREG(3)),          /* behavior */
444    ()
445)
446
447DEF_MACRO(
448    fCHECK_PCALIGN,
449    if (((A) & PCALIGN_MASK)) {
450        register_error_exception(thread,PRECISE_CAUSE_PC_NOT_ALIGNED,thread->Regs[REG_BADVA0],thread->Regs[REG_BADVA1],GET_SSR_FIELD(SSR_BVS),GET_SSR_FIELD(SSR_V0),GET_SSR_FIELD(SSR_V1),0);
451    },
452    ()
453)
454
455DEF_MACRO(
456    fWRITE_NPC, /* write next PC */
457    if (!thread->branch_taken) {
458        if (A != thread->next_PC) {
459            thread->next_pkt_guess=thread->last_pkt->taken_ptr;
460        }
461        fCHECK_PCALIGN(A);
462        thread->branched = 1; thread->branch_taken = 1; thread->next_PC = A; \
463        thread->branch_offset = insn->encoding_offset; thread->branch_opcode = insn->opcode;
464    },          /* behavior */
465    (A_COF)
466)
467
468DEF_MACRO(
469    fBRANCH,
470    fWRITE_NPC(LOC); fCOF_CALLBACK(LOC,TYPE),
471    ()
472)
473
474DEF_MACRO(
475    fJUMPR,    /* A jumpr has executed */
476    {fBRANCH(TARGET,COF_TYPE_JUMPR);},
477    (A_INDIRECT)
478)
479
480DEF_MACRO(
481    fHINTJR,    /* A hintjr instruction has executed */
482    { },
483)
484
485DEF_MACRO(
486    fCALL,    /* Do a call */
487    if (!thread->branch_taken) {fBP_RAS_CALL(A); fWRITE_LR(fREAD_NPC()); fBRANCH(A,COF_TYPE_CALL);},
488    (A_COF,A_IMPLICIT_WRITES_LR,A_CALL)
489)
490
491DEF_MACRO(
492    fCALLR,    /* Do a call Register */
493    if (!thread->branch_taken) {fBP_RAS_CALL(A); fWRITE_LR(fREAD_NPC()); fBRANCH(A,COF_TYPE_CALLR);},
494    (A_COF,A_IMPLICIT_WRITES_LR,A_CALL)
495)
496
497DEF_MACRO(
498    fWRITE_LOOP_REGS0, /* write ln,sa,ea,lc */
499    {WRITE_RREG(REG_LC0,COUNT);
500     WRITE_RREG(REG_SA0,START);},
501    (A_IMPLICIT_WRITES_LC0,A_IMPLICIT_WRITES_SA0)
502)
503
504DEF_MACRO(
505    fWRITE_LOOP_REGS1, /* write ln,sa,ea,lc */
506    {WRITE_RREG(REG_LC1,COUNT);
507     WRITE_RREG(REG_SA1,START);},
508    (A_IMPLICIT_WRITES_LC1,A_IMPLICIT_WRITES_SA1)
509)
510
511DEF_MACRO(
512    fWRITE_LC0,
513    WRITE_RREG(REG_LC0,VAL),
514    (A_IMPLICIT_WRITES_LC0)
515)
516
517DEF_MACRO(
518    fWRITE_LC1,
519    WRITE_RREG(REG_LC1,VAL),
520    (A_IMPLICIT_WRITES_LC1)
521)
522
523DEF_MACRO(
524    fCARRY_FROM_ADD,
525    carry_from_add64(A,B,C),
526    /* NOTHING */
527)
528
529DEF_MACRO(
530    fSET_OVERFLOW,
531    SET_USR_FIELD(USR_OVF,1),
532    ()
533)
534
535DEF_MACRO(
536    fSET_LPCFG,
537    SET_USR_FIELD(USR_LPCFG,(VAL)),
538    ()
539)
540
541
542DEF_MACRO(
543    fGET_LPCFG,
544    (GET_USR_FIELD(USR_LPCFG)),
545    ()
546)
547
548
549
550DEF_MACRO(
551    fWRITE_P0, /* write Predicate 0 */
552    WRITE_PREG(0,VAL),          /* behavior */
553    (A_IMPLICIT_WRITES_P0)
554)
555
556DEF_MACRO(
557    fWRITE_P1, /* write Predicate 0 */
558    WRITE_PREG(1,VAL),          /* behavior */
559    (A_IMPLICIT_WRITES_P1)
560)
561
562DEF_MACRO(
563    fWRITE_P2, /* write Predicate 0 */
564    WRITE_PREG(2,VAL),          /* behavior */
565    (A_IMPLICIT_WRITES_P2)
566)
567
568DEF_MACRO(
569    fWRITE_P3, /* write Predicate 0 */
570    WRITE_PREG(3,VAL),     /* behavior */
571    (A_IMPLICIT_WRITES_P3)
572)
573
574DEF_MACRO(
575    fPART1, /* write Predicate 0 */
576    if (insn->part1) { WORK; return; },          /* behavior */
577    /* optional attributes */
578)
579
580
581/*************************************/
582/* Casting, Sign-Zero extension, etc */
583/*************************************/
584
585DEF_MACRO(
586    fCAST4u, /* macro name */
587    ((size4u_t)(A)),          /* behavior */
588    /* optional attributes */
589)
590
591DEF_MACRO(
592    fCAST4s, /* macro name */
593    ((size4s_t)(A)),          /* behavior */
594    /* optional attributes */
595)
596
597DEF_MACRO(
598    fCAST8u, /* macro name */
599    ((size8u_t)(A)),          /* behavior */
600    /* optional attributes */
601)
602
603DEF_MACRO(
604    fCAST8s, /* macro name */
605    ((size8s_t)(A)),          /* behavior */
606    /* optional attributes */
607)
608
609DEF_MACRO(
610    fCAST2_2s, /* macro name */
611    ((size2s_t)(A)),
612    /* optional attributes */
613)
614
615DEF_MACRO(
616    fCAST2_2u, /* macro name */
617    ((size2u_t)(A)),
618    /* optional attributes */
619)
620
621DEF_MACRO(
622    fCAST4_4s, /* macro name */
623    ((size4s_t)(A)),
624    /* optional attributes */
625)
626
627DEF_MACRO(
628    fCAST4_4u, /* macro name */
629    ((size4u_t)(A)),
630    /* optional attributes */
631)
632
633
634DEF_MACRO(
635    fCAST4_8s, /* macro name */
636    ((size8s_t)((size4s_t)(A))),
637    /* optional attributes */
638)
639
640DEF_MACRO(
641    fCAST4_8u, /* macro name */
642    ((size8u_t)((size4u_t)(A))),
643    /* optional attributes */
644)
645
646DEF_MACRO(
647    fCAST8_8s, /* macro name */
648    ((size8s_t)(A)),
649    /* optional attributes */
650)
651
652DEF_MACRO(
653    fCAST8_8u, /* macro name */
654    ((size8u_t)(A)),
655    /* optional attributes */
656)
657
658DEF_MACRO(
659    fCAST2_8s, /* macro name */
660    ((size8s_t)((size2s_t)(A))),
661    /* optional attributes */
662)
663DEF_MACRO(
664    fCAST2_8u, /* macro name */
665    ((size8u_t)((size2u_t)(A))),
666    /* optional attributes */
667)
668
669DEF_MACRO(
670    fZE8_16, /* zero-extend 8 to 16 */
671    ((size2s_t)((size1u_t)(A))),
672    /* optional attributes */
673)
674DEF_MACRO(
675    fSE8_16, /* sign-extend 8 to 16 */
676    ((size2s_t)((size1s_t)(A))),
677    /* optional attributes */
678)
679
680
681DEF_MACRO(
682    fSE16_32, /* sign-extend 16 to 32 */
683    ((size4s_t)((size2s_t)(A))),          /* behavior */
684    /* optional attributes */
685)
686
687DEF_MACRO(
688    fZE16_32, /* zero-extend 16 to 32 */
689    ((size4u_t)((size2u_t)(A))),          /* behavior */
690    /* optional attributes */
691)
692
693DEF_MACRO(
694    fSE32_64,
695    ( (size8s_t)((size4s_t)(A)) ),          /* behavior */
696    /* optional attributes */
697)
698
699DEF_MACRO(
700    fZE32_64,
701    ( (size8u_t)((size4u_t)(A)) ),          /* behavior */
702    /* optional attributes */
703)
704
705DEF_MACRO(
706    fSE8_32, /* sign-extend 8 to 32 */
707    ((size4s_t)((size1s_t)(A))),
708    /* optional attributes */
709)
710
711DEF_MACRO(
712    fZE8_32, /* zero-extend 8 to 32 */
713    ((size4s_t)((size1u_t)(A))),
714    /* optional attributes */
715)
716
717/*************************************/
718/* DSP arithmetic support            */
719/************************************/
720DEF_MACRO(
721    fMPY8UU, /* multiply half integer */
722    (int)(fZE8_16(A)*fZE8_16(B)),     /* behavior */
723    ()
724)
725DEF_MACRO(
726    fMPY8US, /* multiply half integer */
727    (int)(fZE8_16(A)*fSE8_16(B)),     /* behavior */
728    ()
729)
730DEF_MACRO(
731    fMPY8SU, /* multiply half integer */
732    (int)(fSE8_16(A)*fZE8_16(B)),     /* behavior */
733    ()
734)
735
736DEF_MACRO(
737    fMPY8SS, /* multiply half integer */
738    (int)((short)(A)*(short)(B)),     /* behavior */
739    ()
740)
741
742DEF_MACRO(
743    fMPY16SS, /* multiply half integer */
744    fSE32_64(fSE16_32(A)*fSE16_32(B)),     /* behavior */
745    ()
746)
747
748DEF_MACRO(
749    fMPY16UU, /* multiply unsigned half integer */
750    fZE32_64(fZE16_32(A)*fZE16_32(B)),     /* behavior */
751    ()
752)
753
754DEF_MACRO(
755    fMPY16SU, /* multiply half integer */
756    fSE32_64(fSE16_32(A)*fZE16_32(B)),     /* behavior */
757    ()
758)
759
760DEF_MACRO(
761    fMPY16US, /* multiply half integer */
762    fMPY16SU(B,A),
763    ()
764)
765
766DEF_MACRO(
767    fMPY32SS, /* multiply half integer */
768    (fSE32_64(A)*fSE32_64(B)),     /* behavior */
769    ()
770)
771
772DEF_MACRO(
773    fMPY32UU, /* multiply half integer */
774    (fZE32_64(A)*fZE32_64(B)),     /* behavior */
775    ()
776)
777
778DEF_MACRO(
779    fMPY32SU, /* multiply half integer */
780    (fSE32_64(A)*fZE32_64(B)),     /* behavior */
781    ()
782)
783
784DEF_MACRO(
785    fMPY3216SS, /* multiply mixed precision */
786    (fSE32_64(A)*fSXTN(16,64,B)),     /* behavior */
787    ()
788)
789
790DEF_MACRO(
791    fMPY3216SU, /* multiply mixed precision */
792    (fSE32_64(A)*fZXTN(16,64,B)),     /* behavior */
793    ()
794)
795
796DEF_MACRO(
797    fROUND, /* optional rounding */
798    (A+0x8000),
799    /* optional attributes */
800)
801
802DEF_MACRO(
803    fCLIP, /* optional rounding */
804    { size4s_t maxv = (1<<U)-1;
805      size4s_t minv = -(1<<U);
806      DST = fMIN(maxv,fMAX(SRC,minv));
807    },
808    /* optional attributes */
809)
810
811DEF_MACRO(
812    fCRND, /* optional rounding */
813    ((((A)&0x3)==0x3)?((A)+1):((A))),
814    /* optional attributes */
815)
816
817DEF_MACRO(
818    fRNDN, /* Rounding to a boundary */
819    ((((N)==0)?(A):(((fSE32_64(A))+(1<<((N)-1)))))),
820    /* optional attributes */
821)
822
823DEF_MACRO(
824    fCRNDN, /* Rounding to a boundary */
825    (conv_round(A,N)),
826    /* optional attributes */
827)
828
829DEF_MACRO(
830    fADD128, /* Rounding to a boundary */
831    (add128(A, B)),
832    /* optional attributes */
833)
834DEF_MACRO(
835    fSUB128, /* Rounding to a boundary */
836    (sub128(A, B)),
837    /* optional attributes */
838)
839DEF_MACRO(
840    fSHIFTR128, /* Rounding to a boundary */
841    (shiftr128(A, B)),
842    /* optional attributes */
843)
844
845DEF_MACRO(
846    fSHIFTL128, /* Rounding to a boundary */
847    (shiftl128(A, B)),
848    /* optional attributes */
849)
850
851DEF_MACRO(
852    fAND128, /* Rounding to a boundary */
853    (and128(A, B)),
854    /* optional attributes */
855)
856
857DEF_MACRO(
858    fCAST8S_16S, /* Rounding to a boundary */
859    (cast8s_to_16s(A)),
860    /* optional attributes */
861)
862DEF_MACRO(
863    fCAST16S_8S, /* Rounding to a boundary */
864    (cast16s_to_8s(A)),
865    /* optional attributes */
866)
867
868DEF_MACRO(
869    fEA_RI, /* Calculate EA with Register + Immediate Offset */
870    do { EA=REG+IMM; fDOCHKPAGECROSS(REG,EA); } while (0),
871    ()
872)
873
874DEF_MACRO(
875    fEA_RRs, /* Calculate EA with Register + Registers scaled Offset */
876    do { EA=REG+(REG2<<SCALE); fDOCHKPAGECROSS(REG,EA); } while (0),
877    ()
878)
879
880DEF_MACRO(
881    fEA_IRs, /* Calculate EA with Immediate + Registers scaled Offset */
882    do { EA=IMM+(REG<<SCALE); fDOCHKPAGECROSS(IMM,EA); } while (0),
883    ()
884)
885
886DEF_MACRO(
887    fEA_IMM, /* Calculate EA with Immediate */
888    EA=IMM,
889    ()
890)
891
892DEF_MACRO(
893    fEA_REG, /* Calculate EA with REGISTER */
894    EA=REG,
895    ()
896)
897
898DEF_MACRO(
899    fEA_BREVR, /* Calculate EA with bit reversed bottom of REGISTER */
900    EA=fbrev(REG),
901    ()
902)
903
904DEF_MACRO(
905    fEA_GPI, /* Calculate EA with Global Pointer + Immediate */
906    do { EA=fREAD_GP()+IMM; fGP_DOCHKPAGECROSS(fREAD_GP(),EA); } while (0),
907    ()
908)
909
910DEF_MACRO(
911    fPM_I, /* Post Modify Register by Immediate*/
912    do { REG = REG + IMM; } while (0),
913    ()
914)
915
916DEF_MACRO(
917    fPM_M, /* Post Modify Register by M register */
918    do { REG = REG + MVAL; } while (0),
919    ()
920)
921
922DEF_MACRO(
923    fPM_CIRI, /* Post Modify Register using Circular arithmetic by Immediate */
924    do { fcirc_add(REG,siV,MuV); } while (0),
925    ()
926)
927
928DEF_MACRO(
929    fPM_CIRR, /* Post Modify Register using Circular arithmetic by register */
930    do { fcirc_add(REG,VAL,MuV); } while (0),
931    ()
932)
933
934
935
936DEF_MACRO(
937    fSCALE, /* scale by N */
938    (((size8s_t)(A))<<N),
939    /* optional attributes */
940)
941DEF_MACRO(
942    fVSATW, /* saturating to 32-bits*/
943    fVSATN(32,((long long)A)),
944    ()
945)
946
947DEF_MACRO(
948    fSATW, /* saturating to 32-bits*/
949    fSATN(32,((long long)A)),
950    ()
951)
952
953DEF_MACRO(
954    fVSAT, /* saturating to 32-bits*/
955    fVSATN(32,(A)),
956    ()
957)
958
959DEF_MACRO(
960    fSAT, /* saturating to 32-bits*/
961    fSATN(32,(A)),
962    ()
963)
964
965DEF_MACRO(
966    fSAT_ORIG_SHL, /* Saturating to 32-bits, with original value, for shift left */
967    ((((size4s_t)((fSAT(A)) ^ ((size4s_t)(ORIG_REG)))) < 0) ?
968        fSATVALN(32,((size4s_t)(ORIG_REG))) :
969        ((((ORIG_REG) > 0) && ((A) == 0)) ?
970            fSATVALN(32,(ORIG_REG)) :
971            fSAT(A))),
972    ()
973)
974
975DEF_MACRO(
976    fPASS,
977    A,
978)
979
980DEF_MACRO(
981    fRND, /* saturating to 32-bits*/
982    (((A)+1)>>1),
983)
984
985
986DEF_MACRO(
987    fBIDIR_SHIFTL,
988    (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT))-1)) >>1) : (fCAST##REGSTYPE(SRC) << (SHAMT))),
989    ()
990)
991
992DEF_MACRO(
993    fBIDIR_ASHIFTL,
994    fBIDIR_SHIFTL(SRC,SHAMT,REGSTYPE##s),
995    ()
996)
997
998DEF_MACRO(
999    fBIDIR_LSHIFTL,
1000    fBIDIR_SHIFTL(SRC,SHAMT,REGSTYPE##u),
1001    ()
1002)
1003
1004DEF_MACRO(
1005    fBIDIR_ASHIFTL_SAT,
1006    (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT))-1)) >>1) : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT),(SRC))),
1007    ()
1008)
1009
1010
1011DEF_MACRO(
1012    fBIDIR_SHIFTR,
1013    (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT))-1)) << 1) : (fCAST##REGSTYPE(SRC) >> (SHAMT))),
1014    ()
1015)
1016
1017DEF_MACRO(
1018    fBIDIR_ASHIFTR,
1019    fBIDIR_SHIFTR(SRC,SHAMT,REGSTYPE##s),
1020    ()
1021)
1022
1023DEF_MACRO(
1024    fBIDIR_LSHIFTR,
1025    fBIDIR_SHIFTR(SRC,SHAMT,REGSTYPE##u),
1026    ()
1027)
1028
1029DEF_MACRO(
1030    fBIDIR_ASHIFTR_SAT,
1031    (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) << ((-(SHAMT))-1)) << 1,(SRC)) : (fCAST##REGSTYPE##s(SRC) >> (SHAMT))),
1032    ()
1033)
1034
1035DEF_MACRO(
1036    fASHIFTR,
1037    (fCAST##REGSTYPE##s(SRC) >> (SHAMT)),
1038    /* */
1039)
1040
1041DEF_MACRO(
1042    fLSHIFTR,
1043    (((SHAMT) >= 64)?0:(fCAST##REGSTYPE##u(SRC) >> (SHAMT))),
1044    /* */
1045)
1046
1047DEF_MACRO(
1048    fROTL,
1049    (((SHAMT)==0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \
1050        ((fCAST##REGSTYPE##u(SRC) >> ((sizeof(SRC)*8)-(SHAMT)))))),
1051    /* */
1052)
1053
1054DEF_MACRO(
1055    fROTR,
1056    (((SHAMT)==0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \
1057        ((fCAST##REGSTYPE##u(SRC) << ((sizeof(SRC)*8)-(SHAMT)))))),
1058    /* */
1059)
1060
1061DEF_MACRO(
1062    fASHIFTL,
1063    (((SHAMT) >= 64)?0:(fCAST##REGSTYPE##s(SRC) << (SHAMT))),
1064    /* */
1065)
1066
1067/*************************************/
1068/* Floating-Point Support            */
1069/************************************/
1070
1071DEF_MACRO(
1072    fFLOAT, /* name */
1073    ({ union { float f; size4u_t i; } _fipun; _fipun.i = (A); _fipun.f; }),     /* behavior */
1074    (A_FPOP)
1075)
1076
1077DEF_MACRO(
1078    fUNFLOAT, /* multiply half integer */
1079    ({ union { float f; size4u_t i; } _fipun; _fipun.f = (A); isnan(_fipun.f) ? 0xFFFFFFFFU : _fipun.i; }),     /* behavior */
1080    (A_FPOP)
1081)
1082
1083DEF_MACRO(
1084    fSFNANVAL,
1085    0xffffffff,
1086    ()
1087)
1088
1089DEF_MACRO(
1090    fSFINFVAL,
1091    (((A) & 0x80000000) | 0x7f800000),
1092    ()
1093)
1094
1095DEF_MACRO(
1096    fSFONEVAL,
1097    (((A) & 0x80000000) | fUNFLOAT(1.0)),
1098    ()
1099)
1100
1101DEF_MACRO(
1102    fCHECKSFNAN,
1103    do {
1104        if (isnan(fFLOAT(A))) {
1105            if ((fGETBIT(22,A)) == 0) fRAISEFLAGS(FE_INVALID);
1106            DST = fSFNANVAL();
1107        }
1108    } while (0),
1109    ()
1110)
1111
1112DEF_MACRO(
1113    fCHECKSFNAN3,
1114    do {
1115        fCHECKSFNAN(DST,A);
1116        fCHECKSFNAN(DST,B);
1117        fCHECKSFNAN(DST,C);
1118    } while (0),
1119    ()
1120)
1121
1122DEF_MACRO(
1123    fSF_BIAS,
1124    127,
1125    ()
1126)
1127
1128DEF_MACRO(
1129    fSF_MANTBITS,
1130    23,
1131    ()
1132)
1133
1134DEF_MACRO(
1135    fSF_MUL_POW2,
1136    (fUNFLOAT(fFLOAT(A) * fFLOAT((fSF_BIAS() + (B)) << fSF_MANTBITS()))),
1137    ()
1138)
1139
1140DEF_MACRO(
1141    fSF_GETEXP,
1142    (((A) >> fSF_MANTBITS()) & 0xff),
1143    ()
1144)
1145
1146DEF_MACRO(
1147    fSF_MAXEXP,
1148    (254),
1149    ()
1150)
1151
1152DEF_MACRO(
1153    fSF_RECIP_COMMON,
1154    arch_sf_recip_common(&N,&D,&O,&A),
1155    (A_FPOP)
1156)
1157
1158DEF_MACRO(
1159    fSF_INVSQRT_COMMON,
1160    arch_sf_invsqrt_common(&N,&O,&A),
1161    (A_FPOP)
1162)
1163
1164DEF_MACRO(
1165    fFMAFX,
1166    internal_fmafx(A,B,C,fSXTN(8,64,ADJ)),
1167    ()
1168)
1169
1170DEF_MACRO(
1171    fFMAF,
1172    internal_fmafx(A,B,C,0),
1173    ()
1174)
1175
1176DEF_MACRO(
1177    fSFMPY,
1178    internal_mpyf(A,B),
1179    ()
1180)
1181
1182DEF_MACRO(
1183    fMAKESF,
1184    ((((SIGN) & 1) << 31) | (((EXP) & 0xff) << fSF_MANTBITS()) |
1185        ((MANT) & ((1<<fSF_MANTBITS())-1))),
1186    ()
1187)
1188
1189
1190DEF_MACRO(
1191    fDOUBLE, /* multiply half integer */
1192    ({ union { double f; size8u_t i; } _fipun; _fipun.i = (A); _fipun.f; }),     /* behavior */
1193    (A_FPOP)
1194)
1195
1196DEF_MACRO(
1197    fUNDOUBLE, /* multiply half integer */
1198    ({ union { double f; size8u_t i; } _fipun; _fipun.f = (A); isnan(_fipun.f) ? 0xFFFFFFFFFFFFFFFFULL : _fipun.i; }),     /* behavior */
1199    (A_FPOP)
1200)
1201
1202DEF_MACRO(
1203    fDFNANVAL,
1204    0xffffffffffffffffULL,
1205    ()
1206)
1207
1208DEF_MACRO(
1209    fDF_ISNORMAL,
1210    (fpclassify(fDOUBLE(X)) == FP_NORMAL),
1211    ()
1212)
1213
1214DEF_MACRO(
1215    fDF_ISDENORM,
1216    (fpclassify(fDOUBLE(X)) == FP_SUBNORMAL),
1217    ()
1218)
1219
1220DEF_MACRO(
1221    fDF_ISBIG,
1222    (fDF_GETEXP(X) >= 512),
1223    ()
1224)
1225
1226DEF_MACRO(
1227    fDF_MANTBITS,
1228    52,
1229    ()
1230)
1231
1232DEF_MACRO(
1233    fDF_GETEXP,
1234    (((A) >> fDF_MANTBITS()) & 0x7ff),
1235    ()
1236)
1237
1238DEF_MACRO(
1239    fFMA,
1240    internal_fma(A,B,C),
1241    /* nothing */
1242)
1243
1244DEF_MACRO(
1245    fDF_MPY_HH,
1246    internal_mpyhh(A,B,ACC),
1247    /* nothing */
1248)
1249
1250DEF_MACRO(
1251    fFPOP_START,
1252    arch_fpop_start(thread),
1253    /* nothing */
1254)
1255
1256DEF_MACRO(
1257    fFPOP_END,
1258    arch_fpop_end(thread),
1259    /* nothing */
1260)
1261
1262DEF_MACRO(
1263    fFPSETROUND_NEAREST,
1264    fesetround(FE_TONEAREST),
1265    /* nothing */
1266)
1267
1268DEF_MACRO(
1269    fFPSETROUND_CHOP,
1270    fesetround(FE_TOWARDZERO),
1271    /* nothing */
1272)
1273
1274DEF_MACRO(
1275    fFPCANCELFLAGS,
1276    feclearexcept(FE_ALL_EXCEPT),
1277    /* nothing */
1278)
1279
1280DEF_MACRO(
1281    fISINFPROD,
1282    ((isinf(A) && isinf(B)) ||
1283     (isinf(A) && isfinite(B) && ((B) != 0.0)) ||
1284     (isinf(B) && isfinite(A) && ((A) != 0.0))),
1285    /* nothing */
1286)
1287
1288DEF_MACRO(
1289    fISZEROPROD,
1290    ((((A) == 0.0) && isfinite(B)) || (((B) == 0.0) && isfinite(A))),
1291    /* nothing */
1292)
1293
1294DEF_MACRO(
1295    fRAISEFLAGS,
1296    arch_raise_fpflag(A),
1297    /* NOTHING */
1298)
1299
1300DEF_MACRO(
1301    fDF_MAX,
1302    (((A)==(B))
1303    ? fDOUBLE(fUNDOUBLE(A) & fUNDOUBLE(B))
1304    : fmax(A,B)),
1305    (A_FPOP)
1306)
1307
1308DEF_MACRO(
1309    fDF_MIN,
1310    (((A)==(B))
1311    ? fDOUBLE(fUNDOUBLE(A) | fUNDOUBLE(B))
1312    : fmin(A,B)),
1313    (A_FPOP)
1314)
1315
1316DEF_MACRO(
1317    fSF_MAX,
1318    (((A)==(B))
1319    ? fFLOAT(fUNFLOAT(A) & fUNFLOAT(B))
1320    : fmaxf(A,B)),
1321    (A_FPOP)
1322)
1323
1324DEF_MACRO(
1325    fSF_MIN,
1326    (((A)==(B))
1327    ? fFLOAT(fUNFLOAT(A) | fUNFLOAT(B))
1328    : fminf(A,B)),
1329    (A_FPOP)
1330)
1331
1332/*************************************/
1333/* Load/Store support                */
1334/*************************************/
1335
1336DEF_MACRO(fLOAD,
1337    { DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(thread,EA,insn); },
1338    (A_LOAD,A_MEMLIKE)
1339)
1340
1341DEF_MACRO(fMEMOP,
1342    { memop##SIZE##_##FNTYPE(thread,EA,VALUE); },
1343    (A_LOAD,A_STORE,A_MEMLIKE)
1344)
1345
1346DEF_MACRO(fGET_FRAMEKEY,
1347    READ_RREG(REG_FRAMEKEY),
1348    ()
1349)
1350
1351DEF_MACRO(fFRAME_SCRAMBLE,
1352    ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32)),
1353    /* ATTRIBS */
1354)
1355
1356DEF_MACRO(fFRAME_UNSCRAMBLE,
1357    fFRAME_SCRAMBLE(VAL),
1358    /* ATTRIBS */
1359)
1360
1361DEF_MACRO(fFRAMECHECK,
1362    sys_check_framelimit(thread,ADDR,EA),
1363    ()
1364)
1365
1366DEF_MACRO(fLOAD_LOCKED,
1367    {     DST = (size##SIZE##SIGN##_t)mem_load_locked(thread,EA,SIZE,insn); },
1368    (A_LOAD,A_MEMLIKE)
1369)
1370
1371DEF_MACRO(fSTORE,
1372    { MEM_STORE##SIZE(thread,EA,SRC,insn); },
1373    (A_STORE,A_MEMLIKE)
1374)
1375
1376
1377DEF_MACRO(fSTORE_LOCKED,
1378    { PRED = (mem_store_conditional(thread,EA,SRC,SIZE,insn) ? 0xff : 0); },
1379    (A_STORE,A_MEMLIKE)
1380)
1381
1382/*************************************/
1383/* Functions to help with bytes      */
1384/*************************************/
1385
1386DEF_MACRO(fGETBYTE,
1387    ((size1s_t)((SRC>>((N)*8))&0xff)),
1388    /* nothing */
1389)
1390
1391DEF_MACRO(fGETUBYTE,
1392    ((size1u_t)((SRC>>((N)*8))&0xff)),
1393    /* nothing */
1394)
1395
1396DEF_MACRO(fSETBYTE,
1397    {
1398        DST = (DST & ~(0x0ffLL<<((N)*8))) | (((size8u_t)((VAL) & 0x0ffLL)) << ((N)*8));
1399    },
1400    /* nothing */
1401)
1402
1403DEF_MACRO(fGETHALF,
1404    ((size2s_t)((SRC>>((N)*16))&0xffff)),
1405    /* nothing */
1406)
1407
1408DEF_MACRO(fGETUHALF,
1409    ((size2u_t)((SRC>>((N)*16))&0xffff)),
1410    /* nothing */
1411)
1412
1413DEF_MACRO(fSETHALF,
1414    {
1415        DST = (DST & ~(0x0ffffLL<<((N)*16))) | (((size8u_t)((VAL) & 0x0ffff)) << ((N)*16));
1416    },
1417    /* nothing */
1418)
1419
1420
1421
1422DEF_MACRO(fGETWORD,
1423    ((size8s_t)((size4s_t)((SRC>>((N)*32))&0x0ffffffffLL))),
1424    /* nothing */
1425)
1426
1427DEF_MACRO(fGETUWORD,
1428    ((size8u_t)((size4u_t)((SRC>>((N)*32))&0x0ffffffffLL))),
1429    /* nothing */
1430)
1431
1432DEF_MACRO(fSETWORD,
1433    {
1434        DST = (DST & ~(0x0ffffffffLL<<((N)*32))) | (((VAL) & 0x0ffffffffLL) << ((N)*32));
1435    },
1436    /* nothing */
1437)
1438
1439DEF_MACRO(fSETBIT,
1440    {
1441        DST = (DST & ~(1ULL<<(N))) | (((size8u_t)(VAL))<<(N));
1442    },
1443    /* nothing */
1444)
1445
1446DEF_MACRO(fGETBIT,
1447    (((SRC)>>N)&1),
1448    /* nothing */
1449)
1450
1451
1452DEF_MACRO(fSETBITS,
1453    do {
1454        int j;
1455        for (j=LO;j<=HI;j++) {
1456          fSETBIT(j,DST,VAL);
1457        }
1458    } while (0),
1459    /* nothing */
1460)
1461
1462/*************************************/
1463/* Used for parity, etc........      */
1464/*************************************/
1465DEF_MACRO(fCOUNTONES_2,
1466    count_ones_2(VAL),
1467    /* nothing */
1468)
1469
1470DEF_MACRO(fCOUNTONES_4,
1471    count_ones_4(VAL),
1472    /* nothing */
1473)
1474
1475DEF_MACRO(fCOUNTONES_8,
1476    count_ones_8(VAL),
1477    /* nothing */
1478)
1479
1480DEF_MACRO(fBREV_8,
1481    reverse_bits_8(VAL),
1482    /* nothing */
1483)
1484
1485DEF_MACRO(fBREV_4,
1486    reverse_bits_4(VAL),
1487    /* nothing */
1488)
1489
1490DEF_MACRO(fCL1_8,
1491    count_leading_ones_8(VAL),
1492    /* nothing */
1493)
1494
1495DEF_MACRO(fCL1_4,
1496    count_leading_ones_4(VAL),
1497    /* nothing */
1498)
1499
1500DEF_MACRO(fCL1_2,
1501    count_leading_ones_2(VAL),
1502    /* nothing */
1503)
1504
1505DEF_MACRO(fINTERLEAVE,
1506    interleave(ODD,EVEN),
1507    /* nothing */
1508)
1509
1510DEF_MACRO(fDEINTERLEAVE,
1511    deinterleave(MIXED),
1512    /* nothing */
1513)
1514
1515DEF_MACRO(fHIDE,
1516    A,
1517    ()
1518)
1519
1520DEF_MACRO(fCONSTLL,
1521    A##LL,
1522)
1523
1524/* Do the things in the parens, but don't print the parens. */
1525DEF_MACRO(fECHO,
1526    (A),
1527    /* nothing */
1528)
1529
1530
1531/********************************************/
1532/* OS interface and stop/wait               */
1533/********************************************/
1534
1535DEF_MACRO(fPAUSE,
1536    {sys_pause(thread, insn->slot, IMM);},
1537    ()
1538)
1539
1540DEF_MACRO(fTRAP,
1541    warn("Trap NPC=%x ",fREAD_NPC());
1542    warn("Trap exception, PCYCLE=%lld TYPE=%d NPC=%x IMM=0x%x",thread->processor_ptr->pstats[pcycles],TRAPTYPE,fREAD_NPC(),IMM);
1543    register_trap_exception(thread,fREAD_NPC(),TRAPTYPE,IMM);,
1544    ()
1545)
1546
1547DEF_MACRO(fALIGN_REG_FIELD_VALUE,
1548    ((VAL)<<reg_field_info[FIELD].offset),
1549    /* */
1550)
1551
1552DEF_MACRO(fGET_REG_FIELD_MASK,
1553    (((1<<reg_field_info[FIELD].width)-1)<<reg_field_info[FIELD].offset),
1554    /* */
1555)
1556
1557DEF_MACRO(fREAD_REG_FIELD,
1558    fEXTRACTU_BITS(thread->Regs[REG_##REG],
1559        reg_field_info[FIELD].width,
1560        reg_field_info[FIELD].offset),
1561    /* ATTRIBS */
1562)
1563
1564DEF_MACRO(fGET_FIELD,
1565    fEXTRACTU_BITS(VAL,
1566        reg_field_info[FIELD].width,
1567        reg_field_info[FIELD].offset),
1568    /* ATTRIBS */
1569)
1570
1571DEF_MACRO(fSET_FIELD,
1572    fINSERT_BITS(VAL,
1573        reg_field_info[FIELD].width,
1574        reg_field_info[FIELD].offset,
1575        (NEWVAL)),
1576    /* ATTRIBS */
1577)
1578
1579/********************************************/
1580/* Cache Management                         */
1581/********************************************/
1582
1583DEF_MACRO(fBARRIER,
1584    {
1585        sys_barrier(thread, insn->slot);
1586    },
1587    ()
1588)
1589
1590DEF_MACRO(fSYNCH,
1591    {
1592        sys_sync(thread, insn->slot);
1593    },
1594    ()
1595)
1596
1597DEF_MACRO(fISYNC,
1598    {
1599        sys_isync(thread, insn->slot);
1600    },
1601    ()
1602)
1603
1604
1605DEF_MACRO(fDCFETCH,
1606    sys_dcfetch(thread, (REG), insn->slot),
1607    (A_MEMLIKE)
1608)
1609
1610DEF_MACRO(fICINVA,
1611    {
1612        arch_internal_flush(thread->processor_ptr, 0, 0xffffffff);
1613        sys_icinva(thread, (REG),insn->slot);
1614    },
1615    (A_ICINVA)
1616)
1617
1618DEF_MACRO(fL2FETCH,
1619    sys_l2fetch(thread, ADDR,HEIGHT,WIDTH,STRIDE,FLAGS, insn->slot),
1620    (A_MEMLIKE,A_L2FETCH)
1621)
1622
1623DEF_MACRO(fDCCLEANA,
1624    sys_dccleana(thread, (REG)),
1625    (A_MEMLIKE)
1626)
1627
1628DEF_MACRO(fDCCLEANINVA,
1629    sys_dccleaninva(thread, (REG), insn->slot),
1630    (A_MEMLIKE,A_DCCLEANINVA)
1631)
1632
1633DEF_MACRO(fDCZEROA,
1634    sys_dczeroa(thread, (REG)),
1635    (A_MEMLIKE)
1636)
1637
1638DEF_MACRO(fCHECKFORPRIV,
1639    {sys_check_privs(thread); if (EXCEPTION_DETECTED) return; },
1640    ()
1641)
1642
1643DEF_MACRO(fCHECKFORGUEST,
1644    {sys_check_guest(thread); if (EXCEPTION_DETECTED) return; },
1645    ()
1646)
1647
1648DEF_MACRO(fBRANCH_SPECULATE_STALL,
1649    {
1650        sys_speculate_branch_stall(thread, insn->slot, JUMP_COND(JUMP_PRED_SET),
1651            SPEC_DIR,
1652            DOTNEWVAL,
1653            HINTBITNUM,
1654            STRBITNUM,
1655            0,
1656            thread->last_pkt->pkt_has_dual_jump,
1657            insn->is_2nd_jump,
1658            (thread->fetch_access.vaddr + insn->encoding_offset*4));
1659    },
1660    ()
1661)
1662
1663DEF_MACRO(IV1DEAD,
1664    ,
1665    ()
1666)
1667