1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2601fbec7SMasahiro Yamada /* 3601fbec7SMasahiro Yamada * SoC-specific code for tms320dm644x chips 4601fbec7SMasahiro Yamada * 5601fbec7SMasahiro Yamada * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 6601fbec7SMasahiro Yamada * Copyright (C) 2008 Lyrtech <www.lyrtech.com> 7601fbec7SMasahiro Yamada * Copyright (C) 2004 Texas Instruments. 8601fbec7SMasahiro Yamada */ 9601fbec7SMasahiro Yamada 10601fbec7SMasahiro Yamada #include <common.h> 11601fbec7SMasahiro Yamada #include <asm/arch/hardware.h> 12601fbec7SMasahiro Yamada 13601fbec7SMasahiro Yamada 14601fbec7SMasahiro Yamada #define PINMUX0_EMACEN (1 << 31) 15601fbec7SMasahiro Yamada #define PINMUX0_AECS5 (1 << 11) 16601fbec7SMasahiro Yamada #define PINMUX0_AECS4 (1 << 10) 17601fbec7SMasahiro Yamada 18601fbec7SMasahiro Yamada #define PINMUX1_I2C (1 << 7) 19601fbec7SMasahiro Yamada #define PINMUX1_UART1 (1 << 1) 20601fbec7SMasahiro Yamada #define PINMUX1_UART0 (1 << 0) 21601fbec7SMasahiro Yamada 22601fbec7SMasahiro Yamada davinci_enable_uart0(void)23601fbec7SMasahiro Yamadavoid davinci_enable_uart0(void) 24601fbec7SMasahiro Yamada { 25601fbec7SMasahiro Yamada lpsc_on(DAVINCI_LPSC_UART0); 26601fbec7SMasahiro Yamada 27601fbec7SMasahiro Yamada /* Bringup UART0 out of reset */ 28601fbec7SMasahiro Yamada REG(UART0_PWREMU_MGMT) = 0x00006001; 29601fbec7SMasahiro Yamada 30601fbec7SMasahiro Yamada /* Enable UART0 MUX lines */ 31601fbec7SMasahiro Yamada REG(PINMUX1) |= PINMUX1_UART0; 32601fbec7SMasahiro Yamada } 33601fbec7SMasahiro Yamada 34601fbec7SMasahiro Yamada #ifdef CONFIG_DRIVER_TI_EMAC davinci_enable_emac(void)35601fbec7SMasahiro Yamadavoid davinci_enable_emac(void) 36601fbec7SMasahiro Yamada { 37601fbec7SMasahiro Yamada lpsc_on(DAVINCI_LPSC_EMAC); 38601fbec7SMasahiro Yamada lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); 39601fbec7SMasahiro Yamada lpsc_on(DAVINCI_LPSC_MDIO); 40601fbec7SMasahiro Yamada 41601fbec7SMasahiro Yamada /* Enable GIO3.3V cells used for EMAC */ 42601fbec7SMasahiro Yamada REG(VDD3P3V_PWDN) = 0; 43601fbec7SMasahiro Yamada 44601fbec7SMasahiro Yamada /* Enable EMAC. */ 45601fbec7SMasahiro Yamada REG(PINMUX0) |= PINMUX0_EMACEN; 46601fbec7SMasahiro Yamada } 47601fbec7SMasahiro Yamada #endif 48601fbec7SMasahiro Yamada 49601fbec7SMasahiro Yamada #ifdef CONFIG_SYS_I2C_DAVINCI davinci_enable_i2c(void)50601fbec7SMasahiro Yamadavoid davinci_enable_i2c(void) 51601fbec7SMasahiro Yamada { 52601fbec7SMasahiro Yamada lpsc_on(DAVINCI_LPSC_I2C); 53601fbec7SMasahiro Yamada 54601fbec7SMasahiro Yamada /* Enable I2C pin Mux */ 55601fbec7SMasahiro Yamada REG(PINMUX1) |= PINMUX1_I2C; 56601fbec7SMasahiro Yamada } 57601fbec7SMasahiro Yamada #endif 58601fbec7SMasahiro Yamada davinci_errata_workarounds(void)59601fbec7SMasahiro Yamadavoid davinci_errata_workarounds(void) 60601fbec7SMasahiro Yamada { 61601fbec7SMasahiro Yamada /* 62601fbec7SMasahiro Yamada * Workaround for TMS320DM6446 errata 1.3.22: 63601fbec7SMasahiro Yamada * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset 64601fbec7SMasahiro Yamada * Revision(s) Affected: 1.3 and earlier 65601fbec7SMasahiro Yamada */ 66601fbec7SMasahiro Yamada REG(PSC_SILVER_BULLET) = 0; 67601fbec7SMasahiro Yamada 68601fbec7SMasahiro Yamada /* 69601fbec7SMasahiro Yamada * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR) 70601fbec7SMasahiro Yamada * as suggested in TMS320DM6446 errata 2.1.2: 71601fbec7SMasahiro Yamada * 72601fbec7SMasahiro Yamada * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions 73601fbec7SMasahiro Yamada * low priority modules can occupy the bus and prevent high priority 74601fbec7SMasahiro Yamada * modules like the VPSS from getting the required DDR2 throughput. 75601fbec7SMasahiro Yamada * A hex value of 0x20 should provide a good ARM (cache enabled) 76601fbec7SMasahiro Yamada * performance and still allow good utilization by the VPSS or other 77601fbec7SMasahiro Yamada * modules. 78601fbec7SMasahiro Yamada */ 79601fbec7SMasahiro Yamada REG(VBPR) = 0x20; 80601fbec7SMasahiro Yamada } 81