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Searched refs:OTG (Results 1 – 25 of 188) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_optc.h34 SRI(OTG_VREADY_PARAM, OTG, inst),\
41 SRI(OTG_H_TOTAL, OTG, inst),\
43 SRI(OTG_H_SYNC_A, OTG, inst),\
46 SRI(OTG_V_TOTAL, OTG, inst),\
48 SRI(OTG_V_SYNC_A, OTG, inst),\
50 SRI(OTG_CONTROL, OTG, inst),\
57 SRI(OTG_TRIGA_CNTL, OTG, inst),\
61 SRI(OTG_STATUS, OTG, inst),\
79 SRI(OTG_CRC_CNTL, OTG, inst),\
100 SRI(OTG_CRC_CNTL2, OTG, inst),\
[all …]
H A Ddcn31_dccg.h45 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
46 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
47 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
48 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
119 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 0, mask_sh),\
120 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 1, mask_sh),\
121 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 2, mask_sh),\
123 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
124 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
125 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_optc.h35 SRI(OTG_VREADY_PARAM, OTG, inst),\
42 SRI(OTG_H_TOTAL, OTG, inst),\
44 SRI(OTG_H_SYNC_A, OTG, inst),\
47 SRI(OTG_V_TOTAL, OTG, inst),\
49 SRI(OTG_V_SYNC_A, OTG, inst),\
51 SRI(OTG_CONTROL, OTG, inst),\
55 SRI(OTG_V_TOTAL_MAX, OTG, inst),\
58 SRI(OTG_TRIGA_CNTL, OTG, inst),\
62 SRI(OTG_STATUS, OTG, inst),\
80 SRI(OTG_CRC_CNTL, OTG, inst),\
[all …]
H A Ddcn314_dccg.h52 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
53 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
54 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
55 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
119 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
120 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
121 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
123 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
124 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
125 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_optc.h43 SRI(OTG_H_TOTAL, OTG, inst),\
45 SRI(OTG_H_SYNC_A, OTG, inst),\
48 SRI(OTG_V_TOTAL, OTG, inst),\
50 SRI(OTG_V_SYNC_A, OTG, inst),\
52 SRI(OTG_CONTROL, OTG, inst),\
60 SRI(OTG_TRIGA_CNTL, OTG, inst),\
64 SRI(OTG_STATUS, OTG, inst),\
84 SRI(OTG_CRC_CNTL, OTG, inst),\
85 SRI(OTG_CRC_CNTL2, OTG, inst),\
94 SRI(OTG_DRR_CONTROL, OTG, inst)
[all …]
H A Ddcn30_dccg.h41 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
42 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
43 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
44 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.h81 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
82 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
83 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
84 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
95 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
96 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
97 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 4, mask_sh),\
98 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 5, mask_sh),\
102 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 5, mask_sh)
110 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
[all …]
H A Ddcn20_optc.h33 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
34 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
35 SRI(OTG_GSL_WINDOW_X, OTG, inst),\
36 SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
37 SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
38 SRI(OTG_DSC_START_POSITION, OTG, inst),\
39 SRI(OTG_CRC_CNTL2, OTG, inst),\
45 SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \
46 SRI(OTG_DRR_CONTROL, OTG, inst)
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.h72 SRII(PIXEL_RATE_CNTL, OTG, 0),\
73 SRII(PIXEL_RATE_CNTL, OTG, 1),\
74 SRII(PIXEL_RATE_CNTL, OTG, 2),\
77 SRII(PIXEL_RATE_CNTL, OTG, 5)
86 SRII(PIXEL_RATE_CNTL, OTG, 1)
101 SRII(PIXEL_RATE_CNTL, OTG, 3)
116 SRII(PIXEL_RATE_CNTL, OTG, 3)
131 SRII(PIXEL_RATE_CNTL, OTG, 3)
149 SRII(PIXEL_RATE_CNTL, OTG, 4)
158 SRII(PIXEL_RATE_CNTL, OTG, 1)
[all …]
H A Ddce_hwseq.h373 HWSEQ_PIXEL_RATE_REG_LIST_201(OTG), \
374 HWSEQ_PHYPLL_REG_LIST_201(OTG), \
397 HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \
398 HWSEQ_PHYPLL_REG_LIST_3(OTG), \
428 SRII(PIXEL_RATE_CNTL, OTG, 0), \
429 SRII(PIXEL_RATE_CNTL, OTG, 1),\
430 SRII(PIXEL_RATE_CNTL, OTG, 2),\
431 SRII(PIXEL_RATE_CNTL, OTG, 3),\
538 HWSEQ_PIXEL_RATE_REG_LIST_302(OTG), \
539 HWSEQ_PHYPLL_REG_LIST_302(OTG), \
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dccg.h80 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
81 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
82 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
88 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
89 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
90 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
91 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
92 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
93 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
94 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
[all …]
H A Ddcn32_resource.h190 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 0, index), \
191 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 1, index), \
192 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 2, index), \
1045 SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \
1046 SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \
1048 SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
1049 SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
1059 SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \
1074 SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst), \
1294 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn303/
H A Ddcn303_dccg.h20 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
21 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1)
41 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
42 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
43 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
44 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_optc.h37 SRI(OTG_VREADY_PARAM, OTG, inst),\
42 SRI(OTG_H_TOTAL, OTG, inst),\
44 SRI(OTG_H_SYNC_A, OTG, inst),\
47 SRI(OTG_V_TOTAL, OTG, inst),\
49 SRI(OTG_V_SYNC_A, OTG, inst),\
52 SRI(OTG_CONTROL, OTG, inst),\
56 SRI(OTG_V_TOTAL_MAX, OTG, inst),\
57 SRI(OTG_V_TOTAL_MID, OTG, inst),\
60 SRI(OTG_TRIGA_CNTL, OTG, inst),\
64 SRI(OTG_STATUS, OTG, inst),\
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dusb-drd.yaml7 title: Generic USB OTG Controller
15 Tells usb driver the release number of the OTG and EH supplement with
17 decimal (i.e. 2.0 is 0200H). This property is used if any real OTG
27 should default to OTG.
34 Tells OTG controllers we want to disable OTG HNP. Normally HNP is the
35 basic function of real OTG except you want it to be a srp-capable only B
41 Tells OTG controllers we want to disable OTG SRP. SRP is optional for OTG
47 Tells OTG controllers we want to disable OTG ADP. ADP is optional for OTG
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_optc.h33 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
34 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
35 SRI(OTG_GSL_WINDOW_X, OTG, inst),\
36 SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
37 SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
38 SRI(OTG_DSC_START_POSITION, OTG, inst),\
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dallwinner,suniv-f1c100s-usb-phy.yaml29 description: USB OTG PHY bus clock
36 description: USB OTG reset
43 description: GPIO to the USB OTG ID pin
47 description: GPIO to the USB OTG VBUS detect pin
50 description: Power supply to detect the USB OTG VBUS
53 description: Regulator controlling USB OTG VBUS
H A Dallwinner,sun8i-v3s-usb-phy.yaml32 description: USB OTG PHY bus clock
39 description: USB OTG reset
46 description: GPIO to the USB OTG ID pin
50 description: GPIO to the USB OTG VBUS detect pin
53 description: Power supply to detect the USB OTG VBUS
56 description: Regulator controlling USB OTG VBUS
H A Dallwinner,sun5i-a13-usb-phy.yaml32 description: USB OTG PHY bus clock
39 - description: USB OTG reset
49 description: GPIO to the USB OTG ID pin
53 description: GPIO to the USB OTG VBUS detect pin
56 description: Power supply to detect the USB OTG VBUS
59 description: Regulator controlling USB OTG VBUS
H A Dallwinner,sun8i-a23-usb-phy.yaml34 - description: USB OTG PHY bus clock
44 - description: USB OTG reset
54 description: GPIO to the USB OTG ID pin
58 description: GPIO to the USB OTG VBUS detect pin
61 description: Power supply to detect the USB OTG VBUS
64 description: Regulator controlling USB OTG VBUS
H A Dallwinner,sun50i-a64-usb-phy.yaml36 - description: USB OTG PHY bus clock
46 - description: USB OTG reset
56 description: GPIO to the USB OTG ID pin
60 description: GPIO to the USB OTG VBUS detect pin
63 description: Power supply to detect the USB OTG VBUS
66 description: Regulator controlling USB OTG VBUS
H A Dallwinner,sun50i-h6-usb-phy.yaml34 - description: USB OTG PHY bus clock
44 - description: USB OTG reset
54 description: GPIO to the USB OTG ID pin
58 description: GPIO to the USB OTG VBUS detect pin
61 description: Power supply to detect the USB OTG VBUS
64 description: Regulator controlling USB OTG VBUS
H A Dallwinner,sun6i-a31-usb-phy.yaml34 - description: USB OTG PHY bus clock
46 - description: USB OTG reset
58 description: GPIO to the USB OTG ID pin
62 description: GPIO to the USB OTG VBUS detect pin
65 description: Power supply to detect the USB OTG VBUS
68 description: Regulator controlling USB OTG VBUS
H A Dallwinner,sun8i-a83t-usb-phy.yaml34 - description: USB OTG PHY bus clock
48 - description: USB OTG reset
60 description: GPIO to the USB OTG ID pin
64 description: GPIO to the USB OTG VBUS detect pin
67 description: Power supply to detect the USB OTG VBUS
70 description: Regulator controlling USB OTG VBUS
H A Dallwinner,sun8i-r40-usb-phy.yaml36 - description: USB OTG PHY bus clock
48 - description: USB OTG reset
60 description: GPIO to the USB OTG ID pin
64 description: GPIO to the USB OTG VBUS detect pin
67 description: Power supply to detect the USB OTG VBUS
70 description: Regulator controlling USB OTG VBUS

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