1015b4489SAurabindo Pillai // SPDX-License-Identifier: MIT 2cd6d421eSAurabindo Pillai /* 3015b4489SAurabindo Pillai * Copyright (C) 2021 Advanced Micro Devices, Inc. 4cd6d421eSAurabindo Pillai * 5cd6d421eSAurabindo Pillai * Authors: AMD 6cd6d421eSAurabindo Pillai */ 7cd6d421eSAurabindo Pillai 8cd6d421eSAurabindo Pillai #ifndef __DCN303_DCCG_H__ 9cd6d421eSAurabindo Pillai #define __DCN303_DCCG_H__ 10cd6d421eSAurabindo Pillai 11cd6d421eSAurabindo Pillai #include "dcn30/dcn30_dccg.h" 12cd6d421eSAurabindo Pillai 13cd6d421eSAurabindo Pillai 14cd6d421eSAurabindo Pillai #define DCCG_REG_LIST_DCN3_03() \ 15cd6d421eSAurabindo Pillai SR(DPPCLK_DTO_CTRL),\ 16cd6d421eSAurabindo Pillai DCCG_SRII(DTO_PARAM, DPPCLK, 0),\ 17cd6d421eSAurabindo Pillai DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ 18*2ca6c483SWesley Chalmers SR(REFCLK_CNTL),\ 19*2ca6c483SWesley Chalmers SR(DISPCLK_FREQ_CHANGE_CNTL),\ 20*2ca6c483SWesley Chalmers DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\ 21*2ca6c483SWesley Chalmers DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1) 22*2ca6c483SWesley Chalmers 23cd6d421eSAurabindo Pillai 24cd6d421eSAurabindo Pillai #define DCCG_MASK_SH_LIST_DCN3_03(mask_sh) \ 25cd6d421eSAurabindo Pillai DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ 26cd6d421eSAurabindo Pillai DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ 27cd6d421eSAurabindo Pillai DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\ 28cd6d421eSAurabindo Pillai DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ 29cd6d421eSAurabindo Pillai DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ 30cd6d421eSAurabindo Pillai DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ 31cd6d421eSAurabindo Pillai DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\ 32*2ca6c483SWesley Chalmers DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\ 33*2ca6c483SWesley Chalmers DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\ 34*2ca6c483SWesley Chalmers DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\ 35*2ca6c483SWesley Chalmers DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\ 36*2ca6c483SWesley Chalmers DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\ 37*2ca6c483SWesley Chalmers DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\ 38*2ca6c483SWesley Chalmers DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\ 39*2ca6c483SWesley Chalmers DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\ 40*2ca6c483SWesley Chalmers DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\ 41*2ca6c483SWesley Chalmers DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ 42*2ca6c483SWesley Chalmers DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ 43*2ca6c483SWesley Chalmers DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\ 44*2ca6c483SWesley Chalmers DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh) 45cd6d421eSAurabindo Pillai 46cd6d421eSAurabindo Pillai #endif //__DCN303_DCCG_H__ 47