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Searched refs:MV_OK (Results 1 – 25 of 30) sorted by relevance

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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.c204 if (MV_OK != in ddr3_hw_training()
229 if (MV_OK != in ddr3_hw_training()
237 if (MV_OK != in ddr3_hw_training()
481 return MV_OK; in ddr3_hw_training()
681 return MV_OK; in ddr3_load_patterns()
859 return MV_OK; in ddr3_read_training_results()
970 return MV_OK; in ddr3_training_suspend_resume()
1042 return MV_OK; in ddr3_get_min_max_read_sample_delay()
1064 return MV_OK; in ddr3_get_min_max_rl_phase()
1082 return MV_OK; in ddr3_odt_activate()
[all …]
H A Dxor.c151 return MV_OK; in mv_xor_ctrl_set()
205 return MV_OK; in mv_xor_mem_init()
316 return MV_OK; in mv_xor_transfer()
406 return MV_OK; in mv_xor_cmd_set()
412 return MV_OK; in mv_xor_cmd_set()
418 return MV_OK; in mv_xor_cmd_set()
424 return MV_OK; in mv_xor_cmd_set()
428 return MV_OK; in mv_xor_cmd_set()
H A Dddr3_dqs.c202 return MV_OK; in ddr3_dqs_centralization_rx()
282 return MV_OK; in ddr3_dqs_centralization_tx()
814 return MV_OK; in ddr3_find_adll_limits()
838 return MV_OK; in ddr3_check_window_limits()
875 return MV_OK; in ddr3_check_window_limits()
924 if (MV_OK != in ddr3_center_calc()
933 if (MV_OK != in ddr3_center_calc()
1101 return MV_OK; in ddr3_special_pattern_i_search()
1250 return MV_OK; in ddr3_special_pattern_ii_search()
1321 return MV_OK; in ddr3_set_dqs_centralization_results()
[all …]
H A Dddr3_pbs.c392 return MV_OK; in ddr3_pbs_tx()
509 return MV_OK; in ddr3_tx_shift_dqs_adll_step_before_fail()
904 return MV_OK; in ddr3_pbs_rx()
1079 return MV_OK; in ddr3_rx_shift_dqs_to_first_fail()
1239 if (MV_OK != in ddr3_pbs_per_bit()
1364 return MV_OK; in ddr3_pbs_per_bit()
1406 return MV_OK; in ddr3_pbs_per_bit()
1504 return MV_OK; in ddr3_set_pbs_results()
1570 if (MV_OK != in ddr3_load_pbs_patterns()
1580 if (MV_OK != in ddr3_load_pbs_patterns()
[all …]
H A Dddr3_sdram.c200 return MV_OK; in ddr3_sdram_compare()
264 return MV_OK; in ddr3_sdram_dm_compare()
422 return MV_OK; in ddr3_sdram_pbs_compare()
481 return MV_OK; in ddr3_sdram_direct_compare()
536 if (mv_xor_transfer(chan, MV_DMA, channel.desc_phys_addr) != MV_OK) in ddr3_dram_sram_burst()
547 return MV_OK; in ddr3_dram_sram_burst()
596 return MV_OK; in ddr3_dram_sram_read()
633 return MV_OK; in ddr3_sdram_dqs_compare()
H A Dddr3_write_leveling.c170 return MV_OK; in ddr3_write_leveling_hw()
266 if (MV_OK != ddr3_dram_sram_burst((u32) in ddr3_wl_supplement()
273 if (MV_OK != in ddr3_wl_supplement()
461 return MV_OK; in ddr3_wl_supplement()
615 return MV_OK; in ddr3_write_leveling_hw_reg_dimm()
767 if (MV_OK != in ddr3_write_leveling_sw()
869 return MV_OK; in ddr3_write_leveling_sw()
1008 if (MV_OK != in ddr3_write_leveling_sw_reg_dimm()
1110 return MV_OK; in ddr3_write_leveling_sw_reg_dimm()
1332 return MV_OK; in ddr3_write_leveling_single_cs()
H A Dddr3_read_leveling.c163 return MV_OK; in ddr3_read_leveling_hw()
248 if (MV_OK != status) in ddr3_read_leveling_sw()
256 if (MV_OK != status) in ddr3_read_leveling_sw()
327 return MV_OK; in ddr3_read_leveling_sw()
458 if (MV_OK != in ddr3_read_leveling_single_cs_rl_mode()
736 return MV_OK; in ddr3_read_leveling_single_cs_rl_mode()
812 if (MV_OK != in ddr3_read_leveling_single_cs_window_mode()
1211 return MV_OK; in ddr3_read_leveling_single_cs_window_mode()
H A Dddr3_spd.c495 return MV_OK; in ddr3_spd_init()
510 return MV_OK; in ddr3_spd_sum_init()
564 return MV_OK; in ddr3_spd_sum_init()
599 if (MV_OK != status)
607 if (MV_OK != status)
628 if (MV_OK != status)
631 if (MV_OK != status)
1238 return MV_OK;
H A Dddr3_init.c455 return MV_OK; in ddr3_init_main()
505 if (MV_OK != status) { in ddr3_init_main()
609 if (MV_OK != status) { in ddr3_init_main()
632 if (MV_OK != status) { in ddr3_init_main()
681 return MV_OK; in ddr3_init_main()
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_init.c49 if (mv_ddr_early_init2() != MV_OK) in ddr3_init()
54 if (MV_OK != status) in ddr3_init()
68 if (MV_OK != status) { in ddr3_init()
75 if (MV_OK != status) { in ddr3_init()
94 return MV_OK; in ddr3_init()
135 if (MV_OK != status) { in mv_ddr_training_params_set()
140 return MV_OK; in mv_ddr_training_params_set()
H A Dmv_ddr_plat.c238 return MV_OK; in ddr3_tip_a38x_get_freq_config()
302 return MV_OK; in mv_ddr_is_odpg_done()
347 return MV_OK; in mv_ddr_is_training_done()
377 return MV_OK; in ddr3_tip_a38x_select_ddr_controller()
479 return MV_OK; in mv_ddr_sar_freq_get()
556 return MV_OK; in ddr3_tip_a38x_get_medium_freq()
568 return MV_OK; in ddr3_tip_a38x_get_device_info()
587 return MV_OK; in is_prfa_done()
610 return MV_OK; in prfa_write()
636 return MV_OK; in prfa_read()
[all …]
H A Dddr3_training_bist.c68 return MV_OK; in ddr3_tip_bist_activate()
112 return MV_OK; in ddr3_tip_bist_read_result()
160 return MV_OK; in hws_ddr3_run_bist()
176 return MV_OK; in ddr3_tip_bist_operation()
242 return MV_OK; in mv_ddr_tip_bist()
290 return MV_OK; in interval_init()
302 return MV_OK; in interval_set()
392 return MV_OK; in interval_proc()
420 return MV_OK; in mv_ddr_dm_to_dq_diff_get()
436 return MV_OK; in mv_ddr_bist_tx()
[all …]
H A Dddr3_training.c225 return MV_OK; in ddr3_tip_pad_inv()
273 return MV_OK; in ddr3_tip_tune_training_params()
329 return MV_OK; in ddr3_tip_configure_cs()
670 return MV_OK; in hws_ddr3_tip_init_controller()
727 return MV_OK; in ddr3_tip_rev2_rank_control()
760 return MV_OK; in ddr3_tip_rev3_rank_control()
872 return MV_OK; in ddr3_pre_algo_config()
897 return MV_OK; in ddr3_post_algo_config()
944 int ret = MV_OK, ret_tune = MV_OK; in odt_test()
996 return MV_OK; in ddr3_tip_if_write()
[all …]
H A Dxor.c162 return MV_OK; in mv_xor_ctrl_set()
219 return MV_OK; in mv_xor_mem_init()
308 return MV_OK; in mv_xor_command_set()
314 return MV_OK; in mv_xor_command_set()
321 return MV_OK; in mv_xor_command_set()
327 return MV_OK; in mv_xor_command_set()
330 return MV_OK; in mv_xor_command_set()
465 return MV_OK; in mv_xor_transfer()
H A Dddr3_training_leveling.c309 return MV_OK; in ddr3_tip_dynamic_read_leveling()
350 return MV_OK; in ddr3_tip_legacy_dynamic_write_leveling()
391 return MV_OK; in ddr3_tip_legacy_dynamic_read_leveling()
761 return MV_OK; in ddr3_tip_dynamic_per_bit_read_leveling()
799 return MV_OK; in ddr3_tip_calc_cs_mask()
1168 return MV_OK; in ddr3_tip_dynamic_write_leveling()
1281 return MV_OK; in ddr3_tip_dynamic_write_leveling_supp()
1521 return MV_OK; in ddr3_tip_dynamic_write_leveling_seq()
1559 return MV_OK; in ddr3_tip_dynamic_read_leveling_seq()
1598 return MV_OK; in ddr3_tip_dynamic_per_bit_read_leveling_seq()
[all …]
H A Dddr3_training_ip_engine.c565 return MV_OK; in ddr3_tip_ip_training()
619 return MV_OK; in ddr3_tip_load_pattern_to_odpg()
643 return MV_OK; in ddr3_tip_configure_odpg()
686 return MV_OK; in ddr3_tip_process_result()
841 return MV_OK; in ddr3_tip_read_training_result()
868 return MV_OK; in ddr3_tip_load_all_pattern_to_mem()
949 return MV_OK; in ddr3_tip_load_pattern_to_mem()
1053 return MV_OK; in ddr3_tip_ip_training_wrapper_int()
1442 return MV_OK; in ddr3_tip_ip_training_wrapper()
1516 return MV_OK; in ddr3_tip_load_phy_values()
[all …]
H A Dddr3_debug.c163 return MV_OK; in ddr3_tip_reg_dump()
178 return MV_OK; in ddr3_tip_init_config_func()
310 return MV_OK; in print_device_info()
504 return MV_OK; in ddr3_tip_print_log()
656 return MV_OK; in ddr3_tip_print_stability_log()
666 return MV_OK; in ddr3_tip_register_xsb_info()
860 return MV_OK; in ddr3_tip_print_adll()
882 return MV_OK; in print_adll()
898 return MV_OK; in print_ph()
1343 int ret = MV_OK, ret_tmp; in run_xsb_test()
[all …]
H A Dmv_ddr_common.c46 return MV_OK; in round_div()
H A Dddr3_training_centralization.c37 return MV_OK; in ddr3_tip_centralization_rx()
47 return MV_OK; in ddr3_tip_centralization_tx()
513 return MV_OK; in ddr3_tip_special_rx()
690 return MV_OK; in ddr3_tip_special_rx()
715 return MV_OK; in ddr3_tip_print_centralization_result()
H A Dddr_ml_wrapper.h88 #define MV_OK (0x00) /* Operation succeeded */ macro
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dseq_exec.c40 return MV_OK; in write_op_execute()
66 return MV_OK; in write_op_execute()
80 return MV_OK; in delay_op_execute()
97 return MV_OK; in poll_op_execute()
123 return MV_OK; in poll_op_execute()
167 return MV_OK; in mv_seq_exec()
H A Dhigh_speed_env_spec-38x.c39 if (hws_serdes_seq_db_init() != MV_OK) { in hws_serdes_seq_init()
44 return MV_OK; in hws_serdes_seq_init()
115 return MV_OK; in hws_get_ext_base_addr()
H A Dhigh_speed_env_spec.c861 return MV_OK; in hws_serdes_topology_verify()
1294 return MV_OK; in hws_serdes_seq_db_init()
1409 return MV_OK; in hws_pre_serdes_init_config()
1453 return MV_OK; in serdes_phy_config()
1467 return MV_OK; in serdes_polarity_config()
1554 return MV_OK; in hws_power_up_serdes_lanes()
1586 return MV_OK; in serdes_pex_usb3_pipe_delay_w_a()
1637 return MV_OK; in hws_serdes_pex_ref_clock_satr_get()
1909 return MV_OK; in serdes_power_up_ctrl()
2007 return MV_OK; in hws_update_serdes_phy_selectors()
[all …]
H A Dctrl_pex.c224 return MV_OK; in hws_pex_config()
245 return MV_OK; in pex_local_bus_num_set()
260 return MV_OK; in pex_local_dev_num_set()
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_lib.c146 return MV_OK; in board_modules_scan()
248 int status = MV_OK; in serdes_phy_config()
273 return MV_OK; in serdes_phy_config()
289 return MV_OK; in serdes_phy_config()
938 status = MV_OK; in serdes_phy_config()
996 if (status == MV_OK) in serdes_phy_config()
1415 return MV_OK; in serdes_phy_config()
1574 return MV_OK; in pex_local_bus_num_set()
1609 return MV_OK; in pex_local_dev_num_set()

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