238 	return MV_OK;  in ddr3_tip_a38x_get_freq_config()
302 	return MV_OK;  in mv_ddr_is_odpg_done()
347 	return MV_OK;  in mv_ddr_is_training_done()
377 	return MV_OK;  in ddr3_tip_a38x_select_ddr_controller()
479 	return MV_OK;  in mv_ddr_sar_freq_get()
556 	return MV_OK;  in ddr3_tip_a38x_get_medium_freq()
568 	return MV_OK;  in ddr3_tip_a38x_get_device_info()
587 	return MV_OK;  in is_prfa_done()
607 	if (is_prfa_done() != MV_OK)  in prfa_write()
610 	return MV_OK;  in prfa_write()
624 			if (prfa_write(ACCESS_TYPE_UNICAST, i, phy_type, addr, 0, OPERATION_READ) != MV_OK)  in prfa_read()
630 		if (prfa_write(phy_access, phy, phy_type, addr, 0, OPERATION_READ) != MV_OK)  in prfa_read()
636 	return MV_OK;  in prfa_read()
681 	return MV_OK;  in mv_ddr_sw_db_init()
724 	return MV_OK;  in mv_ddr_training_mask_set()
847 	return MV_OK;  in ddr3_tip_a38x_set_divider()
861 	return MV_OK;  in ddr3_tip_ext_read()
874 	return MV_OK;  in ddr3_tip_ext_write()
895 	return MV_OK;  in mv_ddr_early_init()
902 	return MV_OK;  in mv_ddr_early_init2()
917 	return MV_OK;  in ddr3_post_run_alg()
931 	return MV_OK;  in ddr3_silicon_post_init()
1020 	return MV_OK;  in ddr3_calc_mem_cs_size()
1040 			if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK)  in ddr3_fast_path_dynamic_cs_size_config()
1101 	return MV_OK;  in ddr3_fast_path_dynamic_cs_size_config()
1121 	if (ddr3_fast_path_dynamic_cs_size_config(cs_ena) != MV_OK)  in ddr3_restore_and_set_final_windows()
1136 	return MV_OK;  in ddr3_restore_and_set_final_windows()
1207 	return MV_OK;  in ddr3_save_and_set_training_windows()
1250 		return MV_OK;  in mv_ddr_pre_training_soc_config()
1287 	return MV_OK;  in mv_ddr_pre_training_soc_config()
1319 	return MV_OK;  in ddr3_new_tip_dlb_config()
1337 	return MV_OK;  in mv_ddr_post_training_soc_config()
1351 	if (status != MV_OK)  in mv_ddr_mc_config()
1355 	if (status != MV_OK)  in mv_ddr_mc_config()
1365 	return MV_OK;  in mv_ddr_mc_init()
1442 	return MV_OK;  in ddr3_tip_configure_phy()