196 			if (MV_OK != ddr3_dfs_high_2_low(freq, &dram_info)) {  in ddr3_hw_training()
204 				if (MV_OK !=  in ddr3_hw_training()
229 					if (MV_OK !=  in ddr3_hw_training()
237 					if (MV_OK !=  in ddr3_hw_training()
245 				if (MV_OK != ddr3_write_leveling_hw(  in ddr3_hw_training()
249 						if (MV_OK !=  in ddr3_hw_training()
267 		if (MV_OK != ddr3_load_patterns(&dram_info, 0)) {  in ddr3_hw_training()
299 			if (MV_OK != ddr3_dfs_low_2_high(freq, tmp_ratio,  in ddr3_hw_training()
320 					if (MV_OK != ddr3_write_leveling_sw(  in ddr3_hw_training()
326 					if (MV_OK != ddr3_write_leveling_hw(  in ddr3_hw_training()
336 						if (MV_OK != ddr3_write_leveling_hw_reg_dimm(  in ddr3_hw_training()
341 					if (MV_OK != ddr3_write_leveling_hw(  in ddr3_hw_training()
345 							if (MV_OK != ddr3_write_leveling_sw(  in ddr3_hw_training()
369 				if (MV_OK != status) {  in ddr3_hw_training()
375 				if (MV_OK != ddr3_read_leveling_hw(  in ddr3_hw_training()
379 						if (MV_OK != ddr3_read_leveling_sw(  in ddr3_hw_training()
394 			if (MV_OK != ddr3_wl_supplement(&dram_info)) {  in ddr3_hw_training()
407 				status = MV_OK;  in ddr3_hw_training()
409 				if (MV_OK != status) {  in ddr3_hw_training()
418 				if (MV_OK != status) {  in ddr3_hw_training()
431 		if (MV_OK != status) {  in ddr3_hw_training()
440 		if (MV_OK != status) {  in ddr3_hw_training()
481 	return MV_OK;  in ddr3_hw_training()
681 		return MV_OK;  in ddr3_load_patterns()
859 	return MV_OK;  in ddr3_read_training_results()
879 		if (MV_OK != ddr3_write_leveling_hw(freq, dram_info)) {  in ddr3_check_if_resume_mode()
885 	if (MV_OK != ddr3_load_patterns(dram_info, 1)) {  in ddr3_check_if_resume_mode()
894 	if (MV_OK != ddr3_read_leveling_hw(freq, dram_info)) {  in ddr3_check_if_resume_mode()
919 	if (MV_OK != ddr3_read_training_results())  in ddr3_training_suspend_resume()
947 	if (MV_OK != ddr3_dfs_low_2_high(freq, tmp_ratio, dram_info)) {  in ddr3_training_suspend_resume()
970 	return MV_OK;  in ddr3_training_suspend_resume()
1042 	return MV_OK;  in ddr3_get_min_max_read_sample_delay()
1064 	return MV_OK;  in ddr3_get_min_max_rl_phase()
1082 	return MV_OK;  in ddr3_odt_activate()
1113 	return MV_OK;  in ddr3_odt_read_dynamic_config()