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Searched refs:MP0_HWIP (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dpsp_v13_0.c83 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); in psp_v13_0_init_microcode()
85 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_v13_0_init_microcode()
167 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) ? in psp_v13_0_wait_for_bootloader()
191 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) { in psp_v13_0_wait_for_bootloader_steady_state()
738 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 10)) { in psp_v13_0_fatal_error_recovery_quirk()
H A Dpsp_v13_0_4.c41 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); in psp_v13_0_4_init_microcode()
43 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_v13_0_4_init_microcode()
H A Damdgpu_psp.c103 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_check_pmfw_centralized_cstate_management()
131 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_init_sriov_microcode()
165 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_early_init()
337 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) in psp_get_runtime_db_entry()
416 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); in psp_sw_init()
776 switch (psp->adev->ip_versions[MP0_HWIP][0]) { in psp_boottime_tmr()
831 switch (psp->adev->ip_versions[MP0_HWIP][0]) { in psp_skip_tmr()
1218 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || in psp_xgmi_terminate()
1219 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && in psp_xgmi_terminate()
1318 psp->adev->ip_versions[MP0_HWIP][0] >= IP_VERSION(13, 0, 6); in psp_xgmi_peer_link_info_supported()
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H A Ddimgrey_cavefish_reg_init.c40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
H A Daldebaran_reg_init.c39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in aldebaran_reg_base_init()
H A Damdgpu_ras.c204 if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) && in amdgpu_ras_debugfs_read()
205 obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) { in amdgpu_ras_debugfs_read()
614 if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) && in amdgpu_ras_sysfs_read()
1214 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) && in amdgpu_ras_query_error_count_helper()
1215 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) { in amdgpu_ras_query_error_count_helper()
1922 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) && in amdgpu_ras_log_on_err_counter()
1923 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) && in amdgpu_ras_log_on_err_counter()
1924 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) { in amdgpu_ras_log_on_err_counter()
2412 switch (adev->ip_versions[MP0_HWIP][0]) { in amdgpu_ras_asic_supported()
2422 switch (adev->ip_versions[MP0_HWIP][0]) { in amdgpu_ras_asic_supported()
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H A Darct_reg_init.c39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in arct_reg_base_init()
H A Dpsp_v10_0.c54 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); in psp_v10_0_init_microcode()
H A Damdgpu_discovery.c191 [MP0_HWIP] = MP0_HWID,
1754 switch (adev->ip_versions[MP0_HWIP][0]) { in amdgpu_discovery_set_psp_ip_blocks()
1800 adev->ip_versions[MP0_HWIP][0]); in amdgpu_discovery_set_psp_ip_blocks()
2172 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2194 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2217 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); in amdgpu_discovery_set_ip_blocks()
2233 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); in amdgpu_discovery_set_ip_blocks()
2255 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); in amdgpu_discovery_set_ip_blocks()
2285 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); in amdgpu_discovery_set_ip_blocks()
2310 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); in amdgpu_discovery_set_ip_blocks()
H A Dvega10_reg_init.c39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega10_reg_base_init()
H A Dvega20_reg_init.c39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega20_reg_base_init()
H A Dpsp_v11_0.c96 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); in psp_v11_0_init_microcode()
98 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_v11_0_init_microcode()
H A Dpsp_v12_0.c55 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); in psp_v12_0_init_microcode()
H A Dpsp_v3_1.c65 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); in psp_v3_1_init_microcode()
H A Damdgpu_ucode.c1063 if (block_type == MP0_HWIP) { in amdgpu_ucode_legacy_naming()
1064 switch (adev->ip_versions[MP0_HWIP][0]) { in amdgpu_ucode_legacy_naming()
1291 case MP0_HWIP: in amdgpu_ucode_ip_version_decode()
H A Damdgpu_virt.c852 switch (adev->ip_versions[MP0_HWIP][0]) { in amdgpu_virt_fw_load_skip_check()
H A Dsoc15.c1458 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) { in soc15_common_get_clockgating_state()
H A Damdgpu.h650 MP0_HWIP, enumerator