12605e60cSXiaojian Du /*
22605e60cSXiaojian Du * Copyright 2020 Advanced Micro Devices, Inc.
32605e60cSXiaojian Du *
42605e60cSXiaojian Du * Permission is hereby granted, free of charge, to any person obtaining a
52605e60cSXiaojian Du * copy of this software and associated documentation files (the "Software"),
62605e60cSXiaojian Du * to deal in the Software without restriction, including without limitation
72605e60cSXiaojian Du * the rights to use, copy, modify, merge, publish, distribute, sublicense,
82605e60cSXiaojian Du * and/or sell copies of the Software, and to permit persons to whom the
92605e60cSXiaojian Du * Software is furnished to do so, subject to the following conditions:
102605e60cSXiaojian Du *
112605e60cSXiaojian Du * The above copyright notice and this permission notice shall be included in
122605e60cSXiaojian Du * all copies or substantial portions of the Software.
132605e60cSXiaojian Du *
142605e60cSXiaojian Du * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
152605e60cSXiaojian Du * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
162605e60cSXiaojian Du * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
172605e60cSXiaojian Du * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
182605e60cSXiaojian Du * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
192605e60cSXiaojian Du * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
202605e60cSXiaojian Du * OTHER DEALINGS IN THE SOFTWARE.
212605e60cSXiaojian Du *
222605e60cSXiaojian Du */
232605e60cSXiaojian Du #include "amdgpu.h"
242605e60cSXiaojian Du #include "amdgpu_psp.h"
252605e60cSXiaojian Du #include "amdgpu_ucode.h"
262605e60cSXiaojian Du #include "soc15_common.h"
272605e60cSXiaojian Du #include "psp_v13_0_4.h"
282605e60cSXiaojian Du
292605e60cSXiaojian Du #include "mp/mp_13_0_4_offset.h"
302605e60cSXiaojian Du #include "mp/mp_13_0_4_sh_mask.h"
312605e60cSXiaojian Du
322605e60cSXiaojian Du MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin");
332605e60cSXiaojian Du MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin");
342605e60cSXiaojian Du
psp_v13_0_4_init_microcode(struct psp_context * psp)352605e60cSXiaojian Du static int psp_v13_0_4_init_microcode(struct psp_context *psp)
362605e60cSXiaojian Du {
372605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev;
382605e60cSXiaojian Du char ucode_prefix[30];
392605e60cSXiaojian Du int err = 0;
402605e60cSXiaojian Du
412605e60cSXiaojian Du amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
422605e60cSXiaojian Du
432605e60cSXiaojian Du switch (adev->ip_versions[MP0_HWIP][0]) {
442605e60cSXiaojian Du case IP_VERSION(13, 0, 4):
45*2d39c7aeSMario Limonciello err = psp_init_toc_microcode(psp, ucode_prefix);
462605e60cSXiaojian Du if (err)
472605e60cSXiaojian Du return err;
48*2d39c7aeSMario Limonciello err = psp_init_ta_microcode(psp, ucode_prefix);
492605e60cSXiaojian Du if (err)
502605e60cSXiaojian Du return err;
512605e60cSXiaojian Du break;
522605e60cSXiaojian Du default:
532605e60cSXiaojian Du BUG();
542605e60cSXiaojian Du }
552605e60cSXiaojian Du
562605e60cSXiaojian Du return 0;
572605e60cSXiaojian Du }
582605e60cSXiaojian Du
psp_v13_0_4_is_sos_alive(struct psp_context * psp)592605e60cSXiaojian Du static bool psp_v13_0_4_is_sos_alive(struct psp_context *psp)
602605e60cSXiaojian Du {
612605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev;
622605e60cSXiaojian Du uint32_t sol_reg;
632605e60cSXiaojian Du
642605e60cSXiaojian Du sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
652605e60cSXiaojian Du
662605e60cSXiaojian Du return sol_reg != 0x0;
672605e60cSXiaojian Du }
682605e60cSXiaojian Du
psp_v13_0_4_wait_for_bootloader(struct psp_context * psp)692605e60cSXiaojian Du static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp)
702605e60cSXiaojian Du {
712605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev;
722605e60cSXiaojian Du
732605e60cSXiaojian Du int ret;
742605e60cSXiaojian Du int retry_loop;
752605e60cSXiaojian Du
762605e60cSXiaojian Du for (retry_loop = 0; retry_loop < 10; retry_loop++) {
772605e60cSXiaojian Du /* Wait for bootloader to signify that is
782605e60cSXiaojian Du ready having bit 31 of C2PMSG_35 set to 1 */
792605e60cSXiaojian Du ret = psp_wait_for(psp,
802605e60cSXiaojian Du SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
812605e60cSXiaojian Du 0x80000000,
822605e60cSXiaojian Du 0x80000000,
832605e60cSXiaojian Du false);
842605e60cSXiaojian Du
852605e60cSXiaojian Du if (ret == 0)
862605e60cSXiaojian Du return 0;
872605e60cSXiaojian Du }
882605e60cSXiaojian Du
892605e60cSXiaojian Du return ret;
902605e60cSXiaojian Du }
912605e60cSXiaojian Du
psp_v13_0_4_bootloader_load_component(struct psp_context * psp,struct psp_bin_desc * bin_desc,enum psp_bootloader_cmd bl_cmd)922605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_component(struct psp_context *psp,
932605e60cSXiaojian Du struct psp_bin_desc *bin_desc,
942605e60cSXiaojian Du enum psp_bootloader_cmd bl_cmd)
952605e60cSXiaojian Du {
962605e60cSXiaojian Du int ret;
972605e60cSXiaojian Du uint32_t psp_gfxdrv_command_reg = 0;
982605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev;
992605e60cSXiaojian Du
1002605e60cSXiaojian Du /* Check tOS sign of life register to confirm sys driver and sOS
1012605e60cSXiaojian Du * are already been loaded.
1022605e60cSXiaojian Du */
1032605e60cSXiaojian Du if (psp_v13_0_4_is_sos_alive(psp))
1042605e60cSXiaojian Du return 0;
1052605e60cSXiaojian Du
1062605e60cSXiaojian Du ret = psp_v13_0_4_wait_for_bootloader(psp);
1072605e60cSXiaojian Du if (ret)
1082605e60cSXiaojian Du return ret;
1092605e60cSXiaojian Du
1102605e60cSXiaojian Du memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1112605e60cSXiaojian Du
1122605e60cSXiaojian Du /* Copy PSP KDB binary to memory */
1132605e60cSXiaojian Du memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
1142605e60cSXiaojian Du
1152605e60cSXiaojian Du /* Provide the PSP KDB to bootloader */
1162605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
1172605e60cSXiaojian Du (uint32_t)(psp->fw_pri_mc_addr >> 20));
1182605e60cSXiaojian Du psp_gfxdrv_command_reg = bl_cmd;
1192605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
1202605e60cSXiaojian Du psp_gfxdrv_command_reg);
1212605e60cSXiaojian Du
1222605e60cSXiaojian Du ret = psp_v13_0_4_wait_for_bootloader(psp);
1232605e60cSXiaojian Du
1242605e60cSXiaojian Du return ret;
1252605e60cSXiaojian Du }
1262605e60cSXiaojian Du
psp_v13_0_4_bootloader_load_kdb(struct psp_context * psp)1272605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_kdb(struct psp_context *psp)
1282605e60cSXiaojian Du {
1292605e60cSXiaojian Du return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
1302605e60cSXiaojian Du }
1312605e60cSXiaojian Du
psp_v13_0_4_bootloader_load_spl(struct psp_context * psp)1322605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_spl(struct psp_context *psp)
1332605e60cSXiaojian Du {
1342605e60cSXiaojian Du return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
1352605e60cSXiaojian Du }
1362605e60cSXiaojian Du
psp_v13_0_4_bootloader_load_sysdrv(struct psp_context * psp)1372605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_sysdrv(struct psp_context *psp)
1382605e60cSXiaojian Du {
1392605e60cSXiaojian Du return psp_v13_0_4_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
1402605e60cSXiaojian Du }
1412605e60cSXiaojian Du
psp_v13_0_4_bootloader_load_soc_drv(struct psp_context * psp)1422605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_soc_drv(struct psp_context *psp)
1432605e60cSXiaojian Du {
1442605e60cSXiaojian Du return psp_v13_0_4_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
1452605e60cSXiaojian Du }
1462605e60cSXiaojian Du
psp_v13_0_4_bootloader_load_intf_drv(struct psp_context * psp)1472605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_intf_drv(struct psp_context *psp)
1482605e60cSXiaojian Du {
1492605e60cSXiaojian Du return psp_v13_0_4_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
1502605e60cSXiaojian Du }
1512605e60cSXiaojian Du
psp_v13_0_4_bootloader_load_dbg_drv(struct psp_context * psp)1522605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_dbg_drv(struct psp_context *psp)
1532605e60cSXiaojian Du {
1542605e60cSXiaojian Du return psp_v13_0_4_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
1552605e60cSXiaojian Du }
1562605e60cSXiaojian Du
psp_v13_0_4_bootloader_load_sos(struct psp_context * psp)1572605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_sos(struct psp_context *psp)
1582605e60cSXiaojian Du {
1592605e60cSXiaojian Du int ret;
1602605e60cSXiaojian Du unsigned int psp_gfxdrv_command_reg = 0;
1612605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev;
1622605e60cSXiaojian Du
1632605e60cSXiaojian Du /* Check sOS sign of life register to confirm sys driver and sOS
1642605e60cSXiaojian Du * are already been loaded.
1652605e60cSXiaojian Du */
1662605e60cSXiaojian Du if (psp_v13_0_4_is_sos_alive(psp))
1672605e60cSXiaojian Du return 0;
1682605e60cSXiaojian Du
1692605e60cSXiaojian Du ret = psp_v13_0_4_wait_for_bootloader(psp);
1702605e60cSXiaojian Du if (ret)
1712605e60cSXiaojian Du return ret;
1722605e60cSXiaojian Du
1732605e60cSXiaojian Du memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1742605e60cSXiaojian Du
1752605e60cSXiaojian Du /* Copy Secure OS binary to PSP memory */
1762605e60cSXiaojian Du memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
1772605e60cSXiaojian Du
1782605e60cSXiaojian Du /* Provide the PSP secure OS to bootloader */
1792605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
1802605e60cSXiaojian Du (uint32_t)(psp->fw_pri_mc_addr >> 20));
1812605e60cSXiaojian Du psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
1822605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
1832605e60cSXiaojian Du psp_gfxdrv_command_reg);
1842605e60cSXiaojian Du
1852605e60cSXiaojian Du /* there might be handshake issue with hardware which needs delay */
1862605e60cSXiaojian Du mdelay(20);
1872605e60cSXiaojian Du ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
1882605e60cSXiaojian Du RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
1892605e60cSXiaojian Du 0, true);
1902605e60cSXiaojian Du
1912605e60cSXiaojian Du return ret;
1922605e60cSXiaojian Du }
1932605e60cSXiaojian Du
psp_v13_0_4_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)1942605e60cSXiaojian Du static int psp_v13_0_4_ring_stop(struct psp_context *psp,
1952605e60cSXiaojian Du enum psp_ring_type ring_type)
1962605e60cSXiaojian Du {
1972605e60cSXiaojian Du int ret = 0;
1982605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev;
1992605e60cSXiaojian Du
2002605e60cSXiaojian Du if (amdgpu_sriov_vf(adev)) {
2012605e60cSXiaojian Du /* Write the ring destroy command*/
2022605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
2032605e60cSXiaojian Du GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
2042605e60cSXiaojian Du /* there might be handshake issue with hardware which needs delay */
2052605e60cSXiaojian Du mdelay(20);
2062605e60cSXiaojian Du /* Wait for response flag (bit 31) */
2072605e60cSXiaojian Du ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
2082605e60cSXiaojian Du 0x80000000, 0x80000000, false);
2092605e60cSXiaojian Du } else {
2102605e60cSXiaojian Du /* Write the ring destroy command*/
2112605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
2122605e60cSXiaojian Du GFX_CTRL_CMD_ID_DESTROY_RINGS);
2132605e60cSXiaojian Du /* there might be handshake issue with hardware which needs delay */
2142605e60cSXiaojian Du mdelay(20);
2152605e60cSXiaojian Du /* Wait for response flag (bit 31) */
2162605e60cSXiaojian Du ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
2172605e60cSXiaojian Du 0x80000000, 0x80000000, false);
2182605e60cSXiaojian Du }
2192605e60cSXiaojian Du
2202605e60cSXiaojian Du return ret;
2212605e60cSXiaojian Du }
2222605e60cSXiaojian Du
psp_v13_0_4_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)2232605e60cSXiaojian Du static int psp_v13_0_4_ring_create(struct psp_context *psp,
2242605e60cSXiaojian Du enum psp_ring_type ring_type)
2252605e60cSXiaojian Du {
2262605e60cSXiaojian Du int ret = 0;
2272605e60cSXiaojian Du unsigned int psp_ring_reg = 0;
2282605e60cSXiaojian Du struct psp_ring *ring = &psp->km_ring;
2292605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev;
2302605e60cSXiaojian Du
2312605e60cSXiaojian Du if (amdgpu_sriov_vf(adev)) {
2322605e60cSXiaojian Du ret = psp_v13_0_4_ring_stop(psp, ring_type);
2332605e60cSXiaojian Du if (ret) {
2342605e60cSXiaojian Du DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
2352605e60cSXiaojian Du return ret;
2362605e60cSXiaojian Du }
2372605e60cSXiaojian Du
2382605e60cSXiaojian Du /* Write low address of the ring to C2PMSG_102 */
2392605e60cSXiaojian Du psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
2402605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
2412605e60cSXiaojian Du /* Write high address of the ring to C2PMSG_103 */
2422605e60cSXiaojian Du psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
2432605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
2442605e60cSXiaojian Du
2452605e60cSXiaojian Du /* Write the ring initialization command to C2PMSG_101 */
2462605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
2472605e60cSXiaojian Du GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
2482605e60cSXiaojian Du
2492605e60cSXiaojian Du /* there might be handshake issue with hardware which needs delay */
2502605e60cSXiaojian Du mdelay(20);
2512605e60cSXiaojian Du
2522605e60cSXiaojian Du /* Wait for response flag (bit 31) in C2PMSG_101 */
2532605e60cSXiaojian Du ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
2542605e60cSXiaojian Du 0x80000000, 0x8000FFFF, false);
2552605e60cSXiaojian Du
2562605e60cSXiaojian Du } else {
2572605e60cSXiaojian Du /* Wait for sOS ready for ring creation */
2582605e60cSXiaojian Du ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
2592605e60cSXiaojian Du 0x80000000, 0x80000000, false);
2602605e60cSXiaojian Du if (ret) {
2612605e60cSXiaojian Du DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
2622605e60cSXiaojian Du return ret;
2632605e60cSXiaojian Du }
2642605e60cSXiaojian Du
2652605e60cSXiaojian Du /* Write low address of the ring to C2PMSG_69 */
2662605e60cSXiaojian Du psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
2672605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
2682605e60cSXiaojian Du /* Write high address of the ring to C2PMSG_70 */
2692605e60cSXiaojian Du psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
2702605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
2712605e60cSXiaojian Du /* Write size of ring to C2PMSG_71 */
2722605e60cSXiaojian Du psp_ring_reg = ring->ring_size;
2732605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
2742605e60cSXiaojian Du /* Write the ring initialization command to C2PMSG_64 */
2752605e60cSXiaojian Du psp_ring_reg = ring_type;
2762605e60cSXiaojian Du psp_ring_reg = psp_ring_reg << 16;
2772605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
2782605e60cSXiaojian Du
2792605e60cSXiaojian Du /* there might be handshake issue with hardware which needs delay */
2802605e60cSXiaojian Du mdelay(20);
2812605e60cSXiaojian Du
2822605e60cSXiaojian Du /* Wait for response flag (bit 31) in C2PMSG_64 */
2832605e60cSXiaojian Du ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
2842605e60cSXiaojian Du 0x80000000, 0x8000FFFF, false);
2852605e60cSXiaojian Du }
2862605e60cSXiaojian Du
2872605e60cSXiaojian Du return ret;
2882605e60cSXiaojian Du }
2892605e60cSXiaojian Du
psp_v13_0_4_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)2902605e60cSXiaojian Du static int psp_v13_0_4_ring_destroy(struct psp_context *psp,
2912605e60cSXiaojian Du enum psp_ring_type ring_type)
2922605e60cSXiaojian Du {
2932605e60cSXiaojian Du int ret = 0;
2942605e60cSXiaojian Du struct psp_ring *ring = &psp->km_ring;
2952605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev;
2962605e60cSXiaojian Du
2972605e60cSXiaojian Du ret = psp_v13_0_4_ring_stop(psp, ring_type);
2982605e60cSXiaojian Du if (ret)
2992605e60cSXiaojian Du DRM_ERROR("Fail to stop psp ring\n");
3002605e60cSXiaojian Du
3012605e60cSXiaojian Du amdgpu_bo_free_kernel(&adev->firmware.rbuf,
3022605e60cSXiaojian Du &ring->ring_mem_mc_addr,
3032605e60cSXiaojian Du (void **)&ring->ring_mem);
3042605e60cSXiaojian Du
3052605e60cSXiaojian Du return ret;
3062605e60cSXiaojian Du }
3072605e60cSXiaojian Du
psp_v13_0_4_ring_get_wptr(struct psp_context * psp)3082605e60cSXiaojian Du static uint32_t psp_v13_0_4_ring_get_wptr(struct psp_context *psp)
3092605e60cSXiaojian Du {
3102605e60cSXiaojian Du uint32_t data;
3112605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev;
3122605e60cSXiaojian Du
3132605e60cSXiaojian Du if (amdgpu_sriov_vf(adev))
3142605e60cSXiaojian Du data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
3152605e60cSXiaojian Du else
3162605e60cSXiaojian Du data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
3172605e60cSXiaojian Du
3182605e60cSXiaojian Du return data;
3192605e60cSXiaojian Du }
3202605e60cSXiaojian Du
psp_v13_0_4_ring_set_wptr(struct psp_context * psp,uint32_t value)3212605e60cSXiaojian Du static void psp_v13_0_4_ring_set_wptr(struct psp_context *psp, uint32_t value)
3222605e60cSXiaojian Du {
3232605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev;
3242605e60cSXiaojian Du
3252605e60cSXiaojian Du if (amdgpu_sriov_vf(adev)) {
3262605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
3272605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
3282605e60cSXiaojian Du GFX_CTRL_CMD_ID_CONSUME_CMD);
3292605e60cSXiaojian Du } else
3302605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
3312605e60cSXiaojian Du }
3322605e60cSXiaojian Du
3332605e60cSXiaojian Du static const struct psp_funcs psp_v13_0_4_funcs = {
3342605e60cSXiaojian Du .init_microcode = psp_v13_0_4_init_microcode,
3352605e60cSXiaojian Du .bootloader_load_kdb = psp_v13_0_4_bootloader_load_kdb,
3362605e60cSXiaojian Du .bootloader_load_spl = psp_v13_0_4_bootloader_load_spl,
3372605e60cSXiaojian Du .bootloader_load_sysdrv = psp_v13_0_4_bootloader_load_sysdrv,
3382605e60cSXiaojian Du .bootloader_load_soc_drv = psp_v13_0_4_bootloader_load_soc_drv,
3392605e60cSXiaojian Du .bootloader_load_intf_drv = psp_v13_0_4_bootloader_load_intf_drv,
3402605e60cSXiaojian Du .bootloader_load_dbg_drv = psp_v13_0_4_bootloader_load_dbg_drv,
3412605e60cSXiaojian Du .bootloader_load_sos = psp_v13_0_4_bootloader_load_sos,
3422605e60cSXiaojian Du .ring_create = psp_v13_0_4_ring_create,
3432605e60cSXiaojian Du .ring_stop = psp_v13_0_4_ring_stop,
3442605e60cSXiaojian Du .ring_destroy = psp_v13_0_4_ring_destroy,
3452605e60cSXiaojian Du .ring_get_wptr = psp_v13_0_4_ring_get_wptr,
3462605e60cSXiaojian Du .ring_set_wptr = psp_v13_0_4_ring_set_wptr,
3472605e60cSXiaojian Du };
3482605e60cSXiaojian Du
psp_v13_0_4_set_psp_funcs(struct psp_context * psp)3492605e60cSXiaojian Du void psp_v13_0_4_set_psp_funcs(struct psp_context *psp)
3502605e60cSXiaojian Du {
3512605e60cSXiaojian Du psp->funcs = &psp_v13_0_4_funcs;
3522605e60cSXiaojian Du }
353