197b2e202SAlex Deucher /*
297b2e202SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc.
397b2e202SAlex Deucher * Copyright 2008 Red Hat Inc.
497b2e202SAlex Deucher * Copyright 2009 Jerome Glisse.
597b2e202SAlex Deucher *
697b2e202SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a
797b2e202SAlex Deucher * copy of this software and associated documentation files (the "Software"),
897b2e202SAlex Deucher * to deal in the Software without restriction, including without limitation
997b2e202SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1097b2e202SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the
1197b2e202SAlex Deucher * Software is furnished to do so, subject to the following conditions:
1297b2e202SAlex Deucher *
1397b2e202SAlex Deucher * The above copyright notice and this permission notice shall be included in
1497b2e202SAlex Deucher * all copies or substantial portions of the Software.
1597b2e202SAlex Deucher *
1697b2e202SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1797b2e202SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1897b2e202SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1997b2e202SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
2097b2e202SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
2197b2e202SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2297b2e202SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE.
2397b2e202SAlex Deucher *
2497b2e202SAlex Deucher * Authors: Dave Airlie
2597b2e202SAlex Deucher * Alex Deucher
2697b2e202SAlex Deucher * Jerome Glisse
2797b2e202SAlex Deucher */
2897b2e202SAlex Deucher #ifndef __AMDGPU_H__
2997b2e202SAlex Deucher #define __AMDGPU_H__
3097b2e202SAlex Deucher
31d57229b1SAurabindo Pillai #ifdef pr_fmt
32d57229b1SAurabindo Pillai #undef pr_fmt
33d57229b1SAurabindo Pillai #endif
34d57229b1SAurabindo Pillai
35d57229b1SAurabindo Pillai #define pr_fmt(fmt) "amdgpu: " fmt
36d57229b1SAurabindo Pillai
37539489fcSAurabindo Pillai #ifdef dev_fmt
38539489fcSAurabindo Pillai #undef dev_fmt
39539489fcSAurabindo Pillai #endif
40539489fcSAurabindo Pillai
41539489fcSAurabindo Pillai #define dev_fmt(fmt) "amdgpu: " fmt
42539489fcSAurabindo Pillai
438290268fSChristian König #include "amdgpu_ctx.h"
448290268fSChristian König
4597b2e202SAlex Deucher #include <linux/atomic.h>
4697b2e202SAlex Deucher #include <linux/wait.h>
4797b2e202SAlex Deucher #include <linux/list.h>
4897b2e202SAlex Deucher #include <linux/kref.h>
49a9f87f64SChristian König #include <linux/rbtree.h>
5097b2e202SAlex Deucher #include <linux/hashtable.h>
51f54d1867SChris Wilson #include <linux/dma-fence.h>
52c9a6b82fSAndrey Grodzovsky #include <linux/pci.h>
5397b2e202SAlex Deucher
54a3185f91SChristian König #include <drm/ttm/ttm_bo.h>
55248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_placement.h>
5697b2e202SAlex Deucher
577e5a547fSChunming Zhou #include <drm/amdgpu_drm.h>
58f867723bSSam Ravnborg #include <drm/drm_gem.h>
59f867723bSSam Ravnborg #include <drm/drm_ioctl.h>
6097b2e202SAlex Deucher
6178c16834SAndres Rodriguez #include <kgd_kfd_interface.h>
62c79563a3SRex Zhu #include "dm_pp_interface.h"
63c79563a3SRex Zhu #include "kgd_pp_interface.h"
6478c16834SAndres Rodriguez
655fc3aeebSyanyang1 #include "amd_shared.h"
6697b2e202SAlex Deucher #include "amdgpu_mode.h"
6797b2e202SAlex Deucher #include "amdgpu_ih.h"
6897b2e202SAlex Deucher #include "amdgpu_irq.h"
6997b2e202SAlex Deucher #include "amdgpu_ucode.h"
70c632d799SFlora Cui #include "amdgpu_ttm.h"
710e5ca0d1SHuang Rui #include "amdgpu_psp.h"
7297b2e202SAlex Deucher #include "amdgpu_gds.h"
7356113504SChristian König #include "amdgpu_sync.h"
7478023016SChristian König #include "amdgpu_ring.h"
75073440d2SChristian König #include "amdgpu_vm.h"
76cf097881SAlex Deucher #include "amdgpu_dpm.h"
77a8fe58ceSMaruthi Bayyavarapu #include "amdgpu_acp.h"
784df654d2SLeo Liu #include "amdgpu_uvd.h"
795e568178SLeo Liu #include "amdgpu_vce.h"
8095aa13f6SLeo Liu #include "amdgpu_vcn.h"
8188a1c40aSLeo Liu #include "amdgpu_jpeg.h"
82770d13b1SChristian König #include "amdgpu_gmc.h"
83448fe192SHuang Rui #include "amdgpu_gfx.h"
84bb7743bcSHuang Rui #include "amdgpu_sdma.h"
851b491330SLikun Gao #include "amdgpu_lsdma.h"
86bebc0762SHawking Zhang #include "amdgpu_nbio.h"
87455d40c9SLikun Gao #include "amdgpu_hdp.h"
884562236bSHarry Wentland #include "amdgpu_dm.h"
89ceeb50edSMonk Liu #include "amdgpu_virt.h"
907946340fSRex Zhu #include "amdgpu_csa.h"
912bc956efSJack Xiao #include "amdgpu_mes_ctx.h"
923490bdb5SChristian König #include "amdgpu_gart.h"
9375758255SAlex Deucher #include "amdgpu_debugfs.h"
94050d9d43SChristian König #include "amdgpu_job.h"
954a8c21a1SChristian König #include "amdgpu_bo_list.h"
962cddc50eSHuang Rui #include "amdgpu_gem.h"
97cde577bdSOak Zeng #include "amdgpu_doorbell.h"
98611736d8SFelix Kuehling #include "amdgpu_amdkfd.h"
99f39f5bb1SXiaojie Yuan #include "amdgpu_discovery.h"
100a538bbe7SJack Xiao #include "amdgpu_mes.h"
1019e585a52SHawking Zhang #include "amdgpu_umc.h"
1023d093da0STao Zhou #include "amdgpu_mmhub.h"
1038ffff9b4SOak Zeng #include "amdgpu_gfxhub.h"
104bdf84a80SJoseph Greathouse #include "amdgpu_df.h"
105293f2563SHawking Zhang #include "amdgpu_smuio.h"
10687444254SRoy Sun #include "amdgpu_fdinfo.h"
1073907c492SJohn Clements #include "amdgpu_mca.h"
1087cab2124Syipechai #include "amdgpu_ras.h"
1092c1c7ba4SJames Zhu #include "amdgpu_xcp.h"
110c79563a3SRex Zhu
1119e4216cfSMukul Joshi #define MAX_GPU_INSTANCE 64
11262d73fbcSEvan Quan
11362d73fbcSEvan Quan struct amdgpu_gpu_instance
11462d73fbcSEvan Quan {
11562d73fbcSEvan Quan struct amdgpu_device *adev;
11662d73fbcSEvan Quan int mgpu_fan_enabled;
11762d73fbcSEvan Quan };
11862d73fbcSEvan Quan
11962d73fbcSEvan Quan struct amdgpu_mgpu_info
12062d73fbcSEvan Quan {
12162d73fbcSEvan Quan struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
12262d73fbcSEvan Quan struct mutex mutex;
12362d73fbcSEvan Quan uint32_t num_gpu;
12462d73fbcSEvan Quan uint32_t num_dgpu;
12562d73fbcSEvan Quan uint32_t num_apu;
126e3c1b071Sshaoyunl
127e3c1b071Sshaoyunl /* delayed reset_func for XGMI configuration if necessary */
128e3c1b071Sshaoyunl struct delayed_work delayed_reset_work;
129e3c1b071Sshaoyunl bool pending_reset;
13062d73fbcSEvan Quan };
13162d73fbcSEvan Quan
1323fa8f89dSSathishkumar S enum amdgpu_ss {
1333fa8f89dSSathishkumar S AMDGPU_SS_DRV_LOAD,
1343fa8f89dSSathishkumar S AMDGPU_SS_DEV_D0,
1353fa8f89dSSathishkumar S AMDGPU_SS_DEV_D3,
1363fa8f89dSSathishkumar S AMDGPU_SS_DRV_UNLOAD
1373fa8f89dSSathishkumar S };
1383fa8f89dSSathishkumar S
13988f8575bSDennis Li struct amdgpu_watchdog_timer
14088f8575bSDennis Li {
14188f8575bSDennis Li bool timeout_fatal_disable;
14288f8575bSDennis Li uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
143b80d8475SAlex Deucher };
14497b2e202SAlex Deucher
145f440ff44SWambui Karuga #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
14671f98027SAlex Deucher
14797b2e202SAlex Deucher /*
14897b2e202SAlex Deucher * Modules parameters.
14997b2e202SAlex Deucher */
15097b2e202SAlex Deucher extern int amdgpu_modeset;
1510b04ea39SChristian König extern unsigned int amdgpu_vram_limit;
152218b5dcdSJohn Brooks extern int amdgpu_vis_vram_limit;
15383e74db6SAlex Deucher extern int amdgpu_gart_size;
15436d38372SChristian König extern int amdgpu_gtt_size;
15595844d20SMarek Olšák extern int amdgpu_moverate;
15697b2e202SAlex Deucher extern int amdgpu_audio;
15797b2e202SAlex Deucher extern int amdgpu_disp_priority;
15897b2e202SAlex Deucher extern int amdgpu_hw_i2c;
15997b2e202SAlex Deucher extern int amdgpu_pcie_gen2;
16097b2e202SAlex Deucher extern int amdgpu_msi;
161f440ff44SWambui Karuga extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
16297b2e202SAlex Deucher extern int amdgpu_dpm;
163e635ee07SHuang Rui extern int amdgpu_fw_load_type;
16497b2e202SAlex Deucher extern int amdgpu_aspm;
16597b2e202SAlex Deucher extern int amdgpu_runtime_pm;
1660b693f0bSRex Zhu extern uint amdgpu_ip_block_mask;
16797b2e202SAlex Deucher extern int amdgpu_bapm;
16897b2e202SAlex Deucher extern int amdgpu_deep_color;
16997b2e202SAlex Deucher extern int amdgpu_vm_size;
17097b2e202SAlex Deucher extern int amdgpu_vm_block_size;
171d07f14beSRoger He extern int amdgpu_vm_fragment_size;
172d9c13156SChristian König extern int amdgpu_vm_fault_stop;
173b495bd3aSChristian König extern int amdgpu_vm_debug;
1749a4b7d4cSHarish Kasiviswanathan extern int amdgpu_vm_update_mode;
1757e0ff20cSWambui Karuga extern int amdgpu_exp_hw_support;
1764562236bSHarry Wentland extern int amdgpu_dc;
1771333f723SJammy Zhou extern int amdgpu_sched_jobs;
1784afcb303SJammy Zhou extern int amdgpu_sched_hw_submission;
1790b693f0bSRex Zhu extern uint amdgpu_pcie_gen_cap;
1800b693f0bSRex Zhu extern uint amdgpu_pcie_lane_cap;
18125faeddcSEvan Quan extern u64 amdgpu_cg_mask;
1820b693f0bSRex Zhu extern uint amdgpu_pg_mask;
1830b693f0bSRex Zhu extern uint amdgpu_sdma_phase_quantum;
1846f8941a2SNicolai Hähnle extern char *amdgpu_disable_cu;
1859accf2fdSEmily Deng extern char *amdgpu_virtual_display;
1860b693f0bSRex Zhu extern uint amdgpu_pp_feature_mask;
187367039bfSTianci.Yin extern uint amdgpu_force_long_training;
188e8835e0eSHawking Zhang extern int amdgpu_lbpw;
1894a75aefeSAndres Rodriguez extern int amdgpu_compute_multipipe;
190dcebf026SAndrey Grodzovsky extern int amdgpu_gpu_recovery;
191bfca0289SShaoyun Liu extern int amdgpu_emu_mode;
1927951e376SRex Zhu extern uint amdgpu_smu_memory_pool_size;
1938738a82bSLijo Lazar extern int amdgpu_smu_pptable_id;
1947875a226SAlex Deucher extern uint amdgpu_dc_feature_mask;
1958a791dabSHarry Wentland extern uint amdgpu_dc_debug_mask;
196792a0cddSLeo Li extern uint amdgpu_dc_visual_confirm;
197ad4de27fSNicholas Kazlauskas extern uint amdgpu_dm_abm_level;
1987a46f05eSTakashi Iwai extern int amdgpu_backlight;
19962d73fbcSEvan Quan extern struct amdgpu_mgpu_info mgpu_info;
2001218252fSxinhui pan extern int amdgpu_ras_enable;
2011218252fSxinhui pan extern uint amdgpu_ras_mask;
202acc0204cSGuchun Chen extern int amdgpu_bad_page_threshold;
20368daadf3SKent Russell extern bool amdgpu_ignore_bad_page_threshold;
20488f8575bSDennis Li extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
20551bcce46SHawking Zhang extern int amdgpu_async_gfx_ring;
206b239c017SJack Xiao extern int amdgpu_mcbp;
207a190d1c7SXiaojie Yuan extern int amdgpu_discovery;
20838487284SJack Xiao extern int amdgpu_mes;
209928fe236SJack Xiao extern int amdgpu_mes_kiq;
21075ee6487SFelix Kuehling extern int amdgpu_noretry;
2114e66d7d2SYong Zhao extern int amdgpu_force_asic_type;
21230d95a37SSathishkumar S extern int amdgpu_smartshift_bias;
213158a05a0SAlex Sierra extern int amdgpu_use_xgmi_p2p;
21476eb9c95SDavid Francis extern int amdgpu_mtype_local;
21580e709eeSChong Li extern bool enforce_isolation;
2168c9f69bcSShirish S #ifdef CONFIG_HSA_AMD
217aa978594SHuang Rui extern int sched_policy;
218b2057956SFelix Kuehling extern bool debug_evictions;
219b80f050fSPhilip Yang extern bool no_system_mem_limit;
2209a1662f5SGraham Sider extern int halt_if_hws_hang;
221a35ad98bSShirish S #else
22202f40f82SLee Jones static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
22302f40f82SLee Jones static const bool __maybe_unused debug_evictions; /* = false */
22402f40f82SLee Jones static const bool __maybe_unused no_system_mem_limit;
2259a1662f5SGraham Sider static const int __maybe_unused halt_if_hws_hang;
2268c9f69bcSShirish S #endif
22708a2fd23SRamesh Errabolu #ifdef CONFIG_HSA_AMD_P2P
22808a2fd23SRamesh Errabolu extern bool pcie_p2p;
22908a2fd23SRamesh Errabolu #endif
23097b2e202SAlex Deucher
231d7ccb38dSHuang Rui extern int amdgpu_tmz;
232273da6ffSWenhui Sheng extern int amdgpu_reset_method;
233d7ccb38dSHuang Rui
2346dd13096SFelix Kuehling #ifdef CONFIG_DRM_AMDGPU_SI
2356dd13096SFelix Kuehling extern int amdgpu_si_support;
2366dd13096SFelix Kuehling #endif
2377df28986SFelix Kuehling #ifdef CONFIG_DRM_AMDGPU_CIK
2387df28986SFelix Kuehling extern int amdgpu_cik_support;
2397df28986SFelix Kuehling #endif
240a300de40SMonk Liu extern int amdgpu_num_kcq;
24197b2e202SAlex Deucher
24211eb648dSRuijing Dong #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
24311eb648dSRuijing Dong extern int amdgpu_vcnfw_log;
244bf0207e1SAlex Deucher extern int amdgpu_sg_display;
24511eb648dSRuijing Dong
246570de94bSLijo Lazar extern int amdgpu_user_partt_mode;
2470fa49d10SShiwu Zhang
24808d1bdd4SRex Zhu #define AMDGPU_VM_MAX_NUM_CTX 4096
2496c8d74caSSamuel Li #define AMDGPU_SG_THRESHOLD (256*1024*1024)
2504b559c90SChunming Zhou #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
25197b2e202SAlex Deucher #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
2528c5e13ecSAndrey Grodzovsky #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
25397b2e202SAlex Deucher #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
25497b2e202SAlex Deucher #define AMDGPUFB_CONN_LIMIT 4
255a5bde2f9SAlex Deucher #define AMDGPU_BIOS_NUM_SCRATCH 16
25697b2e202SAlex Deucher
25781b54fb7SAlex Deucher #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
25881b54fb7SAlex Deucher
25997b2e202SAlex Deucher /* hard reset data */
26097b2e202SAlex Deucher #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
26197b2e202SAlex Deucher
26297b2e202SAlex Deucher /* reset flags */
26397b2e202SAlex Deucher #define AMDGPU_RESET_GFX (1 << 0)
26497b2e202SAlex Deucher #define AMDGPU_RESET_COMPUTE (1 << 1)
26597b2e202SAlex Deucher #define AMDGPU_RESET_DMA (1 << 2)
26697b2e202SAlex Deucher #define AMDGPU_RESET_CP (1 << 3)
26797b2e202SAlex Deucher #define AMDGPU_RESET_GRBM (1 << 4)
26897b2e202SAlex Deucher #define AMDGPU_RESET_DMA1 (1 << 5)
26997b2e202SAlex Deucher #define AMDGPU_RESET_RLC (1 << 6)
27097b2e202SAlex Deucher #define AMDGPU_RESET_SEM (1 << 7)
27197b2e202SAlex Deucher #define AMDGPU_RESET_IH (1 << 8)
27297b2e202SAlex Deucher #define AMDGPU_RESET_VMC (1 << 9)
27397b2e202SAlex Deucher #define AMDGPU_RESET_MC (1 << 10)
27497b2e202SAlex Deucher #define AMDGPU_RESET_DISPLAY (1 << 11)
27597b2e202SAlex Deucher #define AMDGPU_RESET_UVD (1 << 12)
27697b2e202SAlex Deucher #define AMDGPU_RESET_VCE (1 << 13)
27797b2e202SAlex Deucher #define AMDGPU_RESET_VCE1 (1 << 14)
27897b2e202SAlex Deucher
27997b2e202SAlex Deucher /* max cursor sizes (in pixels) */
28097b2e202SAlex Deucher #define CIK_CURSOR_WIDTH 128
28197b2e202SAlex Deucher #define CIK_CURSOR_HEIGHT 128
28297b2e202SAlex Deucher
283faf26f2bSpengfuyuan /* smart shift bias level limits */
28430d95a37SSathishkumar S #define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
28530d95a37SSathishkumar S #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
28630d95a37SSathishkumar S
287b75efe88SEvan Quan /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */
288b75efe88SEvan Quan #define AMDGPU_SWCTF_EXTRA_DELAY 50
289b75efe88SEvan Quan
29075d16923SLijo Lazar struct amdgpu_xcp_mgr;
29197b2e202SAlex Deucher struct amdgpu_device;
29297b2e202SAlex Deucher struct amdgpu_irq_src;
2930b492a4cSAlex Deucher struct amdgpu_fpriv;
2949cca0b8eSChristian König struct amdgpu_bo_va_mapping;
295992af942SJonathan Kim struct kfd_vm_fault_info;
296d95e8e97SDennis Li struct amdgpu_hive_info;
29704442bf7SLijo Lazar struct amdgpu_reset_context;
298e071dce3SLijo Lazar struct amdgpu_reset_control;
29997b2e202SAlex Deucher
30097b2e202SAlex Deucher enum amdgpu_cp_irq {
30153b2fe41SHawking Zhang AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
30253b2fe41SHawking Zhang AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
30397b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
30497b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
30597b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
30697b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
30797b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
30897b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
30997b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
31097b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
31197b2e202SAlex Deucher
31297b2e202SAlex Deucher AMDGPU_CP_IRQ_LAST
31397b2e202SAlex Deucher };
31497b2e202SAlex Deucher
31597b2e202SAlex Deucher enum amdgpu_thermal_irq {
31697b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
31797b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
31897b2e202SAlex Deucher
31997b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LAST
32097b2e202SAlex Deucher };
32197b2e202SAlex Deucher
3224e638ae9SXiangliang Yu enum amdgpu_kiq_irq {
3234e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
3244e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_LAST
3254e638ae9SXiangliang Yu };
326373008bfSDusica Milinkovic #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
3273890d111SEmily Deng #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
3283890d111SEmily Deng #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
329006cc1a2SJiawei Gu #define MAX_KIQ_REG_TRY 1000
3303890d111SEmily Deng
33143fa561fSRex Zhu int amdgpu_device_ip_set_clockgating_state(void *dev,
3325fc3aeebSyanyang1 enum amd_ip_block_type block_type,
3335fc3aeebSyanyang1 enum amd_clockgating_state state);
33443fa561fSRex Zhu int amdgpu_device_ip_set_powergating_state(void *dev,
3355fc3aeebSyanyang1 enum amd_ip_block_type block_type,
3365fc3aeebSyanyang1 enum amd_powergating_state state);
3372990a1fcSAlex Deucher void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
33825faeddcSEvan Quan u64 *flags);
3392990a1fcSAlex Deucher int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
3405dbbb60bSAlex Deucher enum amd_ip_block_type block_type);
3412990a1fcSAlex Deucher bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
3425dbbb60bSAlex Deucher enum amd_ip_block_type block_type);
34397b2e202SAlex Deucher
344a1255107SAlex Deucher #define AMDGPU_MAX_IP_NUM 16
345a1255107SAlex Deucher
346a1255107SAlex Deucher struct amdgpu_ip_block_status {
347a1255107SAlex Deucher bool valid;
348a1255107SAlex Deucher bool sw;
349a1255107SAlex Deucher bool hw;
350a1255107SAlex Deucher bool late_initialized;
351a1255107SAlex Deucher bool hang;
352a1255107SAlex Deucher };
353a1255107SAlex Deucher
35497b2e202SAlex Deucher struct amdgpu_ip_block_version {
355a1255107SAlex Deucher const enum amd_ip_block_type type;
356a1255107SAlex Deucher const u32 major;
357a1255107SAlex Deucher const u32 minor;
358a1255107SAlex Deucher const u32 rev;
3595fc3aeebSyanyang1 const struct amd_ip_funcs *funcs;
36097b2e202SAlex Deucher };
36197b2e202SAlex Deucher
362efe4f000STianci.Yin #define HW_REV(_Major, _Minor, _Rev) \
363efe4f000STianci.Yin ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
364efe4f000STianci.Yin
365a1255107SAlex Deucher struct amdgpu_ip_block {
366a1255107SAlex Deucher struct amdgpu_ip_block_status status;
367a1255107SAlex Deucher const struct amdgpu_ip_block_version *version;
368a1255107SAlex Deucher };
369a1255107SAlex Deucher
3702990a1fcSAlex Deucher int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
3715fc3aeebSyanyang1 enum amd_ip_block_type type,
37297b2e202SAlex Deucher u32 major, u32 minor);
37397b2e202SAlex Deucher
3742990a1fcSAlex Deucher struct amdgpu_ip_block *
3752990a1fcSAlex Deucher amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
3765fc3aeebSyanyang1 enum amd_ip_block_type type);
37797b2e202SAlex Deucher
3782990a1fcSAlex Deucher int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
379a1255107SAlex Deucher const struct amdgpu_ip_block_version *ip_block_version);
380a1255107SAlex Deucher
38197b2e202SAlex Deucher /*
38297b2e202SAlex Deucher * BIOS.
38397b2e202SAlex Deucher */
38497b2e202SAlex Deucher bool amdgpu_get_bios(struct amdgpu_device *adev);
38597b2e202SAlex Deucher bool amdgpu_read_bios(struct amdgpu_device *adev);
38604022982SHawking Zhang bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
38704022982SHawking Zhang u8 *bios, u32 length_bytes);
38897b2e202SAlex Deucher /*
38997b2e202SAlex Deucher * Clocks
39097b2e202SAlex Deucher */
39197b2e202SAlex Deucher
39297b2e202SAlex Deucher #define AMDGPU_MAX_PPLL 3
39397b2e202SAlex Deucher
39497b2e202SAlex Deucher struct amdgpu_clock {
39597b2e202SAlex Deucher struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
39697b2e202SAlex Deucher struct amdgpu_pll spll;
39797b2e202SAlex Deucher struct amdgpu_pll mpll;
39897b2e202SAlex Deucher /* 10 Khz units */
39997b2e202SAlex Deucher uint32_t default_mclk;
40097b2e202SAlex Deucher uint32_t default_sclk;
40197b2e202SAlex Deucher uint32_t default_dispclk;
40297b2e202SAlex Deucher uint32_t current_dispclk;
40397b2e202SAlex Deucher uint32_t dp_extclk;
40497b2e202SAlex Deucher uint32_t max_pixel_clock;
40597b2e202SAlex Deucher };
40697b2e202SAlex Deucher
40797b2e202SAlex Deucher /* sub-allocation manager, it has to be protected by another lock.
40897b2e202SAlex Deucher * By conception this is an helper for other part of the driver
40997b2e202SAlex Deucher * like the indirect buffer or semaphore, which both have their
41097b2e202SAlex Deucher * locking.
41197b2e202SAlex Deucher *
41297b2e202SAlex Deucher * Principe is simple, we keep a list of sub allocation in offset
41397b2e202SAlex Deucher * order (first entry has offset == 0, last entry has the highest
41497b2e202SAlex Deucher * offset).
41597b2e202SAlex Deucher *
41697b2e202SAlex Deucher * When allocating new object we first check if there is room at
41797b2e202SAlex Deucher * the end total_size - (last_object_offset + last_object_size) >=
41897b2e202SAlex Deucher * alloc_size. If so we allocate new object there.
41997b2e202SAlex Deucher *
42097b2e202SAlex Deucher * When there is not enough room at the end, we start waiting for
42197b2e202SAlex Deucher * each sub object until we reach object_offset+object_size >=
42297b2e202SAlex Deucher * alloc_size, this object then become the sub object we return.
42397b2e202SAlex Deucher *
42497b2e202SAlex Deucher * Alignment can't be bigger than page size.
42597b2e202SAlex Deucher *
42697b2e202SAlex Deucher * Hole are not considered for allocation to keep things simple.
42797b2e202SAlex Deucher * Assumption is that there won't be hole (all object on same
42897b2e202SAlex Deucher * alignment).
42997b2e202SAlex Deucher */
4306ba60b89SChristian König
43197b2e202SAlex Deucher struct amdgpu_sa_manager {
432c103a23fSMaarten Lankhorst struct drm_suballoc_manager base;
43397b2e202SAlex Deucher struct amdgpu_bo *bo;
43497b2e202SAlex Deucher uint64_t gpu_addr;
43597b2e202SAlex Deucher void *cpu_ptr;
43697b2e202SAlex Deucher };
43797b2e202SAlex Deucher
438d573de2dSRex Zhu int amdgpu_fence_slab_init(void);
439d573de2dSRex Zhu void amdgpu_fence_slab_fini(void);
44097b2e202SAlex Deucher
44197b2e202SAlex Deucher /*
44297b2e202SAlex Deucher * IRQS.
44397b2e202SAlex Deucher */
44497b2e202SAlex Deucher
44597b2e202SAlex Deucher struct amdgpu_flip_work {
446325cbba1SMichel Dänzer struct delayed_work flip_work;
44797b2e202SAlex Deucher struct work_struct unpin_work;
44897b2e202SAlex Deucher struct amdgpu_device *adev;
44997b2e202SAlex Deucher int crtc_id;
450325cbba1SMichel Dänzer u32 target_vblank;
45197b2e202SAlex Deucher uint64_t base;
45297b2e202SAlex Deucher struct drm_pending_vblank_event *event;
453765e7fbfSChristian König struct amdgpu_bo *old_abo;
4541ffd2652SChristian König unsigned shared_count;
455f54d1867SChris Wilson struct dma_fence **shared;
456f54d1867SChris Wilson struct dma_fence_cb cb;
457cb9e59d7SAlex Deucher bool async;
45897b2e202SAlex Deucher };
45997b2e202SAlex Deucher
46097b2e202SAlex Deucher
46197b2e202SAlex Deucher /*
46297b2e202SAlex Deucher * file private structure
46397b2e202SAlex Deucher */
46497b2e202SAlex Deucher
46597b2e202SAlex Deucher struct amdgpu_fpriv {
46697b2e202SAlex Deucher struct amdgpu_vm vm;
467b85891bdSJunwei Zhang struct amdgpu_bo_va *prt_va;
4680f4b3c68SChristian König struct amdgpu_bo_va *csa_va;
46997b2e202SAlex Deucher struct mutex bo_list_lock;
47097b2e202SAlex Deucher struct idr bo_list_handles;
47197b2e202SAlex Deucher struct amdgpu_ctx_mgr ctx_mgr;
472be3800f5SJames Zhu /** GPU partition selection */
473be3800f5SJames Zhu uint32_t xcp_id;
47497b2e202SAlex Deucher };
47597b2e202SAlex Deucher
476021830d2SBas Nieuwenhuizen int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
477021830d2SBas Nieuwenhuizen
47897b2e202SAlex Deucher /*
47997b2e202SAlex Deucher * Writeback
48097b2e202SAlex Deucher */
481541372bbSLe Ma #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
48297b2e202SAlex Deucher
48397b2e202SAlex Deucher struct amdgpu_wb {
48497b2e202SAlex Deucher struct amdgpu_bo *wb_obj;
48597b2e202SAlex Deucher volatile uint32_t *wb;
48697b2e202SAlex Deucher uint64_t gpu_addr;
48797b2e202SAlex Deucher u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
48897b2e202SAlex Deucher unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
48997b2e202SAlex Deucher };
49097b2e202SAlex Deucher
491131b4b36SAlex Deucher int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
492131b4b36SAlex Deucher void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
49397b2e202SAlex Deucher
49497b2e202SAlex Deucher /*
49597b2e202SAlex Deucher * Benchmarking
49697b2e202SAlex Deucher */
497e460f244SAlex Deucher int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
49897b2e202SAlex Deucher
49997b2e202SAlex Deucher /*
50097b2e202SAlex Deucher * ASIC specific register table accessible by UMD
50197b2e202SAlex Deucher */
50297b2e202SAlex Deucher struct amdgpu_allowed_register_entry {
50397b2e202SAlex Deucher uint32_t reg_offset;
50497b2e202SAlex Deucher bool grbm_indexed;
50597b2e202SAlex Deucher };
50697b2e202SAlex Deucher
5070cf3c64fSAlex Deucher enum amd_reset_method {
508e071dce3SLijo Lazar AMD_RESET_METHOD_NONE = -1,
5090cf3c64fSAlex Deucher AMD_RESET_METHOD_LEGACY = 0,
5100cf3c64fSAlex Deucher AMD_RESET_METHOD_MODE0,
5110cf3c64fSAlex Deucher AMD_RESET_METHOD_MODE1,
5120cf3c64fSAlex Deucher AMD_RESET_METHOD_MODE2,
513af484df8SAlex Deucher AMD_RESET_METHOD_BACO,
514af484df8SAlex Deucher AMD_RESET_METHOD_PCI,
5150cf3c64fSAlex Deucher };
5160cf3c64fSAlex Deucher
5179269bf18SAlex Deucher struct amdgpu_video_codec_info {
5189269bf18SAlex Deucher u32 codec_type;
5199269bf18SAlex Deucher u32 max_width;
5209269bf18SAlex Deucher u32 max_height;
5219269bf18SAlex Deucher u32 max_pixels_per_frame;
5229269bf18SAlex Deucher u32 max_level;
5239269bf18SAlex Deucher };
5249269bf18SAlex Deucher
5259075096bSVeerabadhran Gopalakrishnan #define codec_info_build(type, width, height, level) \
5269075096bSVeerabadhran Gopalakrishnan .codec_type = type,\
5279075096bSVeerabadhran Gopalakrishnan .max_width = width,\
5289075096bSVeerabadhran Gopalakrishnan .max_height = height,\
5299075096bSVeerabadhran Gopalakrishnan .max_pixels_per_frame = height * width,\
5309075096bSVeerabadhran Gopalakrishnan .max_level = level,
5319075096bSVeerabadhran Gopalakrishnan
5329269bf18SAlex Deucher struct amdgpu_video_codecs {
5339269bf18SAlex Deucher const u32 codec_count;
5349269bf18SAlex Deucher const struct amdgpu_video_codec_info *codec_array;
5359269bf18SAlex Deucher };
5369269bf18SAlex Deucher
53797b2e202SAlex Deucher /*
53897b2e202SAlex Deucher * ASIC specific functions.
53997b2e202SAlex Deucher */
54097b2e202SAlex Deucher struct amdgpu_asic_funcs {
54197b2e202SAlex Deucher bool (*read_disabled_bios)(struct amdgpu_device *adev);
5427946b878SAlex Deucher bool (*read_bios_from_rom)(struct amdgpu_device *adev,
5437946b878SAlex Deucher u8 *bios, u32 length_bytes);
54497b2e202SAlex Deucher int (*read_register)(struct amdgpu_device *adev, u32 se_num,
54597b2e202SAlex Deucher u32 sh_num, u32 reg_offset, u32 *value);
54697b2e202SAlex Deucher void (*set_vga_state)(struct amdgpu_device *adev, bool state);
54797b2e202SAlex Deucher int (*reset)(struct amdgpu_device *adev);
5480cf3c64fSAlex Deucher enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
54997b2e202SAlex Deucher /* get the reference clock */
55097b2e202SAlex Deucher u32 (*get_xclk)(struct amdgpu_device *adev);
55197b2e202SAlex Deucher /* MM block clocks */
55297b2e202SAlex Deucher int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
55397b2e202SAlex Deucher int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
554841686dfSMaruthi Bayyavarapu /* static power management */
555841686dfSMaruthi Bayyavarapu int (*get_pcie_lanes)(struct amdgpu_device *adev);
556841686dfSMaruthi Bayyavarapu void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
557bbf282d8SAlex Deucher /* get config memsize register */
558bbf282d8SAlex Deucher u32 (*get_config_memsize)(struct amdgpu_device *adev);
5592df1b8b6SAlex Deucher /* flush hdp write queue */
56069882565SChristian König void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
5612df1b8b6SAlex Deucher /* invalidate hdp read cache */
56269882565SChristian König void (*invalidate_hdp)(struct amdgpu_device *adev,
56369882565SChristian König struct amdgpu_ring *ring);
56469070690SAlex Deucher /* check if the asic needs a full reset of if soft reset will work */
56569070690SAlex Deucher bool (*need_full_reset)(struct amdgpu_device *adev);
5665253163aSOak Zeng /* initialize doorbell layout for specific asic*/
5675253163aSOak Zeng void (*init_doorbell_index)(struct amdgpu_device *adev);
568b45e18acSKent Russell /* PCIe bandwidth usage */
569b45e18acSKent Russell void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
570b45e18acSKent Russell uint64_t *count1);
57144401889SAlex Deucher /* do we need to reset the asic at init time (e.g., kexec) */
57244401889SAlex Deucher bool (*need_reset_on_init)(struct amdgpu_device *adev);
573dcea6e65SKent Russell /* PCIe replay counter */
574dcea6e65SKent Russell uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
57569d5436dSAlex Deucher /* device supports BACO */
57669d5436dSAlex Deucher bool (*supports_baco)(struct amdgpu_device *adev);
5779737a923SAlex Deucher /* pre asic_init quirks */
5789737a923SAlex Deucher void (*pre_asic_init)(struct amdgpu_device *adev);
579f2b75bc2SEvan Quan /* enter/exit umd stable pstate */
580f2b75bc2SEvan Quan int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
5819269bf18SAlex Deucher /* query video codecs */
5829269bf18SAlex Deucher int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
5839269bf18SAlex Deucher const struct amdgpu_video_codecs **codecs);
5842fa480d3SLe Ma /* encode "> 32bits" smn addressing */
5852fa480d3SLe Ma u64 (*encode_ext_smn_addressing)(int ext_id);
58697b2e202SAlex Deucher };
58797b2e202SAlex Deucher
58897b2e202SAlex Deucher /*
58997b2e202SAlex Deucher * IOCTL.
59097b2e202SAlex Deucher */
59197b2e202SAlex Deucher int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
59297b2e202SAlex Deucher struct drm_file *filp);
59397b2e202SAlex Deucher
59497b2e202SAlex Deucher int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
5957ca24cf2SMarek Olšák int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
5967ca24cf2SMarek Olšák struct drm_file *filp);
59797b2e202SAlex Deucher int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
598eef18a82SJunwei Zhang int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
599eef18a82SJunwei Zhang struct drm_file *filp);
60097b2e202SAlex Deucher
60197b2e202SAlex Deucher /* VRAM scratch page for HDP bug, default vram page */
6027ccfd79fSChristian König struct amdgpu_mem_scratch {
60397b2e202SAlex Deucher struct amdgpu_bo *robj;
60497b2e202SAlex Deucher volatile uint32_t *ptr;
60597b2e202SAlex Deucher u64 gpu_addr;
60697b2e202SAlex Deucher };
60797b2e202SAlex Deucher
60897b2e202SAlex Deucher /*
609d03846afSChunming Zhou * CGS
610d03846afSChunming Zhou */
611110e6f26SDave Airlie struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
612110e6f26SDave Airlie void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
613a8fe58ceSMaruthi Bayyavarapu
614a8fe58ceSMaruthi Bayyavarapu /*
61597b2e202SAlex Deucher * Core structure, functions and helpers.
61697b2e202SAlex Deucher */
61797b2e202SAlex Deucher typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
61897b2e202SAlex Deucher typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
61997b2e202SAlex Deucher
6200c552ed3SLe Ma typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t);
6210c552ed3SLe Ma typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t);
6220c552ed3SLe Ma
6234fa1c6a6STao Zhou typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
6244fa1c6a6STao Zhou typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
6254fa1c6a6STao Zhou
62697b2e202SAlex Deucher typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
62797b2e202SAlex Deucher typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
62897b2e202SAlex Deucher
62988807dc8SOak Zeng struct amdgpu_mmio_remap {
63088807dc8SOak Zeng u32 reg_offset;
63188807dc8SOak Zeng resource_size_t bus_addr;
63288807dc8SOak Zeng };
63388807dc8SOak Zeng
6344522824cSShaoyun Liu /* Define the HW IP blocks will be used in driver , add more if necessary */
6354522824cSShaoyun Liu enum amd_hw_ip_block_type {
6364522824cSShaoyun Liu GC_HWIP = 1,
6374522824cSShaoyun Liu HDP_HWIP,
6384522824cSShaoyun Liu SDMA0_HWIP,
6394522824cSShaoyun Liu SDMA1_HWIP,
640fa5d2e6fSLe Ma SDMA2_HWIP,
641fa5d2e6fSLe Ma SDMA3_HWIP,
642fa5d2e6fSLe Ma SDMA4_HWIP,
643fa5d2e6fSLe Ma SDMA5_HWIP,
644fa5d2e6fSLe Ma SDMA6_HWIP,
645fa5d2e6fSLe Ma SDMA7_HWIP,
6461b491330SLikun Gao LSDMA_HWIP,
6474522824cSShaoyun Liu MMHUB_HWIP,
6484522824cSShaoyun Liu ATHUB_HWIP,
6494522824cSShaoyun Liu NBIO_HWIP,
6504522824cSShaoyun Liu MP0_HWIP,
651e6636ae1SEvan Quan MP1_HWIP,
6524522824cSShaoyun Liu UVD_HWIP,
6534522824cSShaoyun Liu VCN_HWIP = UVD_HWIP,
65488a1c40aSLeo Liu JPEG_HWIP = VCN_HWIP,
6555eceb201SAlex Deucher VCN1_HWIP,
6564522824cSShaoyun Liu VCE_HWIP,
6574522824cSShaoyun Liu DF_HWIP,
6584522824cSShaoyun Liu DCE_HWIP,
6594522824cSShaoyun Liu OSSSYS_HWIP,
6604522824cSShaoyun Liu SMUIO_HWIP,
6614522824cSShaoyun Liu PWR_HWIP,
6624522824cSShaoyun Liu NBIF_HWIP,
663e6636ae1SEvan Quan THM_HWIP,
66473b19174SRex Zhu CLK_HWIP,
6656501a771SHawking Zhang UMC_HWIP,
6666501a771SHawking Zhang RSMU_HWIP,
6671534db55SAlex Deucher XGMI_HWIP,
6685f931489SAlex Deucher DCI_HWIP,
66962f8f5c3SEvan Quan PCIE_HWIP,
6704522824cSShaoyun Liu MAX_HWIP
6714522824cSShaoyun Liu };
6724522824cSShaoyun Liu
6737e0eebdcSLe Ma #define HWIP_MAX_INSTANCE 44
6744522824cSShaoyun Liu
6755f52e9a7SAlex Deucher #define HW_ID_MAX 300
6765f52e9a7SAlex Deucher #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))
6771d5eee7dSLikun Gao #define IP_VERSION_MAJ(ver) ((ver) >> 16)
6781d5eee7dSLikun Gao #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF)
6791d5eee7dSLikun Gao #define IP_VERSION_REV(ver) ((ver) & 0xFF)
6805f52e9a7SAlex Deucher
6815d30cbb4SLijo Lazar struct amdgpu_ip_map_info {
682af2ba368STao Zhou /* Map of logical to actual dev instances/mask */
6835d30cbb4SLijo Lazar uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE];
6845d30cbb4SLijo Lazar int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev,
6855d30cbb4SLijo Lazar enum amd_hw_ip_block_type block,
6865d30cbb4SLijo Lazar int8_t inst);
687af2ba368STao Zhou uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,
688af2ba368STao Zhou enum amd_hw_ip_block_type block,
689af2ba368STao Zhou uint32_t mask);
6905d30cbb4SLijo Lazar };
6915d30cbb4SLijo Lazar
69211dc9364SRex Zhu struct amd_powerplay {
69311dc9364SRex Zhu void *pp_handle;
69411dc9364SRex Zhu const struct amd_pm_funcs *pp_funcs;
69511dc9364SRex Zhu };
69611dc9364SRex Zhu
697a6c40b17SLuben Tuikov struct ip_discovery_top;
698a6c40b17SLuben Tuikov
69973275181SEvan Quan /* polaris10 kickers */
70073275181SEvan Quan #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
70173275181SEvan Quan ((rid == 0xE3) || \
70273275181SEvan Quan (rid == 0xE4) || \
70373275181SEvan Quan (rid == 0xE5) || \
70473275181SEvan Quan (rid == 0xE7) || \
70573275181SEvan Quan (rid == 0xEF))) || \
70673275181SEvan Quan ((did == 0x6FDF) && \
70773275181SEvan Quan ((rid == 0xE7) || \
70873275181SEvan Quan (rid == 0xEF) || \
70973275181SEvan Quan (rid == 0xFF))))
71073275181SEvan Quan
71173275181SEvan Quan #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
71273275181SEvan Quan ((rid == 0xE1) || \
71373275181SEvan Quan (rid == 0xF7)))
71473275181SEvan Quan
71573275181SEvan Quan /* polaris11 kickers */
71673275181SEvan Quan #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
71773275181SEvan Quan ((rid == 0xE0) || \
71873275181SEvan Quan (rid == 0xE5))) || \
71973275181SEvan Quan ((did == 0x67FF) && \
72073275181SEvan Quan ((rid == 0xCF) || \
72173275181SEvan Quan (rid == 0xEF) || \
72273275181SEvan Quan (rid == 0xFF))))
72373275181SEvan Quan
72473275181SEvan Quan #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
72573275181SEvan Quan ((rid == 0xE2)))
72673275181SEvan Quan
72773275181SEvan Quan /* polaris12 kickers */
72873275181SEvan Quan #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
72973275181SEvan Quan ((rid == 0xC0) || \
73073275181SEvan Quan (rid == 0xC1) || \
73173275181SEvan Quan (rid == 0xC3) || \
73273275181SEvan Quan (rid == 0xC7))) || \
73373275181SEvan Quan ((did == 0x6981) && \
73473275181SEvan Quan ((rid == 0x00) || \
73573275181SEvan Quan (rid == 0x01) || \
73673275181SEvan Quan (rid == 0x10))))
73773275181SEvan Quan
7385405a526SJack Xiao struct amdgpu_mqd_prop {
7395405a526SJack Xiao uint64_t mqd_gpu_addr;
7405405a526SJack Xiao uint64_t hqd_base_gpu_addr;
7415405a526SJack Xiao uint64_t rptr_gpu_addr;
7425405a526SJack Xiao uint64_t wptr_gpu_addr;
7435405a526SJack Xiao uint32_t queue_size;
7445405a526SJack Xiao bool use_doorbell;
7455405a526SJack Xiao uint32_t doorbell_index;
7465405a526SJack Xiao uint64_t eop_gpu_addr;
7475405a526SJack Xiao uint32_t hqd_pipe_priority;
7485405a526SJack Xiao uint32_t hqd_queue_priority;
7495405a526SJack Xiao bool hqd_active;
7505405a526SJack Xiao };
7515405a526SJack Xiao
7525405a526SJack Xiao struct amdgpu_mqd {
7535405a526SJack Xiao unsigned mqd_size;
7545405a526SJack Xiao int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
7555405a526SJack Xiao struct amdgpu_mqd_prop *p);
7565405a526SJack Xiao };
7575405a526SJack Xiao
7580c49e0b8SChunming Zhou #define AMDGPU_RESET_MAGIC_NUM 64
759e4cf4bf5SJonathan Kim #define AMDGPU_MAX_DF_PERFMONS 4
7606c92fe5fSKent Russell #define AMDGPU_PRODUCT_NAME_LEN 64
761cfbb6b00SAndrey Grodzovsky struct amdgpu_reset_domain;
762a4c63cafSAndrey Grodzovsky
76358ab2c08SChristian König /*
76458ab2c08SChristian König * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
76558ab2c08SChristian König */
76658ab2c08SChristian König #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
76758ab2c08SChristian König
76897b2e202SAlex Deucher struct amdgpu_device {
76997b2e202SAlex Deucher struct device *dev;
77097b2e202SAlex Deucher struct pci_dev *pdev;
7718aba21b7SLuben Tuikov struct drm_device ddev;
77297b2e202SAlex Deucher
773a8fe58ceSMaruthi Bayyavarapu #ifdef CONFIG_DRM_AMD_ACP
774a8fe58ceSMaruthi Bayyavarapu struct amdgpu_acp acp;
775a8fe58ceSMaruthi Bayyavarapu #endif
776d95e8e97SDennis Li struct amdgpu_hive_info *hive;
77775d16923SLijo Lazar struct amdgpu_xcp_mgr *xcp_mgr;
77897b2e202SAlex Deucher /* ASIC */
7792f7d10b3SJammy Zhou enum amd_asic_type asic_type;
78097b2e202SAlex Deucher uint32_t family;
78197b2e202SAlex Deucher uint32_t rev_id;
78297b2e202SAlex Deucher uint32_t external_rev_id;
78397b2e202SAlex Deucher unsigned long flags;
78454f78a76SAlex Deucher unsigned long apu_flags;
78597b2e202SAlex Deucher int usec_timeout;
78697b2e202SAlex Deucher const struct amdgpu_asic_funcs *asic_funcs;
78797b2e202SAlex Deucher bool shutdown;
788fd5fd480SChunming Zhou bool need_swiotlb;
78997b2e202SAlex Deucher bool accel_working;
79097b2e202SAlex Deucher struct notifier_block acpi_nb;
79197b2e202SAlex Deucher struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
79298d28ac2SNirmoy Das struct debugfs_blob_wrapper debugfs_vbios_blob;
79381d1bf01SAlex Deucher struct debugfs_blob_wrapper debugfs_discovery_blob;
79497b2e202SAlex Deucher struct mutex srbm_mutex;
79597b2e202SAlex Deucher /* GRBM index mutex. Protects concurrent access to GRBM index */
79697b2e202SAlex Deucher struct mutex grbm_idx_mutex;
79797b2e202SAlex Deucher struct dev_pm_domain vga_pm_domain;
79897b2e202SAlex Deucher bool have_disp_power_ref;
799bae17d2aSJack Xiao bool have_atomics_support;
80097b2e202SAlex Deucher
80197b2e202SAlex Deucher /* BIOS */
8020cdd5005SAlex Deucher bool is_atom_fw;
80397b2e202SAlex Deucher uint8_t *bios;
804a9f5db9cSEvan Quan uint32_t bios_size;
805a5bde2f9SAlex Deucher uint32_t bios_scratch_reg_offset;
80697b2e202SAlex Deucher uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
80797b2e202SAlex Deucher
80897b2e202SAlex Deucher /* Register/doorbell mmio */
80997b2e202SAlex Deucher resource_size_t rmmio_base;
81097b2e202SAlex Deucher resource_size_t rmmio_size;
81197b2e202SAlex Deucher void __iomem *rmmio;
81297b2e202SAlex Deucher /* protects concurrent MM_INDEX/DATA based register access */
81397b2e202SAlex Deucher spinlock_t mmio_idx_lock;
81488807dc8SOak Zeng struct amdgpu_mmio_remap rmmio_remap;
81597b2e202SAlex Deucher /* protects concurrent SMC based register access */
81697b2e202SAlex Deucher spinlock_t smc_idx_lock;
81797b2e202SAlex Deucher amdgpu_rreg_t smc_rreg;
81897b2e202SAlex Deucher amdgpu_wreg_t smc_wreg;
81997b2e202SAlex Deucher /* protects concurrent PCIE register access */
82097b2e202SAlex Deucher spinlock_t pcie_idx_lock;
82197b2e202SAlex Deucher amdgpu_rreg_t pcie_rreg;
82297b2e202SAlex Deucher amdgpu_wreg_t pcie_wreg;
82336b9a952SHuang Rui amdgpu_rreg_t pciep_rreg;
82436b9a952SHuang Rui amdgpu_wreg_t pciep_wreg;
8250c552ed3SLe Ma amdgpu_rreg_ext_t pcie_rreg_ext;
8260c552ed3SLe Ma amdgpu_wreg_ext_t pcie_wreg_ext;
8274fa1c6a6STao Zhou amdgpu_rreg64_t pcie_rreg64;
8284fa1c6a6STao Zhou amdgpu_wreg64_t pcie_wreg64;
82997b2e202SAlex Deucher /* protects concurrent UVD register access */
83097b2e202SAlex Deucher spinlock_t uvd_ctx_idx_lock;
83197b2e202SAlex Deucher amdgpu_rreg_t uvd_ctx_rreg;
83297b2e202SAlex Deucher amdgpu_wreg_t uvd_ctx_wreg;
83397b2e202SAlex Deucher /* protects concurrent DIDT register access */
83497b2e202SAlex Deucher spinlock_t didt_idx_lock;
83597b2e202SAlex Deucher amdgpu_rreg_t didt_rreg;
83697b2e202SAlex Deucher amdgpu_wreg_t didt_wreg;
837ccdbb20aSRex Zhu /* protects concurrent gc_cac register access */
838ccdbb20aSRex Zhu spinlock_t gc_cac_idx_lock;
839ccdbb20aSRex Zhu amdgpu_rreg_t gc_cac_rreg;
840ccdbb20aSRex Zhu amdgpu_wreg_t gc_cac_wreg;
84116abb5d2SEvan Quan /* protects concurrent se_cac register access */
84216abb5d2SEvan Quan spinlock_t se_cac_idx_lock;
84316abb5d2SEvan Quan amdgpu_rreg_t se_cac_rreg;
84416abb5d2SEvan Quan amdgpu_wreg_t se_cac_wreg;
84597b2e202SAlex Deucher /* protects concurrent ENDPOINT (audio) register access */
84697b2e202SAlex Deucher spinlock_t audio_endpt_idx_lock;
84797b2e202SAlex Deucher amdgpu_block_rreg_t audio_endpt_rreg;
84897b2e202SAlex Deucher amdgpu_block_wreg_t audio_endpt_wreg;
84997b2e202SAlex Deucher struct amdgpu_doorbell doorbell;
85097b2e202SAlex Deucher
85197b2e202SAlex Deucher /* clock/pll info */
85297b2e202SAlex Deucher struct amdgpu_clock clock;
85397b2e202SAlex Deucher
85497b2e202SAlex Deucher /* MC */
855770d13b1SChristian König struct amdgpu_gmc gmc;
85697b2e202SAlex Deucher struct amdgpu_gart gart;
85792e71b06SChristian König dma_addr_t dummy_page_addr;
85897b2e202SAlex Deucher struct amdgpu_vm_manager vm_manager;
859e60f8db5SAlex Xie struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
860d9426c3dSLe Ma DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
86197b2e202SAlex Deucher
86297b2e202SAlex Deucher /* memory management */
86397b2e202SAlex Deucher struct amdgpu_mman mman;
8647ccfd79fSChristian König struct amdgpu_mem_scratch mem_scratch;
86597b2e202SAlex Deucher struct amdgpu_wb wb;
86697b2e202SAlex Deucher atomic64_t num_bytes_moved;
867dbd5ed60SChristian König atomic64_t num_evictions;
86868e2c5ffSMarek Olšák atomic64_t num_vram_cpu_page_faults;
869d94aed5aSMarek Olšák atomic_t gpu_reset_counter;
870f1892138SChunming Zhou atomic_t vram_lost_counter;
87197b2e202SAlex Deucher
87295844d20SMarek Olšák /* data for buffer migration throttling */
87395844d20SMarek Olšák struct {
87495844d20SMarek Olšák spinlock_t lock;
87595844d20SMarek Olšák s64 last_update_us;
87695844d20SMarek Olšák s64 accum_us; /* accumulated microseconds */
87700f06b24SJohn Brooks s64 accum_us_vis; /* for visible VRAM */
87895844d20SMarek Olšák u32 log2_max_MBps;
87995844d20SMarek Olšák } mm_stats;
88095844d20SMarek Olšák
88197b2e202SAlex Deucher /* display */
8829accf2fdSEmily Deng bool enable_virtual_display;
88384ec374bSRyan Taylor struct amdgpu_vkms_output *amdgpu_vkms_output;
88497b2e202SAlex Deucher struct amdgpu_mode_info mode_info;
8854562236bSHarry Wentland /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
88690f56611Sxurui struct delayed_work hotplug_work;
88797b2e202SAlex Deucher struct amdgpu_irq_src crtc_irq;
88811f1a553SWayne Lin struct amdgpu_irq_src vline0_irq;
889d2574c33SMario Kleiner struct amdgpu_irq_src vupdate_irq;
89097b2e202SAlex Deucher struct amdgpu_irq_src pageflip_irq;
89197b2e202SAlex Deucher struct amdgpu_irq_src hpd_irq;
892c79fe9b4SLeo (Hanghong) Ma struct amdgpu_irq_src dmub_trace_irq;
893f066af88SJude Shih struct amdgpu_irq_src dmub_outbox_irq;
89497b2e202SAlex Deucher
89597b2e202SAlex Deucher /* rings */
89676bf0db5SChristian König u64 fence_context;
89797b2e202SAlex Deucher unsigned num_rings;
89897b2e202SAlex Deucher struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
89968ce8b24SChristian König struct dma_fence __rcu *gang_submit;
90097b2e202SAlex Deucher bool ib_pool_ready;
9019ecefb19SChristian König struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
9021c6d567bSNirmoy Das struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
90397b2e202SAlex Deucher
90497b2e202SAlex Deucher /* interrupts */
90597b2e202SAlex Deucher struct amdgpu_irq irq;
90697b2e202SAlex Deucher
9071f7371b2SAlex Deucher /* powerplay */
9081f7371b2SAlex Deucher struct amd_powerplay powerplay;
90997b2e202SAlex Deucher struct amdgpu_pm pm;
91025faeddcSEvan Quan u64 cg_flags;
91197b2e202SAlex Deucher u32 pg_flags;
91297b2e202SAlex Deucher
913bebc0762SHawking Zhang /* nbio */
914bebc0762SHawking Zhang struct amdgpu_nbio nbio;
915bebc0762SHawking Zhang
916b291a387SHawking Zhang /* hdp */
917b291a387SHawking Zhang struct amdgpu_hdp hdp;
918b291a387SHawking Zhang
919293f2563SHawking Zhang /* smuio */
920293f2563SHawking Zhang struct amdgpu_smuio smuio;
921293f2563SHawking Zhang
922d3a5a121STao Zhou /* mmhub */
923d3a5a121STao Zhou struct amdgpu_mmhub mmhub;
924d3a5a121STao Zhou
9258ffff9b4SOak Zeng /* gfxhub */
9268ffff9b4SOak Zeng struct amdgpu_gfxhub gfxhub;
9278ffff9b4SOak Zeng
92897b2e202SAlex Deucher /* gfx */
92997b2e202SAlex Deucher struct amdgpu_gfx gfx;
93097b2e202SAlex Deucher
93197b2e202SAlex Deucher /* sdma */
932c113ea1cSAlex Deucher struct amdgpu_sdma sdma;
93397b2e202SAlex Deucher
9341b491330SLikun Gao /* lsdma */
9351b491330SLikun Gao struct amdgpu_lsdma lsdma;
9361b491330SLikun Gao
93797b2e202SAlex Deucher /* uvd */
93897b2e202SAlex Deucher struct amdgpu_uvd uvd;
93997b2e202SAlex Deucher
94097b2e202SAlex Deucher /* vce */
94197b2e202SAlex Deucher struct amdgpu_vce vce;
94295d0906fSLeo Liu
94395d0906fSLeo Liu /* vcn */
94495d0906fSLeo Liu struct amdgpu_vcn vcn;
94597b2e202SAlex Deucher
94688a1c40aSLeo Liu /* jpeg */
94788a1c40aSLeo Liu struct amdgpu_jpeg jpeg;
94888a1c40aSLeo Liu
94997b2e202SAlex Deucher /* firmwares */
95097b2e202SAlex Deucher struct amdgpu_firmware firmware;
95197b2e202SAlex Deucher
9520e5ca0d1SHuang Rui /* PSP */
9530e5ca0d1SHuang Rui struct psp_context psp;
9540e5ca0d1SHuang Rui
95597b2e202SAlex Deucher /* GDS */
95697b2e202SAlex Deucher struct amdgpu_gds gds;
95797b2e202SAlex Deucher
958611736d8SFelix Kuehling /* KFD */
959611736d8SFelix Kuehling struct amdgpu_kfd_dev kfd;
960611736d8SFelix Kuehling
961045c0216STao Zhou /* UMC */
962045c0216STao Zhou struct amdgpu_umc umc;
963045c0216STao Zhou
9644562236bSHarry Wentland /* display related functionality */
9654562236bSHarry Wentland struct amdgpu_display_manager dm;
9664562236bSHarry Wentland
967a538bbe7SJack Xiao /* mes */
968a538bbe7SJack Xiao bool enable_mes;
969928fe236SJack Xiao bool enable_mes_kiq;
970a538bbe7SJack Xiao struct amdgpu_mes mes;
9715405a526SJack Xiao struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
972a538bbe7SJack Xiao
973bdf84a80SJoseph Greathouse /* df */
974bdf84a80SJoseph Greathouse struct amdgpu_df df;
975bdf84a80SJoseph Greathouse
9763907c492SJohn Clements /* MCA */
9773907c492SJohn Clements struct amdgpu_mca mca;
9783907c492SJohn Clements
979a1255107SAlex Deucher struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
98083a0b863SLikun GAO uint32_t harvest_ip_mask;
98197b2e202SAlex Deucher int num_ip_blocks;
98297b2e202SAlex Deucher struct mutex mn_lock;
98397b2e202SAlex Deucher DECLARE_HASHTABLE(mn_hash, 7);
98497b2e202SAlex Deucher
98597b2e202SAlex Deucher /* tracking pinned memory */
986a5ccfe5cSMichel Dänzer atomic64_t vram_pin_size;
987a5ccfe5cSMichel Dänzer atomic64_t visible_pin_size;
988a5ccfe5cSMichel Dänzer atomic64_t gart_pin_size;
989130e0371SOded Gabbay
9904522824cSShaoyun Liu /* soc15 register offset based on ip, instance and segment */
9914522824cSShaoyun Liu uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
9925d30cbb4SLijo Lazar struct amdgpu_ip_map_info ip_map;
9934522824cSShaoyun Liu
9942dc80b00SShirish S /* delayed work_func for deferring clockgating during resume */
995beff74bcSAlex Deucher struct delayed_work delayed_init_work;
9962dc80b00SShirish S
9975a5099cbSXiangliang Yu struct amdgpu_virt virt;
9980c4e7fa5SChunming Zhou
9990c4e7fa5SChunming Zhou /* link all shadow bo */
10000c4e7fa5SChunming Zhou struct list_head shadow_list;
10010c4e7fa5SChunming Zhou struct mutex shadow_list_lock;
10025c1354bdSChunming Zhou
1003c836fec5SJim Qu /* record hw reset is performed */
1004c836fec5SJim Qu bool has_hw_reset;
10050c49e0b8SChunming Zhou u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1006c836fec5SJim Qu
100744779b43SRex Zhu /* s3/s4 mask */
100844779b43SRex Zhu bool in_suspend;
100962498733SAlex Deucher bool in_s3;
101062498733SAlex Deucher bool in_s4;
101162498733SAlex Deucher bool in_s0ix;
10127a3a0b0cSPrike Liang /* indicate amdgpu suspension status */
10137a3a0b0cSPrike Liang bool suspend_complete;
1014b092b196SPrike Liang
1015a3a09142SAlex Deucher enum pp_mp1_state mp1_state;
1016409c5191SOak Zeng struct amdgpu_doorbell_index doorbell_index;
1017d4535e2cSAndrey Grodzovsky
101862914a99SJason Gunthorpe struct mutex notifier_lock;
101962914a99SJason Gunthorpe
102026bc5340SAndrey Grodzovsky int asic_reset_res;
1021d4535e2cSAndrey Grodzovsky struct work_struct xgmi_reset_work;
1022655ce9cbSshaoyunl struct list_head reset_list;
10239b638f97Sshaoyunl
1024912dfc84SEvan Quan long gfx_timeout;
1025912dfc84SEvan Quan long sdma_timeout;
1026912dfc84SEvan Quan long video_timeout;
1027912dfc84SEvan Quan long compute_timeout;
1028fb2dbfd2SKent Russell
1029fb2dbfd2SKent Russell uint64_t unique_id;
1030e4cf4bf5SJonathan Kim uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
10315c5b2ba0SEvan Quan
10326ae6c7d4SAlex Deucher /* enable runtime pm on the device */
1033f0f7ddfcSAlex Deucher bool in_runpm;
1034b10c1c5bSAlex Deucher bool has_pr3;
10357c868b59SYintian Tao
10367c868b59SYintian Tao bool ucode_sysfs_en;
1037bd607166SKent Russell
1038bd607166SKent Russell /* Chip product information */
10391f83db6bSRoy Sun char product_number[20];
10406c92fe5fSKent Russell char product_name[AMDGPU_PRODUCT_NAME_LEN];
10418df1a28fSDan Carpenter char serial[20];
1042728e7e0cSJiange Zhao
1043b265bdbdSEvan Quan atomic_t throttling_logging_enabled;
1044b265bdbdSEvan Quan struct ratelimit_state throttling_logging_rs;
10458ab0d6f0SLuben Tuikov uint32_t ras_hw_enabled;
10468ab0d6f0SLuben Tuikov uint32_t ras_enabled;
1047c1dd4aa6SAndrey Grodzovsky
10487afefb81SAndrey Grodzovsky bool no_hw_access;
1049c1dd4aa6SAndrey Grodzovsky struct pci_saved_state *pci_state;
1050e17e27f9SGuchun Chen pci_channel_state_t pci_channel_state;
105104442bf7SLijo Lazar
105201f64820SJonathan Kim /* Track auto wait count on s_barrier settings */
105301f64820SJonathan Kim bool barrier_has_auto_waitcnt;
105401f64820SJonathan Kim
1055e071dce3SLijo Lazar struct amdgpu_reset_control *reset_cntl;
1056fe9c5c9aSLijo Lazar uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
10574a74c38cSPhilip Yang
10584a74c38cSPhilip Yang bool ram_is_direct_mapped;
10596492e1b0Syipechai
10606492e1b0Syipechai struct list_head ras_list;
1061a6c40b17SLuben Tuikov
1062a6c40b17SLuben Tuikov struct ip_discovery_top *ip_top;
106354f43c17SDave Airlie
1064cfbb6b00SAndrey Grodzovsky struct amdgpu_reset_domain *reset_domain;
106538a15ad9SDave Airlie
1066f113cc32SAlex Deucher struct mutex benchmark_mutex;
10675ce5a584SSomalapuram Amaranath
10685ce5a584SSomalapuram Amaranath /* reset dump register */
10695ce5a584SSomalapuram Amaranath uint32_t *reset_dump_reg_list;
1070651d7ee6SSomalapuram Amaranath uint32_t *reset_dump_reg_value;
10715ce5a584SSomalapuram Amaranath int num_regs;
10723d8785f6SSomalapuram Amaranath #ifdef CONFIG_DEV_COREDUMP
10733d8785f6SSomalapuram Amaranath struct amdgpu_task_info reset_task_info;
10743d8785f6SSomalapuram Amaranath bool reset_vram_lost;
10753d8785f6SSomalapuram Amaranath struct timespec64 reset_time;
10763d8785f6SSomalapuram Amaranath #endif
10777f318f4eSLikun Gao
10787f318f4eSLikun Gao bool scpm_enabled;
10797f318f4eSLikun Gao uint32_t scpm_status;
10802f83658fSAndrey Grodzovsky
10812f83658fSAndrey Grodzovsky struct work_struct reset_work;
10825bd8d53fSVictor Zhao
1083194eb174SVictor Zhao bool job_hang;
1084d09ef243SAlex Deucher bool dc_enabled;
10857a1efad0SLijo Lazar /* Mask of active clusters */
10867a1efad0SLijo Lazar uint32_t aid_mask;
108797b2e202SAlex Deucher };
108897b2e202SAlex Deucher
drm_to_adev(struct drm_device * ddev)10891348969aSLuben Tuikov static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
10901348969aSLuben Tuikov {
10918aba21b7SLuben Tuikov return container_of(ddev, struct amdgpu_device, ddev);
10921348969aSLuben Tuikov }
10931348969aSLuben Tuikov
adev_to_drm(struct amdgpu_device * adev)10944a580877SLuben Tuikov static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
10954a580877SLuben Tuikov {
10968aba21b7SLuben Tuikov return &adev->ddev;
10974a580877SLuben Tuikov }
10984a580877SLuben Tuikov
amdgpu_ttm_adev(struct ttm_device * bdev)10998af8a109SChristian König static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1100a7d64de6SChristian König {
1101a7d64de6SChristian König return container_of(bdev, struct amdgpu_device, mman.bdev);
1102a7d64de6SChristian König }
1103a7d64de6SChristian König
110497b2e202SAlex Deucher int amdgpu_device_init(struct amdgpu_device *adev,
110597b2e202SAlex Deucher uint32_t flags);
110672c8c97bSAndrey Grodzovsky void amdgpu_device_fini_hw(struct amdgpu_device *adev);
110772c8c97bSAndrey Grodzovsky void amdgpu_device_fini_sw(struct amdgpu_device *adev);
110872c8c97bSAndrey Grodzovsky
110997b2e202SAlex Deucher int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
111097b2e202SAlex Deucher
1111048af66bSKevin Wang void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1112048af66bSKevin Wang void *buf, size_t size, bool write);
1113048af66bSKevin Wang size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1114048af66bSKevin Wang void *buf, size_t size, bool write);
1115048af66bSKevin Wang
1116e35e2b11STianci.Yin void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1117048af66bSKevin Wang void *buf, size_t size, bool write);
111881283feeSJames Zhu uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
111981283feeSJames Zhu uint32_t inst, uint32_t reg_addr, char reg_name[],
112081283feeSJames Zhu uint32_t expected_value, uint32_t mask);
1121f7ee1874SHawking Zhang uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1122f7ee1874SHawking Zhang uint32_t reg, uint32_t acc_flags);
11230c552ed3SLe Ma u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
11240c552ed3SLe Ma u64 reg_addr);
1125f7ee1874SHawking Zhang void amdgpu_device_wreg(struct amdgpu_device *adev,
1126f7ee1874SHawking Zhang uint32_t reg, uint32_t v,
112715d72fd7SMonk Liu uint32_t acc_flags);
11280c552ed3SLe Ma void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
11290c552ed3SLe Ma u64 reg_addr, u32 reg_data);
1130f7ee1874SHawking Zhang void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
11318ed49dd1SVictor Lu uint32_t reg, uint32_t v, uint32_t xcc_id);
1132421a2a30SMonk Liu void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1133421a2a30SMonk Liu uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1134421a2a30SMonk Liu
11351bba3683SHawking Zhang u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
11361bba3683SHawking Zhang u32 reg_addr);
11371bba3683SHawking Zhang u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
11381bba3683SHawking Zhang u32 reg_addr);
11391bba3683SHawking Zhang void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
11401bba3683SHawking Zhang u32 reg_addr, u32 reg_data);
11411bba3683SHawking Zhang void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
11421bba3683SHawking Zhang u32 reg_addr, u64 reg_data);
1143dabc114eSHawking Zhang u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);
11444562236bSHarry Wentland bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
11454562236bSHarry Wentland bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
11464562236bSHarry Wentland
114725263da3SAlex Deucher void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
114825263da3SAlex Deucher
1149e3c1b071Sshaoyunl int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
115004442bf7SLijo Lazar struct amdgpu_reset_context *reset_context);
1151e3c1b071Sshaoyunl
115204442bf7SLijo Lazar int amdgpu_do_asic_reset(struct list_head *device_list_handle,
115304442bf7SLijo Lazar struct amdgpu_reset_context *reset_context);
1154e3c1b071Sshaoyunl
11559475a943SShaoyun Liu int emu_soc_asic_init(struct amdgpu_device *adev);
11569475a943SShaoyun Liu
115797b2e202SAlex Deucher /*
115897b2e202SAlex Deucher * Registers read & write functions.
115997b2e202SAlex Deucher */
116015d72fd7SMonk Liu #define AMDGPU_REGS_NO_KIQ (1<<1)
1161a5504e9aSPeng Ju Zhou #define AMDGPU_REGS_RLC (1<<2)
116215d72fd7SMonk Liu
1163f7ee1874SHawking Zhang #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1164f7ee1874SHawking Zhang #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
116515d72fd7SMonk Liu
1166f384ff95SHawking Zhang #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1167f384ff95SHawking Zhang #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1168c68dbcd8Schen gong
1169421a2a30SMonk Liu #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1170421a2a30SMonk Liu #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1171421a2a30SMonk Liu
1172f7ee1874SHawking Zhang #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1173f7ee1874SHawking Zhang #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1174f7ee1874SHawking Zhang #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
117597b2e202SAlex Deucher #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
117697b2e202SAlex Deucher #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
117797b2e202SAlex Deucher #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
117897b2e202SAlex Deucher #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
117936b9a952SHuang Rui #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
118036b9a952SHuang Rui #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
11810c552ed3SLe Ma #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
11820c552ed3SLe Ma #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
11834fa1c6a6STao Zhou #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
11844fa1c6a6STao Zhou #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
118597b2e202SAlex Deucher #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
118697b2e202SAlex Deucher #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
118797b2e202SAlex Deucher #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
118897b2e202SAlex Deucher #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
118997b2e202SAlex Deucher #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
119097b2e202SAlex Deucher #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1191ccdbb20aSRex Zhu #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1192ccdbb20aSRex Zhu #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
119316abb5d2SEvan Quan #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
119416abb5d2SEvan Quan #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
119597b2e202SAlex Deucher #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
119697b2e202SAlex Deucher #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
119797b2e202SAlex Deucher #define WREG32_P(reg, val, mask) \
119897b2e202SAlex Deucher do { \
119997b2e202SAlex Deucher uint32_t tmp_ = RREG32(reg); \
120097b2e202SAlex Deucher tmp_ &= (mask); \
120197b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \
120297b2e202SAlex Deucher WREG32(reg, tmp_); \
120397b2e202SAlex Deucher } while (0)
120497b2e202SAlex Deucher #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
120597b2e202SAlex Deucher #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
120697b2e202SAlex Deucher #define WREG32_PLL_P(reg, val, mask) \
120797b2e202SAlex Deucher do { \
120897b2e202SAlex Deucher uint32_t tmp_ = RREG32_PLL(reg); \
120997b2e202SAlex Deucher tmp_ &= (mask); \
121097b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \
121197b2e202SAlex Deucher WREG32_PLL(reg, tmp_); \
121297b2e202SAlex Deucher } while (0)
1213fb40bcebSAlex Jivin
1214fb40bcebSAlex Jivin #define WREG32_SMC_P(_Reg, _Val, _Mask) \
1215fb40bcebSAlex Jivin do { \
1216fb40bcebSAlex Jivin u32 tmp = RREG32_SMC(_Reg); \
1217fb40bcebSAlex Jivin tmp &= (_Mask); \
1218fb40bcebSAlex Jivin tmp |= ((_Val) & ~(_Mask)); \
1219fb40bcebSAlex Jivin WREG32_SMC(_Reg, tmp); \
1220fb40bcebSAlex Jivin } while (0)
1221fb40bcebSAlex Jivin
1222f7ee1874SHawking Zhang #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
122397b2e202SAlex Deucher
122497b2e202SAlex Deucher #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
122597b2e202SAlex Deucher #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
122697b2e202SAlex Deucher
122797b2e202SAlex Deucher #define REG_SET_FIELD(orig_val, reg, field, field_val) \
122897b2e202SAlex Deucher (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
122997b2e202SAlex Deucher (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
123097b2e202SAlex Deucher
123197b2e202SAlex Deucher #define REG_GET_FIELD(value, reg, field) \
123297b2e202SAlex Deucher (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
123397b2e202SAlex Deucher
123461cb8cefSTom St Denis #define WREG32_FIELD(reg, field, val) \
123561cb8cefSTom St Denis WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
123661cb8cefSTom St Denis
1237ccaf3574STom St Denis #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1238ccaf3574STom St Denis WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1239ccaf3574STom St Denis
124097b2e202SAlex Deucher /*
124197b2e202SAlex Deucher * BIOS helpers.
124297b2e202SAlex Deucher */
124397b2e202SAlex Deucher #define RBIOS8(i) (adev->bios[i])
124497b2e202SAlex Deucher #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
124597b2e202SAlex Deucher #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
124697b2e202SAlex Deucher
124797b2e202SAlex Deucher /*
124897b2e202SAlex Deucher * ASICs macro.
124997b2e202SAlex Deucher */
1250b336c681SLikun Gao #define amdgpu_asic_set_vga_state(adev, state) \
1251b336c681SLikun Gao ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
125297b2e202SAlex Deucher #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
12530cf3c64fSAlex Deucher #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
125497b2e202SAlex Deucher #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
125597b2e202SAlex Deucher #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
125697b2e202SAlex Deucher #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1257841686dfSMaruthi Bayyavarapu #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1258841686dfSMaruthi Bayyavarapu #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1259841686dfSMaruthi Bayyavarapu #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
126097b2e202SAlex Deucher #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
12617946b878SAlex Deucher #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
126297b2e202SAlex Deucher #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1263bbf282d8SAlex Deucher #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1264455d40c9SLikun Gao #define amdgpu_asic_flush_hdp(adev, r) \
1265455d40c9SLikun Gao ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1266455d40c9SLikun Gao #define amdgpu_asic_invalidate_hdp(adev, r) \
1267563fcfbfSLikun Gao ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1268418431bcSLijo Lazar ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0))
126969070690SAlex Deucher #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
12705253163aSOak Zeng #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1271b45e18acSKent Russell #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
127244401889SAlex Deucher #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1273dcea6e65SKent Russell #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
127469d5436dSAlex Deucher #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
12759737a923SAlex Deucher #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1276f2b75bc2SEvan Quan #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1277f2b75bc2SEvan Quan ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
12789269bf18SAlex Deucher #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
127969d5436dSAlex Deucher
1280e3526257SMonk Liu #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
128197b2e202SAlex Deucher
1282b579ea63SLijo Lazar #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i))
1283dd1a02e2SLijo Lazar #define for_each_inst(i, inst_mask) \
1284b579ea63SLijo Lazar for (i = ffs(inst_mask); i-- != 0; \
1285b579ea63SLijo Lazar i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
1286dd1a02e2SLijo Lazar
12870d8318e1SEvan Quan #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
12880d8318e1SEvan Quan
128997b2e202SAlex Deucher /* Common functions */
12909a1cddd6Sjqdeng bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
129112938fadSChristian König bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
12925f152b5eSAlex Deucher int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1293f1549c09SLikun Gao struct amdgpu_job *job,
1294f1549c09SLikun Gao struct amdgpu_reset_context *reset_context);
12958111c387SAlex Deucher void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1296af484df8SAlex Deucher int amdgpu_device_pci_reset(struct amdgpu_device *adev);
129739c640c0SAlex Deucher bool amdgpu_device_need_post(struct amdgpu_device *adev);
129818862307SMario Limonciello bool amdgpu_device_pcie_dynamic_switching_supported(void);
12990ab5d711SMario Limonciello bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
13002b072442SKai-Heng Feng bool amdgpu_device_aspm_support_quirk(void);
1301d5fc5e82SChunming Zhou
130200f06b24SJohn Brooks void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
130300f06b24SJohn Brooks u64 num_vis_bytes);
1304d6895ad3SChristian König int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
13059c3f2b54SAlex Deucher void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
130697b2e202SAlex Deucher const u32 *registers,
130797b2e202SAlex Deucher const u32 array_size);
130897b2e202SAlex Deucher
13095c03e584SFeifei Xu int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1310b98c6299SAlex Deucher bool amdgpu_device_supports_atpx(struct drm_device *dev);
1311b98c6299SAlex Deucher bool amdgpu_device_supports_px(struct drm_device *dev);
131231af062aSAlex Deucher bool amdgpu_device_supports_boco(struct drm_device *dev);
13133fa8f89dSSathishkumar S bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1314a69cba42SAlex Deucher bool amdgpu_device_supports_baco(struct drm_device *dev);
1315992af942SJonathan Kim bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1316992af942SJonathan Kim struct amdgpu_device *peer_adev);
1317361dbd01SAlex Deucher int amdgpu_device_baco_enter(struct drm_device *dev);
1318361dbd01SAlex Deucher int amdgpu_device_baco_exit(struct drm_device *dev);
1319992af942SJonathan Kim
1320810085ddSEric Huang void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1321810085ddSEric Huang struct amdgpu_ring *ring);
1322810085ddSEric Huang void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1323810085ddSEric Huang struct amdgpu_ring *ring);
1324810085ddSEric Huang
132534f3a4a9SLang Yu void amdgpu_device_halt(struct amdgpu_device *adev);
132686700a40SXiaojian Du u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
132786700a40SXiaojian Du u32 reg);
132886700a40SXiaojian Du void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
132986700a40SXiaojian Du u32 reg, u32 v);
133068ce8b24SChristian König struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
133168ce8b24SChristian König struct dma_fence *gang);
1332220c8cc8SAlex Deucher bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
133334f3a4a9SLang Yu
133497b2e202SAlex Deucher /* atpx handler */
133597b2e202SAlex Deucher #if defined(CONFIG_VGA_SWITCHEROO)
133697b2e202SAlex Deucher void amdgpu_register_atpx_handler(void);
133797b2e202SAlex Deucher void amdgpu_unregister_atpx_handler(void);
1338a78fe133SAlex Deucher bool amdgpu_has_atpx_dgpu_power_cntl(void);
13392f5af82eSAlex Deucher bool amdgpu_is_atpx_hybrid(void);
1340efc83cf4SAlex Deucher bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1341714f88e0SAlex Xie bool amdgpu_has_atpx(void);
134297b2e202SAlex Deucher #else
amdgpu_register_atpx_handler(void)134397b2e202SAlex Deucher static inline void amdgpu_register_atpx_handler(void) {}
amdgpu_unregister_atpx_handler(void)134497b2e202SAlex Deucher static inline void amdgpu_unregister_atpx_handler(void) {}
amdgpu_has_atpx_dgpu_power_cntl(void)1345a78fe133SAlex Deucher static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
amdgpu_is_atpx_hybrid(void)13462f5af82eSAlex Deucher static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
amdgpu_atpx_dgpu_req_power_for_displays(void)1347efc83cf4SAlex Deucher static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
amdgpu_has_atpx(void)1348714f88e0SAlex Xie static inline bool amdgpu_has_atpx(void) { return false; }
134997b2e202SAlex Deucher #endif
135097b2e202SAlex Deucher
135124aeefcdSLyude Paul #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
135224aeefcdSLyude Paul void *amdgpu_atpx_get_dhandle(void);
135324aeefcdSLyude Paul #else
amdgpu_atpx_get_dhandle(void)135424aeefcdSLyude Paul static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
135524aeefcdSLyude Paul #endif
135624aeefcdSLyude Paul
135797b2e202SAlex Deucher /*
135897b2e202SAlex Deucher * KMS
135997b2e202SAlex Deucher */
136097b2e202SAlex Deucher extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1361f498d9edSNils Wallménius extern const int amdgpu_max_kms_ioctl;
136297b2e202SAlex Deucher
13638aba21b7SLuben Tuikov int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
136411b3c20bSGabriel Krisman Bertazi void amdgpu_driver_unload_kms(struct drm_device *dev);
136597b2e202SAlex Deucher void amdgpu_driver_lastclose_kms(struct drm_device *dev);
136697b2e202SAlex Deucher int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
136797b2e202SAlex Deucher void amdgpu_driver_postclose_kms(struct drm_device *dev,
136897b2e202SAlex Deucher struct drm_file *file_priv);
136972c8c97bSAndrey Grodzovsky void amdgpu_driver_release_kms(struct drm_device *dev);
137072c8c97bSAndrey Grodzovsky
1371cdd61df6SAlex Deucher int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1372*8b5f7204SMario Limonciello int amdgpu_device_prepare(struct drm_device *dev);
1373de185019SAlex Deucher int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1374de185019SAlex Deucher int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1375e3eff4b5SThomas Zimmermann u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1376e3eff4b5SThomas Zimmermann int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1377e3eff4b5SThomas Zimmermann void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1378b1246bd4SLuben Tuikov int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1379b1246bd4SLuben Tuikov struct drm_file *filp);
138097b2e202SAlex Deucher
138197b2e202SAlex Deucher /*
138297b2e202SAlex Deucher * functions used by amdgpu_encoder.c
138397b2e202SAlex Deucher */
138497b2e202SAlex Deucher struct amdgpu_afmt_acr {
138597b2e202SAlex Deucher u32 clock;
138697b2e202SAlex Deucher
138797b2e202SAlex Deucher int n_32khz;
138897b2e202SAlex Deucher int cts_32khz;
138997b2e202SAlex Deucher
139097b2e202SAlex Deucher int n_44_1khz;
139197b2e202SAlex Deucher int cts_44_1khz;
139297b2e202SAlex Deucher
139397b2e202SAlex Deucher int n_48khz;
139497b2e202SAlex Deucher int cts_48khz;
139597b2e202SAlex Deucher
139697b2e202SAlex Deucher };
139797b2e202SAlex Deucher
139897b2e202SAlex Deucher struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
139997b2e202SAlex Deucher
140097b2e202SAlex Deucher /* amdgpu_acpi.c */
14013fa8f89dSSathishkumar S
1402fa0497c3SLijo Lazar struct amdgpu_numa_info {
1403fa0497c3SLijo Lazar uint64_t size;
1404fa0497c3SLijo Lazar int pxm;
1405fa0497c3SLijo Lazar int nid;
1406fa0497c3SLijo Lazar };
1407fa0497c3SLijo Lazar
14083fa8f89dSSathishkumar S /* ATCS Device/Driver State */
14093fa8f89dSSathishkumar S #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
14103fa8f89dSSathishkumar S #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
14113fa8f89dSSathishkumar S #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
14123fa8f89dSSathishkumar S #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
14133fa8f89dSSathishkumar S
141497b2e202SAlex Deucher #if defined(CONFIG_ACPI)
141597b2e202SAlex Deucher int amdgpu_acpi_init(struct amdgpu_device *adev);
141697b2e202SAlex Deucher void amdgpu_acpi_fini(struct amdgpu_device *adev);
141797b2e202SAlex Deucher bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
141816eb48c6SSathishkumar S bool amdgpu_acpi_is_power_shift_control_supported(void);
141997b2e202SAlex Deucher int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
142097b2e202SAlex Deucher u8 perf_req, bool advertise);
142116eb48c6SSathishkumar S int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
142216eb48c6SSathishkumar S u8 dev_state, bool drv_state);
14233fa8f89dSSathishkumar S int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
142497b2e202SAlex Deucher int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
14256e018822SLijo Lazar int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
14266e018822SLijo Lazar u64 *tmr_size);
1427fa0497c3SLijo Lazar int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1428fa0497c3SLijo Lazar struct amdgpu_numa_info *numa_info);
1429206bbafeSDavid Francis
1430f9b7f370SAlex Deucher void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1431aaee0ce4STim Huang bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1432f9b7f370SAlex Deucher void amdgpu_acpi_detect(void);
14334d5275abSLijo Lazar void amdgpu_acpi_release(void);
143497b2e202SAlex Deucher #else
amdgpu_acpi_init(struct amdgpu_device * adev)143597b2e202SAlex Deucher static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
amdgpu_acpi_get_tmr_info(struct amdgpu_device * adev,u64 * tmr_offset,u64 * tmr_size)14366e018822SLijo Lazar static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
14376e018822SLijo Lazar u64 *tmr_offset, u64 *tmr_size)
14386e018822SLijo Lazar {
14396e018822SLijo Lazar return -EINVAL;
14406e018822SLijo Lazar }
amdgpu_acpi_get_mem_info(struct amdgpu_device * adev,int xcc_id,struct amdgpu_numa_info * numa_info)1441fa0497c3SLijo Lazar static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
1442fa0497c3SLijo Lazar int xcc_id,
1443fa0497c3SLijo Lazar struct amdgpu_numa_info *numa_info)
1444fa0497c3SLijo Lazar {
1445fa0497c3SLijo Lazar return -EINVAL;
1446fa0497c3SLijo Lazar }
amdgpu_acpi_fini(struct amdgpu_device * adev)144797b2e202SAlex Deucher static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
amdgpu_acpi_should_gpu_reset(struct amdgpu_device * adev)1448aaee0ce4STim Huang static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
amdgpu_acpi_detect(void)1449f9b7f370SAlex Deucher static inline void amdgpu_acpi_detect(void) { }
amdgpu_acpi_release(void)14504d5275abSLijo Lazar static inline void amdgpu_acpi_release(void) { }
amdgpu_acpi_is_power_shift_control_supported(void)145116eb48c6SSathishkumar S static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
amdgpu_acpi_power_shift_control(struct amdgpu_device * adev,u8 dev_state,bool drv_state)145216eb48c6SSathishkumar S static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
145316eb48c6SSathishkumar S u8 dev_state, bool drv_state) { return 0; }
amdgpu_acpi_smart_shift_update(struct drm_device * dev,enum amdgpu_ss ss_state)14543fa8f89dSSathishkumar S static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
14553fa8f89dSSathishkumar S enum amdgpu_ss ss_state) { return 0; }
145697b2e202SAlex Deucher #endif
145797b2e202SAlex Deucher
1458f588a1bbSMario Limonciello #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
145918b66aceSMario Limonciello bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1460f588a1bbSMario Limonciello bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1461f588a1bbSMario Limonciello #else
amdgpu_acpi_is_s0ix_active(struct amdgpu_device * adev)1462f588a1bbSMario Limonciello static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
amdgpu_acpi_is_s3_active(struct amdgpu_device * adev)146318b66aceSMario Limonciello static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1464f588a1bbSMario Limonciello #endif
1465f588a1bbSMario Limonciello
14664562236bSHarry Wentland #if defined(CONFIG_DRM_AMD_DC)
14674562236bSHarry Wentland int amdgpu_dm_display_resume(struct amdgpu_device *adev );
14684562236bSHarry Wentland #else
amdgpu_dm_display_resume(struct amdgpu_device * adev)14694562236bSHarry Wentland static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
14704562236bSHarry Wentland #endif
14714562236bSHarry Wentland
1472fdafb359SEvan Quan
1473fdafb359SEvan Quan void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1474fdafb359SEvan Quan void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1475fdafb359SEvan Quan
1476c9a6b82fSAndrey Grodzovsky pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1477c9a6b82fSAndrey Grodzovsky pci_channel_state_t state);
1478c9a6b82fSAndrey Grodzovsky pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1479c9a6b82fSAndrey Grodzovsky pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1480c9a6b82fSAndrey Grodzovsky void amdgpu_pci_resume(struct pci_dev *pdev);
1481c9a6b82fSAndrey Grodzovsky
1482c1dd4aa6SAndrey Grodzovsky bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1483c1dd4aa6SAndrey Grodzovsky bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1484c1dd4aa6SAndrey Grodzovsky
148556b53c0bSDennis Li bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
148656b53c0bSDennis Li
14875d89bb2dSLijo Lazar int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
14885d89bb2dSLijo Lazar enum amd_clockgating_state state);
14895d89bb2dSLijo Lazar int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
14905d89bb2dSLijo Lazar enum amd_powergating_state state);
14915d89bb2dSLijo Lazar
amdgpu_device_has_timeouts_enabled(struct amdgpu_device * adev)1492400ef298SJonathan Kim static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1493400ef298SJonathan Kim {
1494400ef298SJonathan Kim return amdgpu_gpu_recovery != 0 &&
1495400ef298SJonathan Kim adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1496400ef298SJonathan Kim adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1497400ef298SJonathan Kim adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1498400ef298SJonathan Kim adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1499400ef298SJonathan Kim }
1500400ef298SJonathan Kim
150197b2e202SAlex Deucher #include "amdgpu_object.h"
1502e4cf4bf5SJonathan Kim
amdgpu_is_tmz(struct amdgpu_device * adev)1503c6252390SLuben Tuikov static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1504c6252390SLuben Tuikov {
1505c6252390SLuben Tuikov return adev->gmc.tmz_enabled;
1506c6252390SLuben Tuikov }
1507e4cf4bf5SJonathan Kim
150889a7a870SAndrey Grodzovsky int amdgpu_in_reset(struct amdgpu_device *adev);
150989a7a870SAndrey Grodzovsky
1510f9acfafcSSrinivasan Shanmugam extern const struct attribute_group amdgpu_vram_mgr_attr_group;
1511f9acfafcSSrinivasan Shanmugam extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
1512f9acfafcSSrinivasan Shanmugam extern const struct attribute_group amdgpu_flash_attr_group;
1513f9acfafcSSrinivasan Shanmugam
1514c6252390SLuben Tuikov #endif
1515