1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "amdgpu_psp.h"
25 #include "amdgpu_ucode.h"
26 #include "soc15_common.h"
27 #include "psp_v13_0_4.h"
28
29 #include "mp/mp_13_0_4_offset.h"
30 #include "mp/mp_13_0_4_sh_mask.h"
31
32 MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin");
33 MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin");
34
psp_v13_0_4_init_microcode(struct psp_context * psp)35 static int psp_v13_0_4_init_microcode(struct psp_context *psp)
36 {
37 struct amdgpu_device *adev = psp->adev;
38 char ucode_prefix[30];
39 int err = 0;
40
41 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
42
43 switch (adev->ip_versions[MP0_HWIP][0]) {
44 case IP_VERSION(13, 0, 4):
45 err = psp_init_toc_microcode(psp, ucode_prefix);
46 if (err)
47 return err;
48 err = psp_init_ta_microcode(psp, ucode_prefix);
49 if (err)
50 return err;
51 break;
52 default:
53 BUG();
54 }
55
56 return 0;
57 }
58
psp_v13_0_4_is_sos_alive(struct psp_context * psp)59 static bool psp_v13_0_4_is_sos_alive(struct psp_context *psp)
60 {
61 struct amdgpu_device *adev = psp->adev;
62 uint32_t sol_reg;
63
64 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
65
66 return sol_reg != 0x0;
67 }
68
psp_v13_0_4_wait_for_bootloader(struct psp_context * psp)69 static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp)
70 {
71 struct amdgpu_device *adev = psp->adev;
72
73 int ret;
74 int retry_loop;
75
76 for (retry_loop = 0; retry_loop < 10; retry_loop++) {
77 /* Wait for bootloader to signify that is
78 ready having bit 31 of C2PMSG_35 set to 1 */
79 ret = psp_wait_for(psp,
80 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
81 0x80000000,
82 0x80000000,
83 false);
84
85 if (ret == 0)
86 return 0;
87 }
88
89 return ret;
90 }
91
psp_v13_0_4_bootloader_load_component(struct psp_context * psp,struct psp_bin_desc * bin_desc,enum psp_bootloader_cmd bl_cmd)92 static int psp_v13_0_4_bootloader_load_component(struct psp_context *psp,
93 struct psp_bin_desc *bin_desc,
94 enum psp_bootloader_cmd bl_cmd)
95 {
96 int ret;
97 uint32_t psp_gfxdrv_command_reg = 0;
98 struct amdgpu_device *adev = psp->adev;
99
100 /* Check tOS sign of life register to confirm sys driver and sOS
101 * are already been loaded.
102 */
103 if (psp_v13_0_4_is_sos_alive(psp))
104 return 0;
105
106 ret = psp_v13_0_4_wait_for_bootloader(psp);
107 if (ret)
108 return ret;
109
110 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
111
112 /* Copy PSP KDB binary to memory */
113 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
114
115 /* Provide the PSP KDB to bootloader */
116 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
117 (uint32_t)(psp->fw_pri_mc_addr >> 20));
118 psp_gfxdrv_command_reg = bl_cmd;
119 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
120 psp_gfxdrv_command_reg);
121
122 ret = psp_v13_0_4_wait_for_bootloader(psp);
123
124 return ret;
125 }
126
psp_v13_0_4_bootloader_load_kdb(struct psp_context * psp)127 static int psp_v13_0_4_bootloader_load_kdb(struct psp_context *psp)
128 {
129 return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
130 }
131
psp_v13_0_4_bootloader_load_spl(struct psp_context * psp)132 static int psp_v13_0_4_bootloader_load_spl(struct psp_context *psp)
133 {
134 return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
135 }
136
psp_v13_0_4_bootloader_load_sysdrv(struct psp_context * psp)137 static int psp_v13_0_4_bootloader_load_sysdrv(struct psp_context *psp)
138 {
139 return psp_v13_0_4_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
140 }
141
psp_v13_0_4_bootloader_load_soc_drv(struct psp_context * psp)142 static int psp_v13_0_4_bootloader_load_soc_drv(struct psp_context *psp)
143 {
144 return psp_v13_0_4_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
145 }
146
psp_v13_0_4_bootloader_load_intf_drv(struct psp_context * psp)147 static int psp_v13_0_4_bootloader_load_intf_drv(struct psp_context *psp)
148 {
149 return psp_v13_0_4_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
150 }
151
psp_v13_0_4_bootloader_load_dbg_drv(struct psp_context * psp)152 static int psp_v13_0_4_bootloader_load_dbg_drv(struct psp_context *psp)
153 {
154 return psp_v13_0_4_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
155 }
156
psp_v13_0_4_bootloader_load_sos(struct psp_context * psp)157 static int psp_v13_0_4_bootloader_load_sos(struct psp_context *psp)
158 {
159 int ret;
160 unsigned int psp_gfxdrv_command_reg = 0;
161 struct amdgpu_device *adev = psp->adev;
162
163 /* Check sOS sign of life register to confirm sys driver and sOS
164 * are already been loaded.
165 */
166 if (psp_v13_0_4_is_sos_alive(psp))
167 return 0;
168
169 ret = psp_v13_0_4_wait_for_bootloader(psp);
170 if (ret)
171 return ret;
172
173 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
174
175 /* Copy Secure OS binary to PSP memory */
176 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
177
178 /* Provide the PSP secure OS to bootloader */
179 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
180 (uint32_t)(psp->fw_pri_mc_addr >> 20));
181 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
182 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
183 psp_gfxdrv_command_reg);
184
185 /* there might be handshake issue with hardware which needs delay */
186 mdelay(20);
187 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
188 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
189 0, true);
190
191 return ret;
192 }
193
psp_v13_0_4_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)194 static int psp_v13_0_4_ring_stop(struct psp_context *psp,
195 enum psp_ring_type ring_type)
196 {
197 int ret = 0;
198 struct amdgpu_device *adev = psp->adev;
199
200 if (amdgpu_sriov_vf(adev)) {
201 /* Write the ring destroy command*/
202 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
203 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
204 /* there might be handshake issue with hardware which needs delay */
205 mdelay(20);
206 /* Wait for response flag (bit 31) */
207 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
208 0x80000000, 0x80000000, false);
209 } else {
210 /* Write the ring destroy command*/
211 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
212 GFX_CTRL_CMD_ID_DESTROY_RINGS);
213 /* there might be handshake issue with hardware which needs delay */
214 mdelay(20);
215 /* Wait for response flag (bit 31) */
216 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
217 0x80000000, 0x80000000, false);
218 }
219
220 return ret;
221 }
222
psp_v13_0_4_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)223 static int psp_v13_0_4_ring_create(struct psp_context *psp,
224 enum psp_ring_type ring_type)
225 {
226 int ret = 0;
227 unsigned int psp_ring_reg = 0;
228 struct psp_ring *ring = &psp->km_ring;
229 struct amdgpu_device *adev = psp->adev;
230
231 if (amdgpu_sriov_vf(adev)) {
232 ret = psp_v13_0_4_ring_stop(psp, ring_type);
233 if (ret) {
234 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
235 return ret;
236 }
237
238 /* Write low address of the ring to C2PMSG_102 */
239 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
240 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
241 /* Write high address of the ring to C2PMSG_103 */
242 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
243 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
244
245 /* Write the ring initialization command to C2PMSG_101 */
246 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
247 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
248
249 /* there might be handshake issue with hardware which needs delay */
250 mdelay(20);
251
252 /* Wait for response flag (bit 31) in C2PMSG_101 */
253 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
254 0x80000000, 0x8000FFFF, false);
255
256 } else {
257 /* Wait for sOS ready for ring creation */
258 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
259 0x80000000, 0x80000000, false);
260 if (ret) {
261 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
262 return ret;
263 }
264
265 /* Write low address of the ring to C2PMSG_69 */
266 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
267 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
268 /* Write high address of the ring to C2PMSG_70 */
269 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
270 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
271 /* Write size of ring to C2PMSG_71 */
272 psp_ring_reg = ring->ring_size;
273 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
274 /* Write the ring initialization command to C2PMSG_64 */
275 psp_ring_reg = ring_type;
276 psp_ring_reg = psp_ring_reg << 16;
277 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
278
279 /* there might be handshake issue with hardware which needs delay */
280 mdelay(20);
281
282 /* Wait for response flag (bit 31) in C2PMSG_64 */
283 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
284 0x80000000, 0x8000FFFF, false);
285 }
286
287 return ret;
288 }
289
psp_v13_0_4_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)290 static int psp_v13_0_4_ring_destroy(struct psp_context *psp,
291 enum psp_ring_type ring_type)
292 {
293 int ret = 0;
294 struct psp_ring *ring = &psp->km_ring;
295 struct amdgpu_device *adev = psp->adev;
296
297 ret = psp_v13_0_4_ring_stop(psp, ring_type);
298 if (ret)
299 DRM_ERROR("Fail to stop psp ring\n");
300
301 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
302 &ring->ring_mem_mc_addr,
303 (void **)&ring->ring_mem);
304
305 return ret;
306 }
307
psp_v13_0_4_ring_get_wptr(struct psp_context * psp)308 static uint32_t psp_v13_0_4_ring_get_wptr(struct psp_context *psp)
309 {
310 uint32_t data;
311 struct amdgpu_device *adev = psp->adev;
312
313 if (amdgpu_sriov_vf(adev))
314 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
315 else
316 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
317
318 return data;
319 }
320
psp_v13_0_4_ring_set_wptr(struct psp_context * psp,uint32_t value)321 static void psp_v13_0_4_ring_set_wptr(struct psp_context *psp, uint32_t value)
322 {
323 struct amdgpu_device *adev = psp->adev;
324
325 if (amdgpu_sriov_vf(adev)) {
326 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
327 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
328 GFX_CTRL_CMD_ID_CONSUME_CMD);
329 } else
330 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
331 }
332
333 static const struct psp_funcs psp_v13_0_4_funcs = {
334 .init_microcode = psp_v13_0_4_init_microcode,
335 .bootloader_load_kdb = psp_v13_0_4_bootloader_load_kdb,
336 .bootloader_load_spl = psp_v13_0_4_bootloader_load_spl,
337 .bootloader_load_sysdrv = psp_v13_0_4_bootloader_load_sysdrv,
338 .bootloader_load_soc_drv = psp_v13_0_4_bootloader_load_soc_drv,
339 .bootloader_load_intf_drv = psp_v13_0_4_bootloader_load_intf_drv,
340 .bootloader_load_dbg_drv = psp_v13_0_4_bootloader_load_dbg_drv,
341 .bootloader_load_sos = psp_v13_0_4_bootloader_load_sos,
342 .ring_create = psp_v13_0_4_ring_create,
343 .ring_stop = psp_v13_0_4_ring_stop,
344 .ring_destroy = psp_v13_0_4_ring_destroy,
345 .ring_get_wptr = psp_v13_0_4_ring_get_wptr,
346 .ring_set_wptr = psp_v13_0_4_ring_set_wptr,
347 };
348
psp_v13_0_4_set_psp_funcs(struct psp_context * psp)349 void psp_v13_0_4_set_psp_funcs(struct psp_context *psp)
350 {
351 psp->funcs = &psp_v13_0_4_funcs;
352 }
353