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Searched refs:DP (Results 1 – 25 of 193) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.h54 SRI(DP_CONFIG, DP, id), \
55 SRI(DP_DPHY_CNTL, DP, id), \
58 SRI(DP_DPHY_SYM0, DP, id), \
64 SRI(DP_MSE_SAT0, DP, id), \
65 SRI(DP_MSE_SAT1, DP, id), \
66 SRI(DP_MSE_SAT2, DP, id), \
68 SRI(DP_SEC_CNTL, DP, id), \
71 SRI(DP_SEC_CNTL1, DP, id)
88 SRI(DP_CONFIG, DP, id), \
97 SRI(DP_MSE_SAT0, DP, id), \
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dio_link_encoder.h36 SRI(DP_CONFIG, DP, id), \
37 SRI(DP_DPHY_CNTL, DP, id), \
40 SRI(DP_DPHY_SYM0, DP, id), \
41 SRI(DP_DPHY_SYM1, DP, id), \
42 SRI(DP_DPHY_SYM2, DP, id), \
44 SRI(DP_LINK_CNTL, DP, id), \
46 SRI(DP_MSE_SAT0, DP, id), \
47 SRI(DP_MSE_SAT1, DP, id), \
48 SRI(DP_MSE_SAT2, DP, id), \
50 SRI(DP_SEC_CNTL, DP, id), \
[all …]
H A Ddcn30_dio_stream_encoder.h76 SRI(DP_DB_CNTL, DP, id), \
77 SRI(DP_MSA_MISC, DP, id), \
87 SRI(DP_SEC_CNTL, DP, id), \
88 SRI(DP_SEC_CNTL1, DP, id), \
89 SRI(DP_SEC_CNTL2, DP, id), \
90 SRI(DP_SEC_CNTL5, DP, id), \
91 SRI(DP_SEC_CNTL6, DP, id), \
93 SRI(DP_VID_M, DP, id), \
94 SRI(DP_VID_N, DP, id), \
97 SRI(DP_SEC_AUD_N, DP, id), \
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_dio_link_encoder.h37 SRI(DP_CONFIG, DP, id), \
38 SRI(DP_DPHY_CNTL, DP, id), \
41 SRI(DP_DPHY_SYM0, DP, id), \
42 SRI(DP_DPHY_SYM1, DP, id), \
43 SRI(DP_DPHY_SYM2, DP, id), \
45 SRI(DP_LINK_CNTL, DP, id), \
47 SRI(DP_MSE_SAT0, DP, id), \
48 SRI(DP_MSE_SAT1, DP, id), \
49 SRI(DP_MSE_SAT2, DP, id), \
51 SRI(DP_SEC_CNTL, DP, id), \
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dg4x_dp.c130 intel_dp->DP |= DP_SYNC_HS_HIGH; in intel_dp_prepare()
132 intel_dp->DP |= DP_SYNC_VS_HIGH; in intel_dp_prepare()
151 intel_dp->DP |= DP_SYNC_HS_HIGH; in intel_dp_prepare()
153 intel_dp->DP |= DP_SYNC_VS_HIGH; in intel_dp_prepare()
223 intel_dp->DP |= DP_PLL_ENABLE; in ilk_edp_pll_on()
242 intel_dp->DP &= ~DP_PLL_ENABLE; in ilk_edp_pll_off()
459 intel_dp->DP &= ~DP_PORT_EN; in intel_dp_link_down()
633 intel_dp->DP |= DP_PORT_EN; in intel_dp_enable_port()
1011 intel_dp->DP |= signal_levels; in g4x_set_signal_levels()
1059 intel_dp->DP |= signal_levels; in snb_cpu_edp_set_signal_levels()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dio_stream_encoder.h77 SRI(DP_DB_CNTL, DP, id), \
78 SRI(DP_MSA_MISC, DP, id), \
88 SRI(DP_SEC_CNTL, DP, id), \
89 SRI(DP_SEC_CNTL1, DP, id), \
90 SRI(DP_SEC_CNTL2, DP, id), \
91 SRI(DP_SEC_CNTL5, DP, id), \
92 SRI(DP_SEC_CNTL6, DP, id), \
94 SRI(DP_VID_M, DP, id), \
95 SRI(DP_VID_N, DP, id), \
98 SRI(DP_SEC_AUD_N, DP, id), \
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Ddp-aux-bus.yaml14 are hooked up to them. This is the DP AUX bus. Over the DP AUX bus
16 particular, DP sinks support DDC over DP AUX which allows tunneling
19 To model this relationship, DP sinks should be placed as children
20 of the DP controller under the "aux-bus" node.
23 possible it will be extended in the future to handle the DP case.
24 For DP, presumably a connector would be listed under the DP AUX
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_ethtool.c409 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_link_ksettings()
418 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_link_ksettings()
498 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_link_ksettings()
1949 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_ringparam()
1954 DP(BNX2X_MSG_IOV, in bnx2x_set_ringparam()
1960 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_ringparam()
2049 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_pauseparam()
3017 DP(BNX2X_MSG_IOV, in bnx2x_self_test()
3029 DP(BNX2X_MSG_ETHTOOL, in bnx2x_self_test()
3384 DP(BNX2X_MSG_ETHTOOL, in bnx2x_set_rss_flags()
[all …]
H A Dbnx2x_dcb.c134 DP(NETIF_MSG_LINK, in bnx2x_dump_dcbx_drv_param()
137 DP(NETIF_MSG_LINK, in bnx2x_dump_dcbx_drv_param()
141 DP(NETIF_MSG_LINK, in bnx2x_dump_dcbx_drv_param()
160 DP(BNX2X_MSG_DCB, in bnx2x_dump_dcbx_drv_param()
163 DP(BNX2X_MSG_DCB, in bnx2x_dump_dcbx_drv_param()
166 DP(BNX2X_MSG_DCB, in bnx2x_dump_dcbx_drv_param()
365 DP(BNX2X_MSG_DCB, in bnx2x_dcbx_map_nw()
1080 DP(BNX2X_MSG_DCB, in bnx2x_dcbx_print_cos_params()
1082 DP(BNX2X_MSG_DCB, in bnx2x_dcbx_print_cos_params()
1087 DP(BNX2X_MSG_DCB, in bnx2x_dcbx_print_cos_params()
[all …]
H A Dbnx2x_link.c750 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_disabled()
923 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_get_total_bw()
927 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_get_total_bw()
1146 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_config()
1164 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_config()
1198 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_config()
1203 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_config()
1214 DP(NETIF_MSG_LINK, in bnx2x_ets_e3b0_config()
1661 DP(NETIF_MSG_LINK, in bnx2x_xmac_init()
7217 DP(NETIF_MSG_LINK, in bnx2x_8073_8727_external_rom_boot()
[all …]
H A Dbnx2x_sriov.c131 DP(BNX2X_MSG_IOV, in bnx2x_vfop_qctor_dump_tx()
736 DP(BNX2X_MSG_IOV, in bnx2x_vf_igu_reset()
964 DP(BNX2X_MSG_MCP, in bnx2x_vf_handle_flr_event()
983 DP(BNX2X_MSG_IOV, in bnx2x_vf_handle_flr_event()
1159 DP(BNX2X_MSG_IOV, in bnx2x_sriov_info()
1434 DP(BNX2X_MSG_IOV, in bnx2x_vfq_init()
1566 DP(BNX2X_MSG_IOV, in bnx2x_iov_nic_init()
1618 DP(BNX2X_MSG_IOV, in bnx2x_iov_nic_init()
2047 DP(BNX2X_MSG_IOV, in bnx2x_vf_acquire()
2058 DP(BNX2X_MSG_IOV, in bnx2x_vf_acquire()
[all …]
H A Dbnx2x_main.c1604 DP(NETIF_MSG_IFUP, in bnx2x_hc_int_enable()
1822 DP(BNX2X_MSG_SP, in bnx2x_sp_event()
2601 DP(NETIF_MSG_IFUP, in bnx2x_cmng_fns_init()
2818 DP(BNX2X_MSG_MCP, in bnx2x_handle_afex_cmd()
2826 DP(BNX2X_MSG_MCP, in bnx2x_handle_afex_cmd()
2839 DP(BNX2X_MSG_MCP, in bnx2x_handle_afex_cmd()
2857 DP(BNX2X_MSG_MCP, in bnx2x_handle_afex_cmd()
3944 DP(BNX2X_MSG_SP, in bnx2x_sp_post()
5225 DP(NETIF_MSG_HW, in bnx2x_attn_int()
5372 DP(BNX2X_MSG_SP, in bnx2x_after_afex_vif_lists()
[all …]
H A Dbnx2x_sp.c131 DP(BNX2X_MSG_SP, "Preamble failed: %d\n", rc); in bnx2x_exe_queue_add()
1703 DP(BNX2X_MSG_SP, "Optimizing %s command\n", in bnx2x_optimize_vlan_mac()
2884 DP(BNX2X_MSG_SP, "%s bin %d\n", in bnx2x_mcast_set_one_rule_e2()
3550 DP(BNX2X_MSG_SP, in bnx2x_mcast_setup_e1h()
3869 DP(BNX2X_MSG_SP, "Deleting a registry\n"); in bnx2x_mcast_refresh_registry_e1()
4460 DP(BNX2X_MSG_SP, "0x0000: "); in bnx2x_debug_print_ind_table()
4468 DP(BNX2X_MSG_SP, "0x%04x: ", i + 1); in bnx2x_debug_print_ind_table()
4496 DP(BNX2X_MSG_SP, "Configuring RSS\n"); in bnx2x_setup_rss()
4755 DP(BNX2X_MSG_SP, in bnx2x_queue_comp_cmd()
5759 DP(BNX2X_MSG_SP, in bnx2x_func_state_change_comp()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sm8450-dispcc.yaml34 - description: Link clock from DP PHY0
35 - description: VCO DIV clock from DP PHY0
36 - description: Link clock from DP PHY1
37 - description: VCO DIV clock from DP PHY1
38 - description: Link clock from DP PHY2
39 - description: VCO DIV clock from DP PHY2
40 - description: Link clock from DP PHY3
41 - description: VCO DIV clock from DP PHY3
H A Dqcom,sm8550-dispcc.yaml34 - description: Link clock from DP PHY0
35 - description: VCO DIV clock from DP PHY0
36 - description: Link clock from DP PHY1
37 - description: VCO DIV clock from DP PHY1
38 - description: Link clock from DP PHY2
39 - description: VCO DIV clock from DP PHY2
40 - description: Link clock from DP PHY3
41 - description: VCO DIV clock from DP PHY3
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_link_encoder.h47 SRI(DP_CONFIG, DP, id), \
48 SRI(DP_DPHY_CNTL, DP, id), \
51 SRI(DP_DPHY_SYM0, DP, id), \
52 SRI(DP_DPHY_SYM1, DP, id), \
53 SRI(DP_DPHY_SYM2, DP, id), \
55 SRI(DP_LINK_CNTL, DP, id), \
57 SRI(DP_MSE_SAT0, DP, id), \
58 SRI(DP_MSE_SAT1, DP, id), \
59 SRI(DP_MSE_SAT2, DP, id), \
61 SRI(DP_SEC_CNTL, DP, id), \
[all …]
H A Ddcn10_stream_encoder.h74 SRI(DP_DB_CNTL, DP, id), \
75 SRI(DP_MSA_MISC, DP, id), \
85 SRI(DP_SEC_CNTL, DP, id), \
86 SRI(DP_SEC_CNTL1, DP, id), \
87 SRI(DP_SEC_CNTL2, DP, id), \
88 SRI(DP_SEC_CNTL5, DP, id), \
89 SRI(DP_SEC_CNTL6, DP, id), \
90 SRI(DP_STEER_FIFO, DP, id), \
91 SRI(DP_VID_M, DP, id), \
92 SRI(DP_VID_N, DP, id), \
[all …]
/openbmc/linux/Documentation/sound/hd-audio/
H A Ddp-mst.rst2 HD-Audio DP-MST Support
5 To support DP MST audio, HD Audio hdmi codec driver introduces virtual pin
8 Virtual pin is an extension of per_pin. The most difference of DP MST
9 from legacy is that DP MST introduces device entry. Each pin can contain
25 the device entries number is dynamically changed. If DP MST hub is connected,
26 it is in DP MST mode, and the device entries number is 3. Otherwise, the
30 when bootup no matter whether it is in DP MST mode or not.
34 DP MST reuses connection list code. The code can be reused because
37 This means DP MST gets the device entry connection list without the
/openbmc/linux/drivers/gpu/drm/bridge/cadence/
H A DKconfig25 tristate "Cadence DPI/DP bridge"
33 Support Cadence DPI to DP bridge. This is an internal
36 in DP format.
42 bool "J721E Cadence DPI/DP wrapper support"
45 Support J721E Cadence DPI/DP wrapper. This is a wrapper
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Dmegachips-stdpxxxx-ge-b850v3-fw.txt2 STDP4028-ge-b850v3-fw bridges (LVDS-DP)
3 STDP2690-ge-b850v3-fw bridges (DP-DP++)
7 Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
H A Dcdns,mhdp8546.yaml41 DP bridge clock, used by the IP to know how to translate a number of
42 clock cycles into a time (which is used to comply with DP standard timings
67 First input port representing the DP bridge input.
72 Second input port representing the DP bridge input.
77 Third input port representing the DP bridge input.
82 Fourth input port representing the DP bridge input.
87 Output port representing the DP bridge output.
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource.h281 SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \
282 SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \
287 SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \
288 SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \
289 SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \
290 SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \
291 SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id), \
292 SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \
293 SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id), \
294 SRI_ARR(DP_SEC_TIMESTAMP, DP, id), SRI_ARR(DP_DSC_CNTL, DP, id), \
[all …]
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c256 uint32_t DP; member
1474 uint32_t DP = intel_dp->DP; in cdv_intel_dp_start_link_train() local
1476 DP |= DP_PORT_EN; in cdv_intel_dp_start_link_train()
1477 DP &= ~DP_LINK_TRAIN_MASK; in cdv_intel_dp_start_link_train()
1479 reg = DP; in cdv_intel_dp_start_link_train()
1498 reg = DP | DP_LINK_TRAIN_PAT_1; in cdv_intel_dp_start_link_train()
1554 intel_dp->DP = DP; in cdv_intel_dp_start_link_train()
1564 uint32_t DP = intel_dp->DP; in cdv_intel_dp_complete_link_train() local
1632 reg = DP | DP_LINK_TRAIN_OFF; in cdv_intel_dp_complete_link_train()
1645 uint32_t DP = intel_dp->DP; in cdv_intel_dp_link_down() local
[all …]
/openbmc/u-boot/drivers/video/bridge/
H A DKconfig11 bool "Support Parade PS862X DP->LVDS bridge"
21 bool "Support NXP PTN3460 DP->LVDS bridge"
30 bool "Support Analogix ANX6345 RGB->DP bridge"
34 The Analogix ANX6345 is RGB-to-DP converter. It enables an eDP LCD
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_stream_encoder.h37 SRI(DP_DSC_CNTL, DP, id), \
38 SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \
40 SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
42 SRI(DP_SEC_FRAMING4, DP, id)

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