| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 89 #define CLK_TOP_MEM_SEL 78 macro
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| H A D | mt7629-clk.h | 84 #define CLK_TOP_MEM_SEL 74 macro
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| H A D | mt7622-clk.h | 69 #define CLK_TOP_MEM_SEL 57 macro
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| H A D | mediatek,mt6795-clk.h | 91 #define CLK_TOP_MEM_SEL 80 macro
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| H A D | mt6765-clk.h | 132 #define CLK_TOP_MEM_SEL 97 macro
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| H A D | mt8173-clk.h | 93 #define CLK_TOP_MEM_SEL 83 macro
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| H A D | mediatek,mt8365-clk.h | 72 #define CLK_TOP_MEM_SEL 62 macro
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| H A D | mt2712-clk.h | 131 #define CLK_TOP_MEM_SEL 100 macro
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| H A D | mt2701-clk.h | 89 #define CLK_TOP_MEM_SEL 78 macro
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 88 #define CLK_TOP_MEM_SEL 74 macro
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| H A D | mt7623-clk.h | 102 #define CLK_TOP_MEM_SEL 88 macro
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7623.c | 509 MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
604 GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8),
607 GATE_INFRA(CLK_INFRA_RAMBUFIF, CLK_TOP_MEM_SEL, 14),
608 GATE_INFRA(CLK_INFRA_CPUM, CLK_TOP_MEM_SEL, 15),
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| H A D | clk-mt7629.c | 365 MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt7629.c | 464 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
572 clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk); in mtk_topckgen_init()
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| H A D | clk-mt6795-topckgen.c | 454 TOP_MUX_GATE_NOSR(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
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| H A D | clk-mt8173-topckgen.c | 532 MUX_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1,
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| H A D | clk-mt8135.c | 377 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
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| H A D | clk-mt7622.c | 388 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
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| H A D | clk-mt2712.c | 646 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
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| H A D | clk-mt8365.c | 413 MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040,
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| H A D | clk-mt6765.c | 372 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
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| H A D | clk-mt2701.c | 489 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | mt7629.dtsi | 124 <&topckgen CLK_TOP_MEM_SEL>,
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