13b5e7486SRyder Lee /* SPDX-License-Identifier: GPL-2.0 */ 23b5e7486SRyder Lee /* 33b5e7486SRyder Lee * Copyright (C) 2018 MediaTek Inc. 43b5e7486SRyder Lee */ 53b5e7486SRyder Lee 63b5e7486SRyder Lee #ifndef _DT_BINDINGS_CLK_MT7629_H 73b5e7486SRyder Lee #define _DT_BINDINGS_CLK_MT7629_H 83b5e7486SRyder Lee 93b5e7486SRyder Lee /* TOPCKGEN */ 103b5e7486SRyder Lee #define CLK_TOP_TO_U2_PHY 0 113b5e7486SRyder Lee #define CLK_TOP_TO_U2_PHY_1P 1 123b5e7486SRyder Lee #define CLK_TOP_PCIE0_PIPE_EN 2 133b5e7486SRyder Lee #define CLK_TOP_PCIE1_PIPE_EN 3 143b5e7486SRyder Lee #define CLK_TOP_SSUSB_TX250M 4 153b5e7486SRyder Lee #define CLK_TOP_SSUSB_EQ_RX250M 5 163b5e7486SRyder Lee #define CLK_TOP_SSUSB_CDR_REF 6 173b5e7486SRyder Lee #define CLK_TOP_SSUSB_CDR_FB 7 183b5e7486SRyder Lee #define CLK_TOP_SATA_ASIC 8 193b5e7486SRyder Lee #define CLK_TOP_SATA_RBC 9 203b5e7486SRyder Lee #define CLK_TOP_TO_USB3_SYS 10 213b5e7486SRyder Lee #define CLK_TOP_P1_1MHZ 11 223b5e7486SRyder Lee #define CLK_TOP_4MHZ 12 233b5e7486SRyder Lee #define CLK_TOP_P0_1MHZ 13 243b5e7486SRyder Lee #define CLK_TOP_ETH_500M 14 253b5e7486SRyder Lee #define CLK_TOP_TXCLK_SRC_PRE 15 263b5e7486SRyder Lee #define CLK_TOP_RTC 16 273b5e7486SRyder Lee #define CLK_TOP_PWM_QTR_26M 17 283b5e7486SRyder Lee #define CLK_TOP_CPUM_TCK_IN 18 293b5e7486SRyder Lee #define CLK_TOP_TO_USB3_DA_TOP 19 303b5e7486SRyder Lee #define CLK_TOP_MEMPLL 20 313b5e7486SRyder Lee #define CLK_TOP_DMPLL 21 323b5e7486SRyder Lee #define CLK_TOP_DMPLL_D4 22 333b5e7486SRyder Lee #define CLK_TOP_DMPLL_D8 23 343b5e7486SRyder Lee #define CLK_TOP_SYSPLL_D2 24 353b5e7486SRyder Lee #define CLK_TOP_SYSPLL1_D2 25 363b5e7486SRyder Lee #define CLK_TOP_SYSPLL1_D4 26 373b5e7486SRyder Lee #define CLK_TOP_SYSPLL1_D8 27 383b5e7486SRyder Lee #define CLK_TOP_SYSPLL1_D16 28 393b5e7486SRyder Lee #define CLK_TOP_SYSPLL2_D2 29 403b5e7486SRyder Lee #define CLK_TOP_SYSPLL2_D4 30 413b5e7486SRyder Lee #define CLK_TOP_SYSPLL2_D8 31 423b5e7486SRyder Lee #define CLK_TOP_SYSPLL_D5 32 433b5e7486SRyder Lee #define CLK_TOP_SYSPLL3_D2 33 443b5e7486SRyder Lee #define CLK_TOP_SYSPLL3_D4 34 453b5e7486SRyder Lee #define CLK_TOP_SYSPLL_D7 35 463b5e7486SRyder Lee #define CLK_TOP_SYSPLL4_D2 36 473b5e7486SRyder Lee #define CLK_TOP_SYSPLL4_D4 37 483b5e7486SRyder Lee #define CLK_TOP_SYSPLL4_D16 38 493b5e7486SRyder Lee #define CLK_TOP_UNIVPLL 39 503b5e7486SRyder Lee #define CLK_TOP_UNIVPLL1_D2 40 513b5e7486SRyder Lee #define CLK_TOP_UNIVPLL1_D4 41 523b5e7486SRyder Lee #define CLK_TOP_UNIVPLL1_D8 42 533b5e7486SRyder Lee #define CLK_TOP_UNIVPLL_D3 43 543b5e7486SRyder Lee #define CLK_TOP_UNIVPLL2_D2 44 553b5e7486SRyder Lee #define CLK_TOP_UNIVPLL2_D4 45 563b5e7486SRyder Lee #define CLK_TOP_UNIVPLL2_D8 46 573b5e7486SRyder Lee #define CLK_TOP_UNIVPLL2_D16 47 583b5e7486SRyder Lee #define CLK_TOP_UNIVPLL_D5 48 593b5e7486SRyder Lee #define CLK_TOP_UNIVPLL3_D2 49 603b5e7486SRyder Lee #define CLK_TOP_UNIVPLL3_D4 50 613b5e7486SRyder Lee #define CLK_TOP_UNIVPLL3_D16 51 623b5e7486SRyder Lee #define CLK_TOP_UNIVPLL_D7 52 633b5e7486SRyder Lee #define CLK_TOP_UNIVPLL_D80_D4 53 643b5e7486SRyder Lee #define CLK_TOP_UNIV48M 54 653b5e7486SRyder Lee #define CLK_TOP_SGMIIPLL_D2 55 663b5e7486SRyder Lee #define CLK_TOP_CLKXTAL_D4 56 673b5e7486SRyder Lee #define CLK_TOP_HD_FAXI 57 683b5e7486SRyder Lee #define CLK_TOP_FAXI 58 693b5e7486SRyder Lee #define CLK_TOP_F_FAUD_INTBUS 59 703b5e7486SRyder Lee #define CLK_TOP_AP2WBHIF_HCLK 60 713b5e7486SRyder Lee #define CLK_TOP_10M_INFRAO 61 723b5e7486SRyder Lee #define CLK_TOP_MSDC30_1 62 733b5e7486SRyder Lee #define CLK_TOP_SPI 63 743b5e7486SRyder Lee #define CLK_TOP_SF 64 753b5e7486SRyder Lee #define CLK_TOP_FLASH 65 763b5e7486SRyder Lee #define CLK_TOP_TO_USB3_REF 66 773b5e7486SRyder Lee #define CLK_TOP_TO_USB3_MCU 67 783b5e7486SRyder Lee #define CLK_TOP_TO_USB3_DMA 68 793b5e7486SRyder Lee #define CLK_TOP_FROM_TOP_AHB 69 803b5e7486SRyder Lee #define CLK_TOP_FROM_TOP_AXI 70 813b5e7486SRyder Lee #define CLK_TOP_PCIE1_MAC_EN 71 823b5e7486SRyder Lee #define CLK_TOP_PCIE0_MAC_EN 72 833b5e7486SRyder Lee #define CLK_TOP_AXI_SEL 73 843b5e7486SRyder Lee #define CLK_TOP_MEM_SEL 74 853b5e7486SRyder Lee #define CLK_TOP_DDRPHYCFG_SEL 75 863b5e7486SRyder Lee #define CLK_TOP_ETH_SEL 76 873b5e7486SRyder Lee #define CLK_TOP_PWM_SEL 77 883b5e7486SRyder Lee #define CLK_TOP_F10M_REF_SEL 78 893b5e7486SRyder Lee #define CLK_TOP_NFI_INFRA_SEL 79 903b5e7486SRyder Lee #define CLK_TOP_FLASH_SEL 80 913b5e7486SRyder Lee #define CLK_TOP_UART_SEL 81 923b5e7486SRyder Lee #define CLK_TOP_SPI0_SEL 82 933b5e7486SRyder Lee #define CLK_TOP_SPI1_SEL 83 943b5e7486SRyder Lee #define CLK_TOP_MSDC50_0_SEL 84 953b5e7486SRyder Lee #define CLK_TOP_MSDC30_0_SEL 85 963b5e7486SRyder Lee #define CLK_TOP_MSDC30_1_SEL 86 973b5e7486SRyder Lee #define CLK_TOP_AP2WBMCU_SEL 87 983b5e7486SRyder Lee #define CLK_TOP_AP2WBHIF_SEL 88 993b5e7486SRyder Lee #define CLK_TOP_AUDIO_SEL 89 1003b5e7486SRyder Lee #define CLK_TOP_AUD_INTBUS_SEL 90 1013b5e7486SRyder Lee #define CLK_TOP_PMICSPI_SEL 91 1023b5e7486SRyder Lee #define CLK_TOP_SCP_SEL 92 1033b5e7486SRyder Lee #define CLK_TOP_ATB_SEL 93 1043b5e7486SRyder Lee #define CLK_TOP_HIF_SEL 94 1053b5e7486SRyder Lee #define CLK_TOP_SATA_SEL 95 1063b5e7486SRyder Lee #define CLK_TOP_U2_SEL 96 1073b5e7486SRyder Lee #define CLK_TOP_AUD1_SEL 97 1083b5e7486SRyder Lee #define CLK_TOP_AUD2_SEL 98 1093b5e7486SRyder Lee #define CLK_TOP_IRRX_SEL 99 1103b5e7486SRyder Lee #define CLK_TOP_IRTX_SEL 100 1113b5e7486SRyder Lee #define CLK_TOP_SATA_MCU_SEL 101 1123b5e7486SRyder Lee #define CLK_TOP_PCIE0_MCU_SEL 102 1133b5e7486SRyder Lee #define CLK_TOP_PCIE1_MCU_SEL 103 1143b5e7486SRyder Lee #define CLK_TOP_SSUSB_MCU_SEL 104 1153b5e7486SRyder Lee #define CLK_TOP_CRYPTO_SEL 105 1163b5e7486SRyder Lee #define CLK_TOP_SGMII_REF_1_SEL 106 1173b5e7486SRyder Lee #define CLK_TOP_10M_SEL 107 1183b5e7486SRyder Lee #define CLK_TOP_NR_CLK 108 1193b5e7486SRyder Lee 1203b5e7486SRyder Lee /* INFRACFG */ 1213b5e7486SRyder Lee #define CLK_INFRA_MUX1_SEL 0 1223b5e7486SRyder Lee #define CLK_INFRA_DBGCLK_PD 1 1233b5e7486SRyder Lee #define CLK_INFRA_TRNG_PD 2 1243b5e7486SRyder Lee #define CLK_INFRA_DEVAPC_PD 3 1253b5e7486SRyder Lee #define CLK_INFRA_APXGPT_PD 4 1263b5e7486SRyder Lee #define CLK_INFRA_SEJ_PD 5 1273b5e7486SRyder Lee #define CLK_INFRA_NR_CLK 6 1283b5e7486SRyder Lee 1293b5e7486SRyder Lee /* PERICFG */ 1303b5e7486SRyder Lee #define CLK_PERIBUS_SEL 0 1313b5e7486SRyder Lee #define CLK_PERI_PWM1_PD 1 1323b5e7486SRyder Lee #define CLK_PERI_PWM2_PD 2 1333b5e7486SRyder Lee #define CLK_PERI_PWM3_PD 3 1343b5e7486SRyder Lee #define CLK_PERI_PWM4_PD 4 1353b5e7486SRyder Lee #define CLK_PERI_PWM5_PD 5 1363b5e7486SRyder Lee #define CLK_PERI_PWM6_PD 6 1373b5e7486SRyder Lee #define CLK_PERI_PWM7_PD 7 1383b5e7486SRyder Lee #define CLK_PERI_PWM_PD 8 1393b5e7486SRyder Lee #define CLK_PERI_AP_DMA_PD 9 1403b5e7486SRyder Lee #define CLK_PERI_MSDC30_1_PD 10 1413b5e7486SRyder Lee #define CLK_PERI_UART0_PD 11 1423b5e7486SRyder Lee #define CLK_PERI_UART1_PD 12 1433b5e7486SRyder Lee #define CLK_PERI_UART2_PD 13 1443b5e7486SRyder Lee #define CLK_PERI_UART3_PD 14 1453b5e7486SRyder Lee #define CLK_PERI_BTIF_PD 15 1463b5e7486SRyder Lee #define CLK_PERI_I2C0_PD 16 1473b5e7486SRyder Lee #define CLK_PERI_SPI0_PD 17 1483b5e7486SRyder Lee #define CLK_PERI_SNFI_PD 18 1493b5e7486SRyder Lee #define CLK_PERI_NFI_PD 19 1503b5e7486SRyder Lee #define CLK_PERI_NFIECC_PD 20 1513b5e7486SRyder Lee #define CLK_PERI_FLASH_PD 21 1523b5e7486SRyder Lee #define CLK_PERI_NR_CLK 22 1533b5e7486SRyder Lee 1543b5e7486SRyder Lee /* APMIXEDSYS */ 1553b5e7486SRyder Lee #define CLK_APMIXED_ARMPLL 0 1563b5e7486SRyder Lee #define CLK_APMIXED_MAINPLL 1 1573b5e7486SRyder Lee #define CLK_APMIXED_UNIV2PLL 2 1583b5e7486SRyder Lee #define CLK_APMIXED_ETH1PLL 3 1593b5e7486SRyder Lee #define CLK_APMIXED_ETH2PLL 4 1603b5e7486SRyder Lee #define CLK_APMIXED_SGMIPLL 5 1613b5e7486SRyder Lee #define CLK_APMIXED_MAIN_CORE_EN 6 1623b5e7486SRyder Lee #define CLK_APMIXED_NR_CLK 7 1633b5e7486SRyder Lee 1643b5e7486SRyder Lee /* SSUSBSYS */ 1653b5e7486SRyder Lee #define CLK_SSUSB_U2_PHY_1P_EN 0 1663b5e7486SRyder Lee #define CLK_SSUSB_U2_PHY_EN 1 1673b5e7486SRyder Lee #define CLK_SSUSB_REF_EN 2 1683b5e7486SRyder Lee #define CLK_SSUSB_SYS_EN 3 1693b5e7486SRyder Lee #define CLK_SSUSB_MCU_EN 4 1703b5e7486SRyder Lee #define CLK_SSUSB_DMA_EN 5 1713b5e7486SRyder Lee #define CLK_SSUSB_NR_CLK 6 1723b5e7486SRyder Lee 1733b5e7486SRyder Lee /* PCIESYS */ 1743b5e7486SRyder Lee #define CLK_PCIE_P1_AUX_EN 0 1753b5e7486SRyder Lee #define CLK_PCIE_P1_OBFF_EN 1 1763b5e7486SRyder Lee #define CLK_PCIE_P1_AHB_EN 2 1773b5e7486SRyder Lee #define CLK_PCIE_P1_AXI_EN 3 1783b5e7486SRyder Lee #define CLK_PCIE_P1_MAC_EN 4 1793b5e7486SRyder Lee #define CLK_PCIE_P1_PIPE_EN 5 1803b5e7486SRyder Lee #define CLK_PCIE_P0_AUX_EN 6 1813b5e7486SRyder Lee #define CLK_PCIE_P0_OBFF_EN 7 1823b5e7486SRyder Lee #define CLK_PCIE_P0_AHB_EN 8 1833b5e7486SRyder Lee #define CLK_PCIE_P0_AXI_EN 9 1843b5e7486SRyder Lee #define CLK_PCIE_P0_MAC_EN 10 1853b5e7486SRyder Lee #define CLK_PCIE_P0_PIPE_EN 11 1863b5e7486SRyder Lee #define CLK_PCIE_NR_CLK 12 1873b5e7486SRyder Lee 1883b5e7486SRyder Lee /* ETHSYS */ 1893b5e7486SRyder Lee #define CLK_ETH_FE_EN 0 1903b5e7486SRyder Lee #define CLK_ETH_GP2_EN 1 1913b5e7486SRyder Lee #define CLK_ETH_GP1_EN 2 1923b5e7486SRyder Lee #define CLK_ETH_GP0_EN 3 1933b5e7486SRyder Lee #define CLK_ETH_ESW_EN 4 1943b5e7486SRyder Lee #define CLK_ETH_NR_CLK 5 1953b5e7486SRyder Lee 1963b5e7486SRyder Lee /* SGMIISYS */ 1973b5e7486SRyder Lee #define CLK_SGMII_TX_EN 0 1983b5e7486SRyder Lee #define CLK_SGMII_RX_EN 1 1993b5e7486SRyder Lee #define CLK_SGMII_CDR_REF 2 2003b5e7486SRyder Lee #define CLK_SGMII_CDR_FB 3 2013b5e7486SRyder Lee #define CLK_SGMII_NR_CLK 4 2023b5e7486SRyder Lee 2033b5e7486SRyder Lee #endif /* _DT_BINDINGS_CLK_MT7629_H */ 204