11802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2bda921faSChen Zhong /* 3bda921faSChen Zhong * Copyright (c) 2017 MediaTek Inc. 4bda921faSChen Zhong * Author: Chen Zhong <chen.zhong@mediatek.com> 5bda921faSChen Zhong */ 6bda921faSChen Zhong 7bda921faSChen Zhong #ifndef _DT_BINDINGS_CLK_MT7622_H 8bda921faSChen Zhong #define _DT_BINDINGS_CLK_MT7622_H 9bda921faSChen Zhong 10bda921faSChen Zhong /* TOPCKGEN */ 11bda921faSChen Zhong 12bda921faSChen Zhong #define CLK_TOP_TO_U2_PHY 0 13bda921faSChen Zhong #define CLK_TOP_TO_U2_PHY_1P 1 14bda921faSChen Zhong #define CLK_TOP_PCIE0_PIPE_EN 2 15bda921faSChen Zhong #define CLK_TOP_PCIE1_PIPE_EN 3 16bda921faSChen Zhong #define CLK_TOP_SSUSB_TX250M 4 17bda921faSChen Zhong #define CLK_TOP_SSUSB_EQ_RX250M 5 18bda921faSChen Zhong #define CLK_TOP_SSUSB_CDR_REF 6 19bda921faSChen Zhong #define CLK_TOP_SSUSB_CDR_FB 7 20bda921faSChen Zhong #define CLK_TOP_SATA_ASIC 8 21bda921faSChen Zhong #define CLK_TOP_SATA_RBC 9 22bda921faSChen Zhong #define CLK_TOP_TO_USB3_SYS 10 23bda921faSChen Zhong #define CLK_TOP_P1_1MHZ 11 24bda921faSChen Zhong #define CLK_TOP_4MHZ 12 25bda921faSChen Zhong #define CLK_TOP_P0_1MHZ 13 26bda921faSChen Zhong #define CLK_TOP_TXCLK_SRC_PRE 14 27bda921faSChen Zhong #define CLK_TOP_RTC 15 28bda921faSChen Zhong #define CLK_TOP_MEMPLL 16 29bda921faSChen Zhong #define CLK_TOP_DMPLL 17 30bda921faSChen Zhong #define CLK_TOP_SYSPLL_D2 18 31bda921faSChen Zhong #define CLK_TOP_SYSPLL1_D2 19 32bda921faSChen Zhong #define CLK_TOP_SYSPLL1_D4 20 33bda921faSChen Zhong #define CLK_TOP_SYSPLL1_D8 21 34bda921faSChen Zhong #define CLK_TOP_SYSPLL2_D4 22 35bda921faSChen Zhong #define CLK_TOP_SYSPLL2_D8 23 36bda921faSChen Zhong #define CLK_TOP_SYSPLL_D5 24 37bda921faSChen Zhong #define CLK_TOP_SYSPLL3_D2 25 38bda921faSChen Zhong #define CLK_TOP_SYSPLL3_D4 26 39bda921faSChen Zhong #define CLK_TOP_SYSPLL4_D2 27 40bda921faSChen Zhong #define CLK_TOP_SYSPLL4_D4 28 41bda921faSChen Zhong #define CLK_TOP_SYSPLL4_D16 29 42bda921faSChen Zhong #define CLK_TOP_UNIVPLL 30 43bda921faSChen Zhong #define CLK_TOP_UNIVPLL_D2 31 44bda921faSChen Zhong #define CLK_TOP_UNIVPLL1_D2 32 45bda921faSChen Zhong #define CLK_TOP_UNIVPLL1_D4 33 46bda921faSChen Zhong #define CLK_TOP_UNIVPLL1_D8 34 47bda921faSChen Zhong #define CLK_TOP_UNIVPLL1_D16 35 48bda921faSChen Zhong #define CLK_TOP_UNIVPLL2_D2 36 49bda921faSChen Zhong #define CLK_TOP_UNIVPLL2_D4 37 50bda921faSChen Zhong #define CLK_TOP_UNIVPLL2_D8 38 51bda921faSChen Zhong #define CLK_TOP_UNIVPLL2_D16 39 52bda921faSChen Zhong #define CLK_TOP_UNIVPLL_D5 40 53bda921faSChen Zhong #define CLK_TOP_UNIVPLL3_D2 41 54bda921faSChen Zhong #define CLK_TOP_UNIVPLL3_D4 42 55bda921faSChen Zhong #define CLK_TOP_UNIVPLL3_D16 43 56bda921faSChen Zhong #define CLK_TOP_UNIVPLL_D7 44 57bda921faSChen Zhong #define CLK_TOP_UNIVPLL_D80_D4 45 58bda921faSChen Zhong #define CLK_TOP_UNIV48M 46 59bda921faSChen Zhong #define CLK_TOP_SGMIIPLL 47 60bda921faSChen Zhong #define CLK_TOP_SGMIIPLL_D2 48 61bda921faSChen Zhong #define CLK_TOP_AUD1PLL 49 62bda921faSChen Zhong #define CLK_TOP_AUD2PLL 50 63bda921faSChen Zhong #define CLK_TOP_AUD_I2S2_MCK 51 64bda921faSChen Zhong #define CLK_TOP_TO_USB3_REF 52 65bda921faSChen Zhong #define CLK_TOP_PCIE1_MAC_EN 53 66bda921faSChen Zhong #define CLK_TOP_PCIE0_MAC_EN 54 67bda921faSChen Zhong #define CLK_TOP_ETH_500M 55 68bda921faSChen Zhong #define CLK_TOP_AXI_SEL 56 69bda921faSChen Zhong #define CLK_TOP_MEM_SEL 57 70bda921faSChen Zhong #define CLK_TOP_DDRPHYCFG_SEL 58 71bda921faSChen Zhong #define CLK_TOP_ETH_SEL 59 72bda921faSChen Zhong #define CLK_TOP_PWM_SEL 60 73bda921faSChen Zhong #define CLK_TOP_F10M_REF_SEL 61 74bda921faSChen Zhong #define CLK_TOP_NFI_INFRA_SEL 62 75bda921faSChen Zhong #define CLK_TOP_FLASH_SEL 63 76bda921faSChen Zhong #define CLK_TOP_UART_SEL 64 77bda921faSChen Zhong #define CLK_TOP_SPI0_SEL 65 78bda921faSChen Zhong #define CLK_TOP_SPI1_SEL 66 79bda921faSChen Zhong #define CLK_TOP_MSDC50_0_SEL 67 80bda921faSChen Zhong #define CLK_TOP_MSDC30_0_SEL 68 81bda921faSChen Zhong #define CLK_TOP_MSDC30_1_SEL 69 82bda921faSChen Zhong #define CLK_TOP_A1SYS_HP_SEL 70 83bda921faSChen Zhong #define CLK_TOP_A2SYS_HP_SEL 71 84bda921faSChen Zhong #define CLK_TOP_INTDIR_SEL 72 85bda921faSChen Zhong #define CLK_TOP_AUD_INTBUS_SEL 73 86bda921faSChen Zhong #define CLK_TOP_PMICSPI_SEL 74 87bda921faSChen Zhong #define CLK_TOP_SCP_SEL 75 88bda921faSChen Zhong #define CLK_TOP_ATB_SEL 76 89bda921faSChen Zhong #define CLK_TOP_HIF_SEL 77 90bda921faSChen Zhong #define CLK_TOP_AUDIO_SEL 78 91bda921faSChen Zhong #define CLK_TOP_U2_SEL 79 92bda921faSChen Zhong #define CLK_TOP_AUD1_SEL 80 93bda921faSChen Zhong #define CLK_TOP_AUD2_SEL 81 94bda921faSChen Zhong #define CLK_TOP_IRRX_SEL 82 95bda921faSChen Zhong #define CLK_TOP_IRTX_SEL 83 96bda921faSChen Zhong #define CLK_TOP_ASM_L_SEL 84 97bda921faSChen Zhong #define CLK_TOP_ASM_M_SEL 85 98bda921faSChen Zhong #define CLK_TOP_ASM_H_SEL 86 99bda921faSChen Zhong #define CLK_TOP_APLL1_SEL 87 100bda921faSChen Zhong #define CLK_TOP_APLL2_SEL 88 101bda921faSChen Zhong #define CLK_TOP_I2S0_MCK_SEL 89 102bda921faSChen Zhong #define CLK_TOP_I2S1_MCK_SEL 90 103bda921faSChen Zhong #define CLK_TOP_I2S2_MCK_SEL 91 104bda921faSChen Zhong #define CLK_TOP_I2S3_MCK_SEL 92 105bda921faSChen Zhong #define CLK_TOP_APLL1_DIV 93 106bda921faSChen Zhong #define CLK_TOP_APLL2_DIV 94 107bda921faSChen Zhong #define CLK_TOP_I2S0_MCK_DIV 95 108bda921faSChen Zhong #define CLK_TOP_I2S1_MCK_DIV 96 109bda921faSChen Zhong #define CLK_TOP_I2S2_MCK_DIV 97 110bda921faSChen Zhong #define CLK_TOP_I2S3_MCK_DIV 98 111bda921faSChen Zhong #define CLK_TOP_A1SYS_HP_DIV 99 112bda921faSChen Zhong #define CLK_TOP_A2SYS_HP_DIV 100 113bda921faSChen Zhong #define CLK_TOP_APLL1_DIV_PD 101 114bda921faSChen Zhong #define CLK_TOP_APLL2_DIV_PD 102 115bda921faSChen Zhong #define CLK_TOP_I2S0_MCK_DIV_PD 103 116bda921faSChen Zhong #define CLK_TOP_I2S1_MCK_DIV_PD 104 117bda921faSChen Zhong #define CLK_TOP_I2S2_MCK_DIV_PD 105 118bda921faSChen Zhong #define CLK_TOP_I2S3_MCK_DIV_PD 106 119bda921faSChen Zhong #define CLK_TOP_A1SYS_HP_DIV_PD 107 120bda921faSChen Zhong #define CLK_TOP_A2SYS_HP_DIV_PD 108 121bda921faSChen Zhong #define CLK_TOP_NR_CLK 109 122bda921faSChen Zhong 123bda921faSChen Zhong /* INFRACFG */ 124bda921faSChen Zhong 125bda921faSChen Zhong #define CLK_INFRA_MUX1_SEL 0 126bda921faSChen Zhong #define CLK_INFRA_DBGCLK_PD 1 127bda921faSChen Zhong #define CLK_INFRA_AUDIO_PD 2 128bda921faSChen Zhong #define CLK_INFRA_IRRX_PD 3 129bda921faSChen Zhong #define CLK_INFRA_APXGPT_PD 4 130bda921faSChen Zhong #define CLK_INFRA_PMIC_PD 5 131bda921faSChen Zhong #define CLK_INFRA_TRNG 6 132bda921faSChen Zhong #define CLK_INFRA_NR_CLK 7 133bda921faSChen Zhong 134bda921faSChen Zhong /* PERICFG */ 135bda921faSChen Zhong 136bda921faSChen Zhong #define CLK_PERIBUS_SEL 0 137bda921faSChen Zhong #define CLK_PERI_THERM_PD 1 138bda921faSChen Zhong #define CLK_PERI_PWM1_PD 2 139bda921faSChen Zhong #define CLK_PERI_PWM2_PD 3 140bda921faSChen Zhong #define CLK_PERI_PWM3_PD 4 141bda921faSChen Zhong #define CLK_PERI_PWM4_PD 5 142bda921faSChen Zhong #define CLK_PERI_PWM5_PD 6 143bda921faSChen Zhong #define CLK_PERI_PWM6_PD 7 144bda921faSChen Zhong #define CLK_PERI_PWM7_PD 8 145bda921faSChen Zhong #define CLK_PERI_PWM_PD 9 146bda921faSChen Zhong #define CLK_PERI_AP_DMA_PD 10 147bda921faSChen Zhong #define CLK_PERI_MSDC30_0_PD 11 148bda921faSChen Zhong #define CLK_PERI_MSDC30_1_PD 12 149bda921faSChen Zhong #define CLK_PERI_UART0_PD 13 150bda921faSChen Zhong #define CLK_PERI_UART1_PD 14 151bda921faSChen Zhong #define CLK_PERI_UART2_PD 15 152bda921faSChen Zhong #define CLK_PERI_UART3_PD 16 153bda921faSChen Zhong #define CLK_PERI_UART4_PD 17 154bda921faSChen Zhong #define CLK_PERI_BTIF_PD 18 155bda921faSChen Zhong #define CLK_PERI_I2C0_PD 19 156bda921faSChen Zhong #define CLK_PERI_I2C1_PD 20 157bda921faSChen Zhong #define CLK_PERI_I2C2_PD 21 158bda921faSChen Zhong #define CLK_PERI_SPI1_PD 22 159bda921faSChen Zhong #define CLK_PERI_AUXADC_PD 23 160bda921faSChen Zhong #define CLK_PERI_SPI0_PD 24 161bda921faSChen Zhong #define CLK_PERI_SNFI_PD 25 162bda921faSChen Zhong #define CLK_PERI_NFI_PD 26 163bda921faSChen Zhong #define CLK_PERI_NFIECC_PD 27 164bda921faSChen Zhong #define CLK_PERI_FLASH_PD 28 165bda921faSChen Zhong #define CLK_PERI_IRTX_PD 29 166bda921faSChen Zhong #define CLK_PERI_NR_CLK 30 167bda921faSChen Zhong 168bda921faSChen Zhong /* APMIXEDSYS */ 169bda921faSChen Zhong 170bda921faSChen Zhong #define CLK_APMIXED_ARMPLL 0 171bda921faSChen Zhong #define CLK_APMIXED_MAINPLL 1 172bda921faSChen Zhong #define CLK_APMIXED_UNIV2PLL 2 173bda921faSChen Zhong #define CLK_APMIXED_ETH1PLL 3 174bda921faSChen Zhong #define CLK_APMIXED_ETH2PLL 4 175bda921faSChen Zhong #define CLK_APMIXED_AUD1PLL 5 176bda921faSChen Zhong #define CLK_APMIXED_AUD2PLL 6 177bda921faSChen Zhong #define CLK_APMIXED_TRGPLL 7 178bda921faSChen Zhong #define CLK_APMIXED_SGMIPLL 8 179bda921faSChen Zhong #define CLK_APMIXED_MAIN_CORE_EN 9 180bda921faSChen Zhong #define CLK_APMIXED_NR_CLK 10 181bda921faSChen Zhong 182bda921faSChen Zhong /* AUDIOSYS */ 183bda921faSChen Zhong 184bda921faSChen Zhong #define CLK_AUDIO_AFE 0 185bda921faSChen Zhong #define CLK_AUDIO_HDMI 1 186bda921faSChen Zhong #define CLK_AUDIO_SPDF 2 187bda921faSChen Zhong #define CLK_AUDIO_APLL 3 188bda921faSChen Zhong #define CLK_AUDIO_I2SIN1 4 189bda921faSChen Zhong #define CLK_AUDIO_I2SIN2 5 190bda921faSChen Zhong #define CLK_AUDIO_I2SIN3 6 191bda921faSChen Zhong #define CLK_AUDIO_I2SIN4 7 192bda921faSChen Zhong #define CLK_AUDIO_I2SO1 8 193bda921faSChen Zhong #define CLK_AUDIO_I2SO2 9 194bda921faSChen Zhong #define CLK_AUDIO_I2SO3 10 195bda921faSChen Zhong #define CLK_AUDIO_I2SO4 11 196bda921faSChen Zhong #define CLK_AUDIO_ASRCI1 12 197bda921faSChen Zhong #define CLK_AUDIO_ASRCI2 13 198bda921faSChen Zhong #define CLK_AUDIO_ASRCO1 14 199bda921faSChen Zhong #define CLK_AUDIO_ASRCO2 15 200bda921faSChen Zhong #define CLK_AUDIO_INTDIR 16 201bda921faSChen Zhong #define CLK_AUDIO_A1SYS 17 202bda921faSChen Zhong #define CLK_AUDIO_A2SYS 18 203bda921faSChen Zhong #define CLK_AUDIO_UL1 19 204bda921faSChen Zhong #define CLK_AUDIO_UL2 20 205bda921faSChen Zhong #define CLK_AUDIO_UL3 21 206bda921faSChen Zhong #define CLK_AUDIO_UL4 22 207bda921faSChen Zhong #define CLK_AUDIO_UL5 23 208bda921faSChen Zhong #define CLK_AUDIO_UL6 24 209bda921faSChen Zhong #define CLK_AUDIO_DL1 25 210bda921faSChen Zhong #define CLK_AUDIO_DL2 26 211bda921faSChen Zhong #define CLK_AUDIO_DL3 27 212bda921faSChen Zhong #define CLK_AUDIO_DL4 28 213bda921faSChen Zhong #define CLK_AUDIO_DL5 29 214bda921faSChen Zhong #define CLK_AUDIO_DL6 30 215bda921faSChen Zhong #define CLK_AUDIO_DLMCH 31 216bda921faSChen Zhong #define CLK_AUDIO_ARB1 32 217bda921faSChen Zhong #define CLK_AUDIO_AWB 33 218bda921faSChen Zhong #define CLK_AUDIO_AWB2 34 219bda921faSChen Zhong #define CLK_AUDIO_DAI 35 220bda921faSChen Zhong #define CLK_AUDIO_MOD 36 221bda921faSChen Zhong #define CLK_AUDIO_ASRCI3 37 222bda921faSChen Zhong #define CLK_AUDIO_ASRCI4 38 223bda921faSChen Zhong #define CLK_AUDIO_ASRCO3 39 224bda921faSChen Zhong #define CLK_AUDIO_ASRCO4 40 225bda921faSChen Zhong #define CLK_AUDIO_MEM_ASRC1 41 226bda921faSChen Zhong #define CLK_AUDIO_MEM_ASRC2 42 227bda921faSChen Zhong #define CLK_AUDIO_MEM_ASRC3 43 228bda921faSChen Zhong #define CLK_AUDIO_MEM_ASRC4 44 229bda921faSChen Zhong #define CLK_AUDIO_MEM_ASRC5 45 230936ceb12SRyder Lee #define CLK_AUDIO_AFE_CONN 46 231936ceb12SRyder Lee #define CLK_AUDIO_NR_CLK 47 232bda921faSChen Zhong 233bda921faSChen Zhong /* SSUSBSYS */ 234bda921faSChen Zhong 235bda921faSChen Zhong #define CLK_SSUSB_U2_PHY_1P_EN 0 236bda921faSChen Zhong #define CLK_SSUSB_U2_PHY_EN 1 237bda921faSChen Zhong #define CLK_SSUSB_REF_EN 2 238bda921faSChen Zhong #define CLK_SSUSB_SYS_EN 3 239bda921faSChen Zhong #define CLK_SSUSB_MCU_EN 4 240bda921faSChen Zhong #define CLK_SSUSB_DMA_EN 5 241bda921faSChen Zhong #define CLK_SSUSB_NR_CLK 6 242bda921faSChen Zhong 243bda921faSChen Zhong /* PCIESYS */ 244bda921faSChen Zhong 245bda921faSChen Zhong #define CLK_PCIE_P1_AUX_EN 0 246bda921faSChen Zhong #define CLK_PCIE_P1_OBFF_EN 1 247bda921faSChen Zhong #define CLK_PCIE_P1_AHB_EN 2 248bda921faSChen Zhong #define CLK_PCIE_P1_AXI_EN 3 249bda921faSChen Zhong #define CLK_PCIE_P1_MAC_EN 4 250bda921faSChen Zhong #define CLK_PCIE_P1_PIPE_EN 5 251bda921faSChen Zhong #define CLK_PCIE_P0_AUX_EN 6 252bda921faSChen Zhong #define CLK_PCIE_P0_OBFF_EN 7 253bda921faSChen Zhong #define CLK_PCIE_P0_AHB_EN 8 254bda921faSChen Zhong #define CLK_PCIE_P0_AXI_EN 9 255bda921faSChen Zhong #define CLK_PCIE_P0_MAC_EN 10 256bda921faSChen Zhong #define CLK_PCIE_P0_PIPE_EN 11 257bda921faSChen Zhong #define CLK_SATA_AHB_EN 12 258bda921faSChen Zhong #define CLK_SATA_AXI_EN 13 259bda921faSChen Zhong #define CLK_SATA_ASIC_EN 14 260bda921faSChen Zhong #define CLK_SATA_RBC_EN 15 261bda921faSChen Zhong #define CLK_SATA_PM_EN 16 262bda921faSChen Zhong #define CLK_PCIE_NR_CLK 17 263bda921faSChen Zhong 264bda921faSChen Zhong /* ETHSYS */ 265bda921faSChen Zhong 266bda921faSChen Zhong #define CLK_ETH_HSDMA_EN 0 267bda921faSChen Zhong #define CLK_ETH_ESW_EN 1 268bda921faSChen Zhong #define CLK_ETH_GP2_EN 2 269bda921faSChen Zhong #define CLK_ETH_GP1_EN 3 270bda921faSChen Zhong #define CLK_ETH_GP0_EN 4 271bda921faSChen Zhong #define CLK_ETH_NR_CLK 5 272bda921faSChen Zhong 273bda921faSChen Zhong /* SGMIISYS */ 274bda921faSChen Zhong 275bda921faSChen Zhong #define CLK_SGMII_TX250M_EN 0 276bda921faSChen Zhong #define CLK_SGMII_RX250M_EN 1 277bda921faSChen Zhong #define CLK_SGMII_CDR_REF 2 278bda921faSChen Zhong #define CLK_SGMII_CDR_FB 3 279bda921faSChen Zhong #define CLK_SGMII_NR_CLK 4 280bda921faSChen Zhong 281bda921faSChen Zhong #endif /* _DT_BINDINGS_CLK_MT7622_H */ 282bda921faSChen Zhong 283