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Searched refs:CLK_TOP_ETH_SEL (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt7629-clk.h86 #define CLK_TOP_ETH_SEL 76 macro
H A Dmt8516-clk.h175 #define CLK_TOP_ETH_SEL 143 macro
H A Dmt7622-clk.h71 #define CLK_TOP_ETH_SEL 59 macro
H A Dmediatek,mt8365-clk.h109 #define CLK_TOP_ETH_SEL 99 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dmt7629-clk.h90 #define CLK_TOP_ETH_SEL 76 macro
/openbmc/u-boot/arch/arm/dts/
H A Dmt7629.dtsi238 clocks = <&topckgen CLK_TOP_ETH_SEL>,
261 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi443 clocks = <&topckgen CLK_TOP_ETH_SEL>,
466 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt7622.c392 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
H A Dclk-mt8516.c393 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
H A Dclk-mt8167.c572 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
H A Dclk-mt7629.c468 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
H A Dclk-mt8365.c514 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x0d0,
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c367 MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmediatek,net.yaml416 clocks = <&topckgen CLK_TOP_ETH_SEL>,
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8365.dtsi577 clocks = <&topckgen CLK_TOP_ETH_SEL>,
H A Dmt7622.dtsi970 clocks = <&topckgen CLK_TOP_ETH_SEL>,